A Simple Charge Model for Symmetric Double-Gate MOSFETs Adapted to Gate-Oxide-Thickness Asymmetry

Surface-potential-based compact charge models for symmetric double-gate metal-oxide-semiconductor field-effect transistors (SDG-MOSFETs) are based on the fundamental assumption of having equal oxide thicknesses for both gates. However, for practical devices, there will always be some amount of asymmetry between the gate oxide thicknesses due to process variations and uncertainties, which can affect device performance significantly. In this paper, we propose a simple surface-potential-based charge model, which is applicable for tied double-gate MOSFETs having same gate work function but could have any difference in gate oxide thickness. The proposed model utilizes the unique so-far-unexplored quasi-linear relationship between the surface potentials along the channel. In this model, the terminal charges could be computed by basic arithmetic operations from the surface potentials and applied biases, and thus, it could be implemented in any circuit simulator very easily and extendable to short-channel devices. We also propose a simple physics-based perturbation technique by which the surface potentials of an asymmetric device could be obtained just by solving the input voltage equation of SDG devices for small asymmetry cases. The proposed model, which shows excellent agreement with numerical and TCAD simulations, is implemented in a professional circuit simulator through the Verilog-A interface and demonstrated for a 101-stage ring oscillator simulation. It is also shown that the proposed model preserves the source/drain symmetry, which is essential for RF circuit design.

Analytical Field-Effect Method for Extraction of Subgap States in Thin-Film Transistors

We present an analytical field-effect method to extract the density of subgap states (subgap DOS) in amorphous semiconductor thin-film transistors (TFTs), using a closed-form relationship between surface potential and gate voltage. By accounting the interface states in the subthreshold characteristics, the subgap DOS is retrieved, leading to a reasonably accurate description of field-effect mobility and its gate voltage dependence. The method proposed here is very useful not only in extracting device performance but also in physically based compact TFT modeling for circuit simulation.

Optimization of HfO2 films for high transconductance back gated graphene transistors

Hafnium dioxide (HfO2) films, deposited using electron beam evaporation, are optimized for high performance back-gated graphene transistors. Bilayer graphene is identified on HfO2/Si substrate using optical microscope and subsequently confirmed with Raman spectroscopy. Back-gated graphene transistor, with 32 nm thick HfO2 gate dielectric, has been fabricated with very high transconductance value of 60 mu S. From the hysteresis of the current-voltage characteristics, we estimate the trap density in HfO2 to be in the mid 10(11)/cm(2) range, comparable to SiO2.

AIM-Spice Integration of a Recursive Model for Threshold Voltage Shift in Thin Film Transistors

Non-crystalline semiconductor based thin film transistors are the building blocks of large area electronic systems. These devices experience a threshold voltage shift with time due to prolonged gate bias stress. In this paper we integrate a recursive model for threshold voltage shift with the open source BSIM4V4 model of AIM-Spice. This creates a tool for circuit simulation for TFTs. We demonstrate the integrity of the model using several test cases including display driver circuits.

Fourier spectrum based extraction of an equivalent trap state density in indium gallium zinc oxide transistors

Segregating the dynamics of gate bias induced threshold voltage shift, and in particular, charge trapping in thin film transistors (TFTs) based on time constants provides insight into the different mechanisms underlying TFTs instability. In this Letter we develop a representation of the time constants and model the magnitude of charge trapped in the form of an equivalent density of created trap states. This representation is extracted from the Fourier spectrum of the dynamics of charge trapping. Using amorphous In-Ga-Zn-O TFTs as an example, the charge trapping was modeled within an energy range of Delta E-t approximate to 0.3 eV and with a density of state distribution as D-t(Et-j) = D-t0 exp(-Delta E-t/kT) with D-t0 = 5.02 x 10(11) cm(-2) eV(-1). Such a model is useful for developing simulation tools for circuit design. (C) 2014 AIP Publishing LLC.

Design Optimization of Thin-Film Transistors Based on a Metal-Substrate-Semiconductor Architecture for High DC Voltage Sensing

We discuss the potential application of high dc voltage sensing using thin-film transistors (TFTs) on flexible substrates. High voltage sensing has potential applications for power transmission instrumentation. For this, we consider a gate metal-substrate-semiconductor architecture for TFTs. In this architecture, the flexible substrate not only provides mechanical support but also plays the role of the gate dielectric of the TFT. Hence, the thickness of the substrate needs to be optimized for maximizing transconductance, minimizing mechanical stress, and minimizing gate leakage currents. We discuss this optimization, and develop n-type and p-type organic TFTs using polyvinyldene fluoride as the substrate-gate insulator. Circuits are also realized to achieve level shifting, amplification, and high drain voltage operation.

A comparative study of plasma-enhanced chemical vapor gate dielectrics for solution-processed polymer thin-film transistor circuit integration

This paper considers plasma-enhanced chemical vapor deposited (PECVD) silicon nitride (SiNx) and silicon oxide (SiOx) as gate dielectrics for organic thin-film transistors (OTFTs), with solution-processed poly[5, 5′ -bis(3-dodecyl-2-thienyl)-2, 2′ -bithiophene] (PQT-12) as the active semiconductor layer. We examine transistors with SiNx films of varying composition deposited at 300 °C as well as 150 °C for plastic compatibility. The transistors show over 100% (two times) improvement in field-effect mobility as the silicon content in SiNx increases, with mobility (μFE) up to 0.14 cm2 /V s and on/off current ratio (ION / IOFF) of 108. With PECVD SiOx gate dielectric, preliminary devices exhibit a μFE of 0.4 cm2 /V s and ION / IOFF of 108. PQT-12 OTFTs with PECVD SiNx and SiOx gate dielectrics on flexible plastic substrates are also presented. These results demonstrate the viability of using PECVD SiN x and SiOx as gate dielectrics for OTFT circuit integration, where the low temperature and large area deposition capabilities of PECVD films are highly amenable to integration of OTFT circuits targeted for flexible and lightweight applications. © 2008 American Institute of Physics.

Persistent photoconductivity in Hf-In-Zn-O thin film transistors

Passivated Hf-In-Zn-O (HIZO) thin film transistors suffer from a negative threshold voltage shift under visible light stress due to persistent photoconductivity (PPC). Ionization of oxygen vacancy sites is identified as the origin of the PPC following observations of its temperature- and wavelength-dependence. This is further corroborated by the photoluminescence spectrum of the HIZO. We also show that the gate voltage can control the decay of PPC in the dark, giving rise to a memory action. © 2010 American Institute of Physics.

Direct growth of horizontally aligned carbon nanotubes between electrodes and its application to field-effect transistors

This paper presents direct growth of horizontally aligned carbon nanotubes (CNTs) between two predefined various inter-spacing up to tens of microns of electrodes (pads) and its use as CNT field-effect transistors (CNT-FETs). The catalytic metals were prepared, consisting of iron (Fe), aluminum (Al) and platinum (Pt) triple layers, on the thermal silicon oxide substrate (Pt/Al/Fe/SiO2). Scanning electron microscopy measurements of CNT-FETs from the as-grown samples showed that over 80% of the nanotubes are grown across the catalytic electrodes. Moreover, the number of CNTs across the catalytic electrodes is roughly controllable by adjusting the growth condition. The Al, as the upper layer on Fe electrode, not only plays a role as a barrier to prevent vertical growth but also serves as a porous medium that helps in forming smaller nano-sized Fe particles which would be necessary for lateral growth of CNTs. Back-gate field effect transistors were demonstrated with the laterally aligned CNTs. The on/off ratios in all the measured devices are lower than 100 due to the drain leakage current. ©2010 IEEE.

Tuning of the electronic characteristics of ZnO nanowire field effect transistors by proton irradiation.

We demonstrated a controllable tuning of the electronic characteristics of ZnO nanowire field effect transistors (FETs) using a high-energy proton beam. After a short proton irradiation time, the threshold voltage shifted to the negative gate bias direction with an increase in the electrical conductance, whereas the threshold voltage shifted to the positive gate bias direction with a decrease in the electrical conductance after a long proton irradiation time. The electrical characteristics of two different types of ZnO nanowires FET device structures in which the ZnO nanowires are placed on the substrate or suspended above the substrate and photoluminescence (PL) studies of the ZnO nanowires provide substantial evidence that the experimental observations result from the irradiation-induced charges in the bulk SiO(2) and at the SiO(2)/ZnO nanowire interface, which can be explained by a surface-band-bending model in terms of gate electric field modulation. Our study on the proton-irradiation-mediated functionalization can be potentially interesting not only for understanding the proton irradiation effects on nanoscale devices, but also for creating the property-tailored nanoscale devices.

Nonvolatile memory functionality of ZnO nanowire transistors controlled by mobile protons.

We demonstrated the nonvolatile memory functionality of ZnO nanowire field effect transistors (FETs) using mobile protons that are generated by high-pressure hydrogen annealing (HPHA) at relatively low temperature (400 °C). These ZnO nanowire devices exhibited reproducible hysteresis, reversible switching, and nonvolatile memory behaviors in comparison with those of the conventional FET devices. We show that the memory characteristics are attributed to the movement of protons between the Si/SiO(2) interface and the SiO(2)/ZnO nanowire interface by the applied gate electric field. The memory mechanism is explained in terms of the tuning of interface properties, such as effective electric field, surface charge density, and surface barrier potential due to the movement of protons in the SiO(2) layer, consistent with the UV photoresponse characteristics of nanowire memory devices. Our study will further provide a useful route of creating memory functionality and incorporating proton-based storage elements onto a modified CMOS platform for FET memory devices using nanomaterials.

Correlation between density of states distributions and the fermi level position in interfacial regions of amorphous silicon thin film transistors

This paper investigates the variation of the integrated density of states with conduction activation energy in hydrogenated amorphous silicon thin film transistors. Results are given for two different gate insulator layers, PECVD silicon oxide and thermally grown silicon dioxide. The different gate insulators produce transistors with very different initial transfer characteristics, but the variation of integrated density of states with conduction activation energy is shown to be similar.

MOS and bipolar gated thyristor: A thyristor with IGBT switching characteristics

The IGBT has become the device of choice in many high-voltage-power electronic applications, by virtue of combining the ease of MOS gate control with an acceptable forward voltage drop. However, designers have retained an interest in MOS gated thyristor structures which have a turn-off capability. These offer low on-state losses as a result of their latching behaviour. Recently, there have been various proposals for dual-gate devices that have a thyristor on-state with IGBT-like switching. Many of these dual gated structures rely on advanced MOS technology, with inherent manufacturing difficulties. The MOS and bipolar gated thyristor offers all the advantages of dual gated performance, while employing standard IGBT processing techniques. The paper describes the MBGT in detail, and presents experimental and simulation results for devices based on realistic commercial processes. It is shown that the MBGT represents a viable power semiconductor device technology, suitable for a diverse range of applications. © IEE, 1998.

Characterization of defect removal in hydrogenated and deuterated amorphous silicon thin film transistors

Thin film transistors (TFTs) utilizing an hydrogenated amorphous silicon (a-Si:H) channel layer exhibit a shift in the threshold voltage with time under the application of a gate bias voltage due to the creation of metastable defects. These defects are removed by annealing the device with zero gate bias applied. The defect removal process can be characterized by a thermalization energy which is, in turn, dependent upon an attempt-to-escape frequency for defect removal. The threshold voltage of both hydrogenated and deuterated amorphous silicon (a-Si:D) TFTs has been measured as a function of annealing time and temperature. Using a molecular dynamics simulation of hydrogen and deuterium in a silicon network in the H2 * configuration, it is shown that the experimental results are consistent with an attempt-to-escape frequency of (4.4 ± 0.3) × 1013 Hz and (5.7 ± 0.3) × 1013 Hz for a-Si:H and a-Si:D respectively which is attributed to the oscillation of the Si-H and Si-D bonds. Using this approach, it becomes possible to describe defect removal in hydrogenated and deuterated material by the thermalization energies of (1.552 ± 0.003) eV and (1.559 ± 0.003) eV respectively. This correlates with the energy per atom of the Si-H and Si-D bonds. © 2006 Elsevier B.V. All rights reserved.

Self-aligned high-resolution printed polymer transistors

A process to fabricate solution-processable thin-film transistors (TFTs) with a one-step self-aligned definition of the dimensions in all functional layers is demonstrated. The TFT-channel, semiconductor materials, and effective gate dimention of different layers are determined by a one-step imprint process and the subsequent pattern transfer without the need for multiple patterning and mask alignment. The process is compatible with fabrication of large-scale circuits. Copyright © 2011 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.