Enhancement of fatigue life of Ni-Ti-Fe shape memory alloys by thermal cycling

The effect of thermal cycling on the load-controlled tension-tension fatigue behavior of a Ni-Ti-Fe shape memory alloy (SMA) at room temperature was studied. Considerable strain accumulation was observed to occur in this alloy under both quasi-static and cyclic loading conditions. Though, in all cases, steady-state is reached within the first 50-100 cycles, the accumulated steady-state strain, epsilon(p.ss), is much smaller in thermally cycled alloy. As a result, the fatigue performance of them was found to be significantly enhanced vis-a-vis the as-solutionized alloy. Furthermore, under load-controlled conditions, the fatigue life of Ni-Ti-Fe alloys was found to be exclusively dependent on epsilon(p.ss). Observations made by profilometry and differential scanning calorimetry (DSC) indicate that the 200-500% enhancement in fatigue life of thermally cycled alloy is due to the homogeneous distribution of the accumulated fatigue strain. (C) 2010 Elsevier B.V. All rights reserved.

Some experiments on human memory and a new neural model

An associative memory with parallel architecture is presented. The neurons are modelled by perceptrons having only binary, rather than continuous valued input. To store m elements each having n features, m neurons each with n connections are needed. The n features are coded as an n-bit binary vector. The weights of the n connections that store the n features of an element has only two values -1 and 1 corresponding to the absence or presence of a feature. This makes the learning very simple and straightforward. For an input corrupted by binary noise, the associative memory indicates the element that is closest (in terms of Hamming distance) to the noisy input. In the case where the noisy input is equidistant from two or more stored vectors, the associative memory indicates two or more elements simultaneously. From some simple experiments performed on the human memory and also on the associative memory, it can be concluded that the associative memory presented in this paper is in some respect more akin to a human memory than a Hopfield model.

Influence of Substrate Temperature and Deposition Rate on Structural and Mechanical Properties of Shape Memory NiTi Films

NiTi thin films deposited by DC magnetron sputtering of an alloy (Ni/Ti:45/55) target at different deposition rates and substrate temperatures were analyzed for their structure and mechanical properties. The crystalline structure, phase-transformation and mechanical response were characterized by X-ray diffraction (XRD), Differential Scanning Calorimetry (DSC) and Nano-indentation techniques, respectively. The films were deposited on silicon substrates maintained at temperatures in the range 300 to 500 degrees C and post-annealed at 600 degrees C for four hours to ensure film crystallinity. Films deposited at 300 degrees C and annealed for 600 degrees C have exhibited crystalline behavior with Austenite phase as the prominent phase. Deposition onto substrates held at higher deposition temperatures (400 and 500 degrees C) resulted in the co-existence of Austenite phase along with Martensite phase. The increase in deposition rates corresponding to increase in cathode current from 250 to 350 mA has also resulted in the appearance of Martensite phase as well as improvement in crystallinity. XRD analysis revealed that the crystalline film structure is strongly influenced by process parameters such as substrate temperature and deposition rate. DSC results indicate that the film deposited at 300 degrees C had its crystallization temperature at 445 degrees C in the first thermal cycle, which is further confirmed by stress temperature response. In the second thermal cycle the Austenite and Martensite transitions were observed at 75 and 60 degrees C respectively. However, the films deposited at 500 degrees C had the Austenite and Martensite transitions at 73 and 58 degrees C, respectively. Elastic modulus and hardness values increased from 93 to 145 GPa and 7.2 to 12.6 GPa, respectively, with increase in deposition rates. These results are explained on the basis of change in film composition and crystallization. (C) 2010 Published by Elsevier Ltd

Memory Bandwidth and Power Reduction Using Lossy Reference Frame Compression in Video Encoding

Large external memory bandwidth requirement leads to increased system power dissipation and cost in video coding application. Majority of the external memory traffic in video encoder is due to reference data accesses. We describe a lossy reference frame compression technique that can be used in video coding with minimal impact on quality while significantly reducing power and bandwidth requirement. The low cost transformless compression technique uses lossy reference for motion estimation to reduce memory traffic, and lossless reference for motion compensation (MC) to avoid drift. Thus, it is compatible with all existing video standards. We calculate the quantization error bound and show that by storing quantization error separately, bandwidth overhead due to MC can be reduced significantly. The technique meets key requirements specific to the video encode application. 24-39% reduction in peak bandwidth and 23-31% reduction in total average power consumption are observed for IBBP sequences.

Pulsed laser deposition of strontium titanate thin films for dynamic random access memory applications

Polycrystalline strontium titanate (SrTiO3) films were prepared by a pulsed laser deposition technique on p-type silicon and platinum-coated silicon substrates. The films exhibited good structural and dielectric properties which were sensitive to the processing conditions. The small signal dielectric constant and dissipation factor at a frequency of 100 kHz were about 225 and 0.03 respectively. The capacitance-voltage (C-V) characteristics in metal-insulator-semiconductor structures exhibited anomalous frequency dispersion behavior and a hysteresis effect. The hysteresis in the C-V curve was found to be about 1 V and of a charge injection type. The density of interface states was about 1.79 x 10(12) cm(-2). The charge storage density was found to be 40 fC mu m(-2) at an applied electric field of 200 kV cm(-1). Studies on current-voltage characteristics indicated an ohmic nature at lower voltages and space charge conduction at higher voltages. The films also exhibited excellent time-dependent dielectric breakdown behavior.

A Flat Concurrent Prolog compiler for PARAM

We describe a compiler for the Flat Concurrent Prolog language on a message passing multiprocessor architecture. This compiler permits symbolic and declarative programming in the syntax of Guarded Horn Rules, The implementation has been verified and tested on the 64-node PARAM parallel computer developed by C-DAC (Centre for the Development of Advanced Computing, India), Flat Concurrent Prolog (FCP) is a logic programming language designed for concurrent programming and parallel execution, It is a process oriented language, which embodies dataflow synchronization and guarded-command as its basic control mechanisms. An identical algorithm is executed on every processor in the network, We assume regular network topologies like mesh, ring, etc, Each node has a local memory, The algorithm comprises of two important parts: reduction and communication, The most difficult task is to integrate the solutions of problems that arise in the implementation in a coherent and efficient manner. We have tested the efficacy of the compiler on various benchmark problems of the ICOT project that have been reported in the recent book by Evan Tick, These problems include Quicksort, 8-queens, and Prime Number Generation, The results of the preliminary tests are favourable, We are currently examining issues like indexing and load balancing to further optimize our compiler.

Neural network modeling of associative memory: Beyond the Hopfield model

A number of neural network models, in which fixed-point and limit-cycle attractors of the underlying dynamics are used to store and associatively recall information, are described. In the first class of models, a hierarchical structure is used to store an exponentially large number of strongly correlated memories. The second class of models uses limit cycles to store and retrieve individual memories. A neurobiologically plausible network that generates low-amplitude periodic variations of activity, similar to the oscillations observed in electroencephalographic recordings, is also described. Results obtained from analytic and numerical studies of the properties of these networks are discussed.

A Comparative Study of Electrical Switching Behavior of Certain Tellurium based Chalcogenide Thin Films for Phase Change Memory (PCM) Applications

This work describes the electrical switching behavior of three telluride based amorphous chalcogenide thin film samples, Al-Te, Ge-Se-Te and Ge-Te-Si. These amorphous thin films are made using bulk glassy ingots, prepared by conventional melt quenching technique, using flash evaporation technique; while Al-Te sample has been coated in coplanar electrode geometry, Ge-Se-Te and Ge-Te-Si samples have been deposited with sandwich electrodes. It is observed that all the three samples studied, exhibit memory switching behavior in thin film form, with Ge-Te-Si sample exhibiting a faster switching characteristic. The difference seen in the switching voltages of the three samples studied has been understood on the basis of difference in device geometry and thickness. Scanning electron microscopic image of switched region of a representative Ge15Te81Si4 sample shows a structural change and formation of crystallites in the electrode region, which is responsible for making a conducting channel between the two electrodes during switching.

WOMM: A Weak Operational Memory Model

Memory models of shared memory concurrent programs define the values a read of a shared memory location is allowed to see. Such memory models are typically weaker than the intuitive sequential consistency semantics to allow efficient execution. In this paper, we present WOMM (abbreviation for Weak Operational Memory Model) that formally unifies two sources of weak behavior in hardware memory models: reordering of instructions and weakly consistent memory. We show that a large number of optimizations are allowed by WOMM. We also show that WOMM is weaker than a number of hardware memory models. Consequently, if a program behaves correctly under WOMM, it will be correct with respect to those hardware memory models. Hence, WOMM can be used as a formally specified abstraction of the hardware memory models. Moreover; unlike most weak memory models, WOMM is described using operational semantics, making it easy to integrate into a model checker for concurrent programs. We further show that WOMM has an important property - it has sequential consistency semantics for datarace-free programs.

Low electric field, easily reversible electrical set and reset processes in a Ge15Te83Si2 glass for phase change memory applications

We report here an easily reversible set-reset process in a new Ge15Te83Si2 glass that could be a promising candidate for phase change random access memory applications. The I-V characteristics of the studied sample show a comparatively low threshold electric field (E-th) of 7.3 kV/cm. Distinct differences in the type of switching behavior are achieved by means of controlling the on state current. It enables the observation of a threshold type for less than 0.7 mA beyond memory type (set) switching. The set and reset processes have been achieved with a similar magnitude of 1 mA, and with a triangular current pulse for the set process and a short duration rectangular pulse of 10 msec width for the reset operation. Further, a self-resetting effect is seen in this material upon excitation with a saw-tooth/square pulse, and their response of leading and trailing edges are discussed. About 6.5 x 10(4) set-reset cycles have been undertaken without any damage to the device. (C) 2011 American Institute of Physics. doi: 10.1063/1.3574659]

Hierarchical Directory-Based Shared Memory Architecture

We describe the design of a directory-based shared memory architecture on a hierarchical network of hypercubes. The distributed directory scheme comprises two separate hierarchical networks for handling cache requests and transfers. Further, the scheme assumes a single address space and each processing element views the entire network as contiguous memory space. The size of individual directories stored at each node of the network remains constant throughout the network. Although the size of the directory increases with the network size, the architecture is scalable. The results of the analytical studies demonstrate superior performance characteristics of our scheme compared with those of other schemes.

On the problem of spurious patterns in neural associative memory models

The problem of spurious patterns in neural associative memory models is discussed, Some suggestions to solve this problem from the literature are reviewed and their inadequacies are pointed out, A solution based on the notion of neural self-interaction with a suitably chosen magnitude is presented for the Hebb learning rule. For an optimal learning rule based on linear programming, asymmetric dilution of synaptic connections is presented as another solution to the problem of spurious patterns, With varying percentages of asymmetric dilution it is demonstrated numerically that this optimal learning rule leads to near total suppression of spurious patterns. For practical usage of neural associative memory networks a combination of the two solutions with the optimal learning rule is recommended to be the best proposition.

Network Error Correction for Unit-Delay, Memory-Free Networks Using Convolutional Codes

A single source network is said to be memory-free if all of the internal nodes (those except the source and the sinks) do not employ memory but merely send linear combinations of the symbols received at their incoming edges on their outgoing edges. In this work, we introduce network-error correction for single source, acyclic, unit-delay, memory-free networks with coherent network coding for multicast. A convolutional code is designed at the source based on the network code in order to correct network- errors that correspond to any of a given set of error patterns, as long as consecutive errors are separated by a certain interval which depends on the convolutional code selected. Bounds on this interval and the field size required for constructing the convolutional code with the required free distance are also obtained. We illustrate the performance of convolutional network error correcting codes (CNECCs) designed for the unit-delay networks using simulations of CNECCs on an example network under a probabilistic error model.