Parallel GPU architecture for hyperspectral unmixing based on augmented Lagrangian method

Hyperspectral imaging has become one of the main topics in remote sensing applications, which comprise hundreds of spectral bands at different (almost contiguous) wavelength channels over the same area generating large data volumes comprising several GBs per flight. This high spectral resolution can be used for object detection and for discriminate between different objects based on their spectral characteristics. One of the main problems involved in hyperspectral analysis is the presence of mixed pixels, which arise when the spacial resolution of the sensor is not able to separate spectrally distinct materials. Spectral unmixing is one of the most important task for hyperspectral data exploitation. However, the unmixing algorithms can be computationally very expensive, and even high power consuming, which compromises the use in applications under on-board constraints. In recent years, graphics processing units (GPUs) have evolved into highly parallel and programmable systems. Specifically, several hyperspectral imaging algorithms have shown to be able to benefit from this hardware taking advantage of the extremely high floating-point processing performance, compact size, huge memory bandwidth, and relatively low cost of these units, which make them appealing for onboard data processing. In this paper, we propose a parallel implementation of an augmented Lagragian based method for unsupervised hyperspectral linear unmixing on GPUs using CUDA. The method called simplex identification via split augmented Lagrangian (SISAL) aims to identify the endmembers of a scene, i.e., is able to unmix hyperspectral data sets in which the pure pixel assumption is violated. The efficient implementation of SISAL method presented in this work exploits the GPU architecture at low level, using shared memory and coalesced accesses to memory.

Multiagent System Architecture for Short-term Operation of Integrated Microgrids

The forthcoming smart grids are comprised of integrated microgrids operating in grid-connected and isolated mode with local generation, storage and demand response (DR) programs. The proposed model is based on three successive complementary steps for power transaction in the market environment. The first step is characterized as a microgrid’s internal market; the second concerns negotiations between distinct interconnected microgrids; and finally, the third refers to the actual electricity market. The proposed approach is modeled and tested using a MAS framework directed to the study of the smart grids environment, including the simulation of electricity markets. This is achieved through the integration of the proposed approach with the MASGriP (Multi-Agent Smart Grid Platform) system.

Energy-aware task mapping onto heterogeneous platforms using DVFS and sleep states

Heterogeneous multicore platforms are becoming an interesting alternative for embedded computing systems with limited power supply as they can execute specific tasks in an efficient manner. Nonetheless, one of the main challenges of such platforms consists of optimising the energy consumption in the presence of temporal constraints. This paper addresses the problem of task-to-core allocation onto heterogeneous multicore platforms such that the overall energy consumption of the system is minimised. To this end, we propose a two-phase approach that considers both dynamic and leakage energy consumption: (i) the first phase allocates tasks to the cores such that the dynamic energy consumption is reduced; (ii) the second phase refines the allocation performed in the first phase in order to achieve better sleep states by trading off the dynamic energy consumption with the reduction in leakage energy consumption. This hybrid approach considers core frequency set-points, tasks energy consumption and sleep states of the cores to reduce the energy consumption of the system. Major value has been placed on a realistic power model which increases the practical relevance of the proposed approach. Finally, extensive simulations have been carried out to demonstrate the effectiveness of the proposed algorithm. In the best-case, savings up to 18% of energy are reached over the first fit algorithm, which has shown, in previous works, to perform better than other bin-packing heuristics for the target heterogeneous multicore platform.

Intra-Task Device Scheduling for Real-Time Embedded Systems

An ever increasing need for extra functionality in a single embedded system demands for extra Input/Output (I/O) devices, which are usually connected externally and are expensive in terms of energy consumption. To reduce their energy consumption, these devices are equipped with power saving mechanisms. While I/O device scheduling for real-time (RT) systems with such power saving features has been studied in the past, the use of energy resources by these scheduling algorithms may be improved. Technology enhancements in the semiconductor industry have allowed the hardware vendors to reduce the device transition and energy overheads. The decrease in overhead of sleep transitions has opened new opportunities to further reduce the device energy consumption. In this research effort, we propose an intra-task device scheduling algorithm for real-time systems that wakes up a device on demand and reduces its active time while ensuring system schedulability. This intra-task device scheduling algorithm is extended for devices with multiple sleep states to further minimise the overall device energy consumption of the system. The proposed algorithms have less complexity when compared to the conservative inter-task device scheduling algorithms. The system model used relaxes some of the assumptions commonly made in the state-of-the-art that restrict their practical relevance. Apart from the aforementioned advantages, the proposed algorithms are shown to demonstrate the substantial energy savings.

TEA: Timing and Energy Aware compression architecture for Efficient Configuration in CGRAs

Coarse Grained Reconfigurable Architectures (CGRAs) are emerging as enabling platforms to meet the high performance demanded by modern applications (e.g. 4G, CDMA, etc.). Recently proposed CGRAs offer time-multiplexing and dynamic applications parallelism to enhance device utilization and reduce energy consumption at the cost of additional memory (up to 50% area of the overall platform). To reduce the memory overheads, novel CGRAs employ either statistical compression, intermediate compact representation, or multicasting. Each compaction technique has different properties (i.e. compression ratio, decompression time and decompression energy) and is best suited for a particular class of applications. However, existing research only deals with these methods separately. Moreover, they only analyze the compaction ratio and do not evaluate the associated energy overheads. To tackle these issues, we propose a polymorphic compression architecture that interleaves these techniques in a unique platform. The proposed architecture allows each application to take advantage of a separate compression/decompression hierarchy (consisting of various types and implementations of hardware/software decoders) tailored to its needs. Simulation results, using different applications (FFT, Matrix multiplication, and WLAN), reveal that the choice of compression hierarchy has a significant impact on compression ratio (up to 52%), decompression energy (up to 4 orders of magnitude), and configuration time (from 33 n to 1.5 s) for the tested applications. Synthesis results reveal that introducing adaptivity incurs negligible additional overheads (1%) compared to the overall platform area.

A Novel Run-Time Monitoring Architecture for Safe and Efficient Inline Monitoring

20th International Conference on Reliable Software Technologies - Ada-Europe 2015 (Ada-Europe 2015), Madrid, Spain.

A module for the XDense architecture in ns-3

Demo in Workshop on ns-3 (WNS3 2015). 13 to 14, May, 2015. Castelldefels, Spain.

A Novel Runtime Monitoring Architecture

Poster presented in 28th GI/ITG International Conference on Architecture of Computing Systems (ARCS 2015). 25 to 28, Mar, 2015, Poster Session. Porto, Portugal.

Architecture to Support Quality of Service in Arrowhead Systems

Presented at INForum - Simpósio de Informática (INFORUM 2015). 7 to 8, Sep, 2015. Covilhã, Portugal.

Run-time Monitoring Architecture for RealTime Systems

Presented at INForum - Simpósio de Informática (INFORUM 2015). 7 to 8, Sep, 2015. Portugal.

Detrimental role of prolonged sleep deprivation on adult neurogenesis

Adult mammalian brains continuously generate new neurons, a phenomenon called adult neurogenesis. Both environmental stimuli and endogenous factors are important regulators of adult neurogenesis. Sleep has an important role in normal brain physiology and its disturbance causes very stressful conditions, which disrupt normal brain physiology. Recently, an influence of sleep in adult neurogenesis has been established, mainly based on sleep deprivation studies. This review provides an overview on how rhythms and sleep cycles regulate hippocampal and subventricular zone neurogenesis, discussing some potential underlying mechanisms. In addition, our review highlights some interacting points between sleep and adult neurogenesis in brain function, such as learning, memory, and mood states, and provides some insights on the effects of antidepressants and hypnotic drugs on adult neurogenesis.

Crowdsourcing innovation: a proposal for a brokering architecture focused in the innovation needs of SMEs

Crowdsourcing is evolving into powerful outsourcing options for organizations by providing access to the intellectual capital within a vast knowledge community. Innovation brokering services have emerged to facilitate crowdsourcing projects by connecting up companies with potential solution providers within the wider ‘crowd’. Most existing innovation brokering services are primarily aimed at larger organizations, however, Small and Medium Enterprises (SMEs) offer considerable potential for crowdsourcing activity since they are typically the innovation and employment engines in society; they are typically more nimble and responsive to the business environment than the larger companies. SMEs have very different challenges and needs to larger organizations since they have fewer resources, a more limited knowledge and skill base, and immature management practices. Consequently, innovation brokering for SMEs require considerably more support than for larger organizations. This paper identifies the crowdsourcing innovation brokerage facilities needed by SMEs, and presents an architecture that encourages knowledge sharing, development of community, support in mixing and matching capabilities, and management of stakeholders’ risks. Innovation brokering is emerging as a novel business model that is challenging concepts of the traditional value chain and organizational boundaries.

An agent based architecture for material handling systems

Dissertação para obtenção do Grau de Mestre em Engenharia Electrotécnica e de Computadores

Service-oriented architecture for device lifecycle support in industrial automation

Dissertação para obtenção do Grau de Doutor em Engenharia Electrotécnica e de Computadores Especialidade: Robótica e Manufactura Integrada

The stone and the cross. Indo-Portuguese Jesuit Architecture in Ethiopia. 1603-33

A fundação de uma missão jesuita no Norte da Etiópia em 1603, na província do Tigré, pelo enérgico Pe. Pero Pais, S. J. teólogo, construtor e historiador vindo de Goa, tomou um forte impulso com a aliança pretendida com os Portugueses pelo imperador Susénios (1619-20) para o apoio militar contra os muçulmanos; e, sobretudo, após a sua conversão oficial à Igreja Católica Romana, em 1626. Uma dúzia de inovadores edifícios foram então construídos pelos Jesuítas na região paradisíaca em torno do Lago Tana: basílicas, igrejas, palácios e jardins, complexos palatinos e eclesiásticos, colégios, etc. A tipologia em cruz latina e ornatos incisos é deliberadamente diferente das igrejas ortodoxas etíopes, circulares e em madeira. A técnica de construção em pedra e cal, ignorada na Etiópia, significou uma revolução. No presente texto procura-se determinar a quem deve ser atribuído este inédito surto construtivo, deixando de lado as teorias tradicionais de pedreiros vindos de Portugal ou de construtores locais. Com base na evidência estilística e em referências de textos da época, atribui-se a inovação a padres e “irmãos” jesuitas com experiência de arquitectos na Índia portuguesa e a construtores de Goa e de Diu, definindo a arte portuguesa na Etiópia como uma província da arquitectura indo-portuguesa na Índia, prosseguida após a expulsão dos Jesuítas (1633) com os “castelos portugueses”, ou paços acastelados da nova capital, Gondar.