Formation of highly conductive composite coatings and their applications to broadband antennas and mechanical transducers

Tight networks of interwoven carbon nanotube bundles are formed in our highly conductive composite. The composite possesses propertiessuggesting a two-dimensional percolative network rather than other reported dispersions displaying three-dimensional networks. Binding nanotubes into large but tight bundles dramatically alters the morphology and electronic transport dynamics of the composite. This enables itto carry higher levels of charge in the macroscale leading to conductivities as high as 1600 S/cm. We now discuss in further detail, the electronic and physical properties of the nanotube composites through Raman spectroscopy and transmission electron microscopy analysis. When controlled and usedappropriately, the interesting properties of these composites reveal their potential for practical device applications. For instance, we used this composite to fabricate coatings, whic improve the properties of an electromagnetic antenna/amplifier transducer. The resulting transducer possesses a broadband range up to GHz frequencies. A strain gauge transducer was also fabricated using changes in conductivity to monitor structural deformations in the composite coatings.

Analysis and design of beam-shaped rectangular polyrod antennas

Theoretical and experimental investigations on the near field and radiation characteristics show a fairly good agreement which justifies the TE(11)(x) mode of excitation. Eight polyrod antennas of different configurations were built and tested as functions of taper angles, straight and curved axial lengths, and frequency of excitation. It is found that the radiation patterns. cross-polarization level, beamwidth and gain could be controlled not only by the axial length and taper angles but also by shaping the axis of the polyrods in order to realize an optimum design

Broadband Suspended Microstrip Antenna For Circular Polarization

In this paper we propose a circularly polarized (CP) microstrip antenna on a suspended substrate with a coplanar capacitive feed and a slot within the rectangular patch. The antenna has an axial ratio bandwidth (< 3 dB) of 7.1%. The proposed antenna exhibits a much higher impedance bandwidth of about 49% (S11 < -10 dB) and also yields return loss better than -15 dB in the useful range of circular polarization. Measured characteristics of the antenna are in good agreement with the simulated results. The radiation patterns indicate good cross polarization rejection and low back lobe radiations. The design proposed here can be scaled to any frequency of interest.

Within-Die Gate Delay Variability Measurement Using Reconfigurable Ring Oscillator

We report the design and characterization of a circuit technique to measure the on-chip delay of an individual logic gate (both inverting and noninverting) in its unmodified form. The test circuit comprises of digitally reconfigurable ring oscillator (RO). The gate under test is embedded in each stage of the ring oscillator. A system of linear equations is then formed with different configuration settings of the RO, relating the individual gate delay to the measured period of the RO, whose solution gives the delay of the individual gates. Experimental results from a test chip in 65-nm process node show the feasibility of measuring the delay of an individual inverter to within 1 ps accuracy. Delay measurements of different nominally identicall inverters in close physical proximity show variations of up to 28% indicating the large impact of local variations. As a demonstration of this technique, we have studied delay variation with poly-pitch, length of diffusion (LOD) and different orientations of layout in silicon. The proposed technique is quite suitable for early process characterization, monitoring mature process in manufacturing and correlating model-to-hardware.

Compiling Techniques for Coarse Grained Runtime Reconfigurable Architectures

In this paper we develop compilation techniques for the realization of applications described in a High Level Language (HLL) onto a Runtime Reconfigurable Architecture. The compiler determines Hyper Operations (HyperOps) that are subgraphs of a data flow graph (of an application) and comprise elementary operations that have strong producer-consumer relationship. These HyperOps are hosted on computation structures that are provisioned on demand at runtime. We also report compiler optimizations that collectively reduce the overheads of data-driven computations in runtime reconfigurable architectures. On an average, HyperOps offer a 44% reduction in total execution time and a 18% reduction in management overheads as compared to using basic blocks as coarse grained operations. We show that HyperOps formed using our compiler are suitable to support data flow software pipelining.

Redefine: Runtime Reconfigurable Polymorphic ASIC

Emerging embedded applications are based on evolving standards (e.g., MPEG2/4, H.264/265, IEEE802.11a/b/g/n). Since most of these applications run on handheld devices, there is an increasing need for a single chip solution that can dynamically interoperate between different standards and their derivatives. In order to achieve high resource utilization and low power dissipation, we propose REDEFINE, a polymorphic ASIC in which specialized hardware units are replaced with basic hardware units that can create the same functionality by runtime re-composition. It is a ``future-proof'' custom hardware solution for multiple applications and their derivatives in a domain. In this article, we describe a compiler framework and supporting hardware comprising compute, storage, and communication resources. Applications described in high-level language (e.g., C) are compiled into application substructures. For each application substructure, a set of compute elements on the hardware are interconnected during runtime to form a pattern that closely matches the communication pattern of that particular application. The advantage is that the bounded CEs are neither processor cores nor logic elements as in FPGAs. Hence, REDEFINE offers the power and performance advantage of an ASIC and the hardware reconfigurability and programmability of that of an FPGA/instruction set processor. In addition, the hardware supports custom instruction pipelining. Existing instruction-set extensible processors determine a sequence of instructions that repeatedly occur within the application to create custom instructions at design time to speed up the execution of this sequence. We extend this scheme further, where a kernel is compiled into custom instructions that bear strong producer-consumer relationship (and not limited to frequently occurring sequences of instructions). Custom instructions, realized as hardware compositions effected at runtime, allow several instances of the same to be active in parallel. A key distinguishing factor in majority of the emerging embedded applications is stream processing. To reduce the overheads of data transfer between custom instructions, direct communication paths are employed among custom instructions. In this article, we present the overview of the hardware-aware compiler framework, which determines the NoC-aware schedule of transports of the data exchanged between the custom instructions on the interconnect. The results for the FFT kernel indicate a 25% reduction in the number of loads/stores, and throughput improves by log(n) for n-point FFT when compared to sequential implementation. Overall, REDEFINE offers flexibility and a runtime reconfigurability at the expense of 1.16x in power and 8x in area when compared to an ASIC. REDEFINE implementation consumes 0.1x the power of an FPGA implementation. In addition, the configuration overhead of the FPGA implementation is 1,000x more than that of REDEFINE.

A Compact Defected Ground Microstrip Device with Photonic Bandgap Effects

Filters and other devices using photonic bandgap (PBG) theory are typically implemented in microstrip lines by etching periodic holes on the ground plane of the microstrip. The period of such several holes corresponds to nearly half the guided wavelength of the transmission line. In this paper we study the effects of miniaturization of the PBG device by meandering the microstrip line about one single hole in the ground plane. A comparison of the S-parameters and dispersion behavior of the modified geometry and a conventional PBG device with a straight microstrip line shows that these devices have similar behaviors.

Reconfigurable Viterbi decoder on mesh connected multiprocessor architecture

In modern wireline and wireless communication systems, Viterbi decoder is one of the most compute intensive and essential elements. Each standard requires a different configuration of Viterbi decoder. Hence there is a need to design a flexible reconfigurable Viterbi decoder to support different configurations on a single platform. In this paper we present a reconfigurable Viterbi decoder which can be reconfigured for standards such as WCDMA, CDMA2000, IEEE 802.11, DAB, DVB, and GSM. Different parameters like code rate, constraint length, polynomials and truncation length can be configured to map any of the above mentioned standards. Our design provides higher throughput and scalable power consumption in various configuration of the reconfigurable Viterbi decoder. The power and throughput can also be optimized for different standards.

High-Rate,2-Group ML-Decodable STBCs for 2(m) Transmit Antennas

A Space-Time Block Code (STBC) in K-variables is said to be g-Group ML-Decodable (GMLD) if its Maximum-Likelihood (ML) decoding metric can be written as a sum of g independent terms, with each term being a function of a subset of the K variables. In this paper, a construction method to obtain high-rate, 2-GMLD STBCs for 2(m) transmit antennas, m > 1, is presented. The rate of the STBC obtained for 2(m) transmit antennas is 2(m-2) + 1/2(m), complex symbols per channel use. The design method is illustrated for the case of 4 and 8 transmit antennas. The code obtained for 4 transmit antennas is equivalent to the rate-5/4 Quasi-Orthogonal design (QOD) proposed by Yuen, Guan and Tjung.

Architecture of Run-time Reconfigurable Channel Decoder

Modern wireline and wireless communication devices are multimode and multifunctional communication devices. In order to support multiple standards on a single platform, it is necessary to develop a reconfigurable architecture that can provide the required flexibility and performance. The Channel decoder is one of the most compute intensive and essential elements of any communication system. Most of the standards require a reconfigurable Channel decoder that is capable of performing Viterbi decoding and Turbo decoding. Furthermore, the Channel decoder needs to support different configurations of Viterbi and Turbo decoders. In this paper, we propose a reconfigurable Channel decoder that can be reconfigured for standards such as WCDMA, CDMA2000, IEEE802.11, DAB, DVB and GSM. Different parameters like code rate, constraint length, polynomials and truncation length can be configured to map any of the above mentioned standards. A multiprocessor approach has been followed to provide higher throughput and scalable power consumption in various configurations of the reconfigurable Viterbi decoder and Turbo decoder. We have proposed A Hybrid register exchange approach for multiprocessor architecture to minimize power consumption.

A geodesic constant method for computing high-frequency mutual coupling between antennas on general quadric cylinders

A Geodesic Constant Method (GCM) is outlined which provides a common approach to ray tracing on quadric cylinders in general, and yields all the surface ray-geometric parameters required in the UTD mutual coupling analysis of conformal antenna arrays in the closed form. The approach permits the incorporation of a shaping parameter which permits the modeling of quadric cylindrical surfaces of desired sharpness/flatness with a common set of equations. The mutual admittance between the slots on a general parabolic cylinder is obtained as an illustration of the applicability of the GCM.

Broadband stacked three-layer circular microstrip antenna arrays

The broadband aspects of stacked three-layer electromagnetically coupled circular microstrip antenna arrays are investigated experimentally. Experiments carried out on 8-element linear microstrip antenna arrays, using optimized stacked three-layer circular microstrip antenna elements, configured in E- and H-planes, have exhibited an impedance bandwidth of 20 percent, with a high gain and a good pattern shape with sidelobe as well as crosspolarization levels better than -20 dB through a scan angle of 40 deg from the broadside.

Effect of tolerance on the propagation characteristic of a superconducting thin film microstrip delay line

The propagation constant of a superconducting microstrip transmission delay line is evaluated using the spectral domain immitance approach, modelling the superconductor as a surface current having an equivalent surface impedance found through the complex resistive boundary condition. The sensitivity approach is used to study the beta variations with substrate parameters and film characteristics. Results show that the surface impedance does not have much influence on beta sensitivities with respect to epsilon r, W and h. However, it can be observed that the surface impedance plays a crucial role in determining the optimum design.

Resistivity imaging of a reconfigurable phantom with circular inhomogeneities in 2D-electrical impedance tomography

Resistivity imaging of a reconfigurable phantom with circular inhomogeneities is studied with a simple instrumentation and data acquisition system for Electrical Impedance Tomography. The reconfigurable phantom is developed with stainless steel electrodes and a sinusoidal current of constant amplitude is injected to the phantom boundary using opposite current injection protocol. Nylon and polypropylene cylinders with different cross sectional areas are kept inside the phantom and the boundary potential data are collected. The instrumentation and the data acquisition system with a DIP switch-based multiplexer board are used to inject a constant current of desired amplitude and frequency. Voltage data for the first eight current patterns (128 voltage data) are found to be sufficient to reconstruct the inhomogeneities and hence the acquisition time is reduced. Resistivity images are reconstructed from the boundary data for different inhomogeneity positions using EIDORS-2D. The results show that the shape and resistivity of the inhomogeneity as well as the background resistivity are successfully reconstructed from the potential data for single or double inhomogeneity phantoms. The resistivity images obtained from the single and double inhomogeneity phantom clearly indicate the inhomogeneity as the high resistive material. Contrast to noise ratio (CNR) and contrast recovery (CR) of the reconstructed images are found high for the inhomogeneities near all the electrodes arbitrarily chosen for the entire study. (C) 2010 Elsevier Ltd. All rights reserved.

Fast algorithm for data exchange in reconfigurable tree structures

This paper presents a fast algorithm for data exchange in a network of processors organized as a reconfigurable tree structure. For a given data exchange table, the algorithm generates a sequence of tree configurations in which the data exchanges are to be executed. A significant feature of the algorithm is that each exchange is executed in a tree configuration in which the source and destination nodes are adjacent to each other. It has been proved in a theorem that for every pair of nodes in the reconfigurable tree structure, there always exists two and only two configurations in which these two nodes are adjacent to each other. The algorithm utilizes this fact and determines the solution so as to optimize both the number of configurations required and the time to perform the data exchanges. Analysis of the algorithm shows that it has linear time complexity, and provides a large reduction in run-time as compared to a previously proposed algorithm. This is well-confirmed from the experimental results obtained by executing a large number of randomly-generated data exchange tables. Another significant feature of the algorithm is that the bit-size of the routing information code is always two bits, irrespective of the number of nodes in the tree. This not only increases the speed of the algorithm but also results in simpler hardware inside each node.