Automatic layout generation of static CMOS circuits targeting delay and power

The evolution of integrated circuits technologies demands the development of new CAD tools. The traditional development of digital circuits at physical level is based in library of cells. These libraries of cells offer certain predictability of the electrical behavior of the design due to the previous characterization of the cells. Besides, different versions of each cell are required in such a way that delay and power consumption characteristics are taken into account, increasing the number of cells in a library. The automatic full custom layout generation is an alternative each time more important to cell based generation approaches. This strategy implements transistors and connections according patterns defined by algorithms. So, it is possible to implement any logic function avoiding the limitations of the library of cells. Tools of analysis and estimate must offer the predictability in automatic full custom layouts. These tools must be able to work with layout estimates and to generate information related to delay, power consumption and area occupation. This work includes the research of new methods of physical synthesis and the implementation of an automatic layout generation in which the cells are generated at the moment of the layout synthesis. The research investigates different strategies of elements disposition (transistors, contacts and connections) in a layout and their effects in the area occupation and circuit delay. The presented layout strategy applies delay optimization by the integration with a gate sizing technique. This is performed in such a way the folding method allows individual discrete sizing to transistors. The main characteristics of the proposed strategy are: power supply lines between rows, over the layout routing (channel routing is not used), circuit routing performed before layout generation and layout generation targeting delay reduction by the application of the sizing technique. The possibility to implement any logic function, without restrictions imposed by a library of cells, allows the circuit synthesis with optimization in the number of the transistors. This reduction in the number of transistors decreases the delay and power consumption, mainly the static power consumption in submicrometer circuits. Comparisons between the proposed strategy and other well-known methods are presented in such a way the proposed method is validated.

Power performance evaluation of an electric home fan with triac-based automatic speed control system

In order to provide a low cost system of thermal comfort, a common model of home fan, 40 cm diameter size, had its manual four-button control system replaced by an automatic speed control. The new control system has a temperature sensor feeding a microcontroller that, by using an optic coupling, DIAC or TRIAC-based circuit, varies the RMS value of the fan motor input voltage and its speed, according to the room temperature. Over a wide range of velocity, the fan net power and the motor fan input power were measured working under both control system. The temperature of the motor stator and the voltage waveforms were observed too. Measured values analysis showed that the TRIAC-based control system makes the fan motor work at a very low power factor and efficiency values. The worst case is at low velocity range where the higher fan motor stator temperatures were registered. The poor power factor and efficiency and the harmonics signals inserted in the motor input voltage wave by the TRIAC commutation procedure are correlated.

Robust fault diagnosis in power distribution systems based on fuzzy ARTMAP neural network-aided evidence theory

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

Simulation Tools of DC-DC Converters for Power Electronics Education

This paper presents interactive simulation tools to support the enhancement of power electronics education considering DC to DC converters. These interactive tools make use of the benefits of Java language to provide a dynamic and interactive visualization of simulations in steady-state for idealized non-isolated DC to DC converters. Additionally, this paper discusses the features and the usage of the interactive educational tools to serve as a first design tool for the laboratory experiments in the power electronics courses. In this way, some results were confronted with a well-known simulator package and with experimental results in order to validate the developed interactive simulation tools.

Simulation Tools for Power Electronics Courses Based on Java Technologies

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

Time-series-based maximization of distributed wind power generation integration

Energy policies and technological progress in the development of wind turbines have made wind power the fastest growing renewable power source worldwide. The inherent variability of this resource requires special attention when analyzing the impacts of high penetration on the distribution network. A time-series steady-state analysis is proposed that assesses technical issues such as energy export, losses, and short-circuit levels. A multiobjective programming approach based on the nondominated sorting genetic algorithm (NSGA) is applied in order to find configurations that maximize the integration of distributed wind power generation (DWPG) while satisfying voltage and thermal limits. The approach has been applied to a medium voltage distribution network considering hourly demand and wind profiles for part of the U.K. The Pareto optimal solutions obtained highlight the drawbacks of using a single demand and generation scenario, and indicate the importance of appropriate substation voltage settings for maximizing the connection of MPG.

Unbalanced Three-Phase Induction Motors Starting and Arc Welding Machines Short-Circuit Modeling

Three-Phase Induction Motors (TIM) and Arc Welding Machines (AWM) are loads of special behavior widely used in industrial and commercial installations, and therefore may contribute significantly to the deterioration of the quality of energy supplied by utilities. This paper proposes a modeling in constant power of the unbalanced TIM starting using Genetic Algorithm (GA) and AWM short-circuit based on their statics characteristics curves. The proposed models are compared with the conventional models in the literature. The results showed the good performance of the proposed models, allowing a more precise analysis of the real requests of these loads.

Determination and statistical treatment of short-circuit currents for faults on the lines of networks of 440 kV CESP system

The distribution of short-circuit current is investigated by means of two methods, one direct and the other analytic; both methods consider uniform probability distribution of line faults. In the direct method, the procedure consists of calculating fault currents at equidistant points along the line, starting from one of the end points and considering the other end open. The magnitude of the current is classified according to Brazilian standards (regulation NBR-7118). The analytic method assumes that the distribution of short-circuit currents through the busbar and the distribution of the line length connected to it are known, as well as the independence of values. The method is designed to determine the probability that fault currents through a line will surpass the pre-established magnitude, thus generating frequency distribution curves of short-circuit currents along the lines.

Electric power systems transient stability analysis by neural networks

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

Power analysis applying the instantaneous complex power analytical expressions on a RL symmetrical three-phase system

This paper enhances some concepts of the Instantaneous Complex Power Theory by analyzing the analytical expressions for voltages, currents and powers developed on a symmetrical RL three-phase system, during the transient caused by a sinusoidal voltage excitation. The powers delivered to an ideal inductor will be interpreted, allowing a deep insight in the power phenomenon by analyzing the voltages in each element of the circuit. The results can be applied to the understanding of non-linear systems subject to sinusoidal voltage excitation and distorted currents.

A Gm-C bump equalizer for low-voltage low-power applications

A low-voltage low-power 2nd-order CMOS pseudo-differential bump-equalizer is presented. Its topology comprises a bandpass section with adjustable center frequency and quality factor, together with a programmable current amplifier. The basic building blocks are triode-operating transconductors, tunable by means of either a DC voltage or a digitally controlled current divider. The bump-equalizer as part of a battery-operated hearing aid device is designed for a 1.4V-supply and a 0.35μm CMOS fabrication process. The circuit performance is supported by a set of simulation results, which indicates a center frequency from 600Hz to 2.4kHz, 1≤Q≤5, and an adjustable gain within ±6dB at center frequency. The filter dynamic range lies around 40dB. Quiescent consumption is kept below 12μW for any configuration of the filter.

Defects location in power systems components through a dedicated genetic algorithm

In this work the problem of defects location in power systems is formulated through a binary linear programming (BLP) model based on alarms historical database of control and protection devices from the system control center, sets theory of minimal coverage (AI) and protection philosophy adopted by the electric utility. In this model, circuit breaker operations are compared to their expected states in a strictly mathematical manner. For solving this BLP problem, which presents a great number of decision variables, a dedicated Genetic Algorithm (GA), is proposed. Control parameters of the GA, such as crossing over and mutation rates, population size, iterations number and population diversification, are calibrated in order to obtain efficiency and robustness. Results for a test system found in literature, are presented and discussed. © 2004 IEEE.

Comparison of algorithms for loss allocation in transmission networks considering power redispatch

An analysis of the performances of three important methods for generators and loads loss allocation is presented. The discussed methods are: based on pro-rata technique; based on the incremental technique; and based on matrices of circuit. The algorithms are tested considering different generation conditions, using a known electric power system: IEEE 14 bus. Presented and discussed results verify: the location and the magnitude of generators and loads; the possibility to have agents well or poorly located in each network configuration; the discriminatory behavior considering variations in the power flow in the transmission lines. © 2004 IEEE.

An AC voltage regulator with high-power-factor, and control using a FPGA device

This paper presents the analysis, design, simulation, and experimental results for a high frequency high Power-Factor (PF) AC (Alternate Current) voltage regulator, using a Sepic converter as power stage. The control technique employed to impose a sinusoidal input current waveform, with low Total Harmonic Distortion (THD), is the sinusoidal variable hysteresis control. The control technique was implemented in a FPGA (Field Programmable Gate Array) device, using a Hardware Description Language (VHDL). Through the use of the proposed control technique, the AC voltage regulator performs active power-factor correction, and low THD in the input current, for linear and non-linear loads, satisfying the requirements of the EEC61000-3-2 standards. Experimental results from an example prototype, designed for 300W of nominal output power, 50kHz (switching frequency), and 127Vrms of nominal input and output voltages, are presented in order to validate the proposed AC regulator. © 2005 IEEE.

Integrated planning of electric power distribution networks

In this work, a heuristic model for integrated planning of primary distribution network and secondary distribution circuits is proposed. A Tabu Search (TS) algorithm is employed to solve the planning of primary distribution networks. Evolutionary Algorithms (EA) are used to solve the planning model of secondary networks. The planning integration of both networks is carried out by means a constructive heuristic taking into account a set of integration alternatives between these networks. These integration alternatives are treated in a hierarchical way. The planning of primary networks and secondary distribution circuits is carried out based on assessment of the effects of the alternative solutions in the expansion costs of both networks simultaneously. In order to evaluate this methodology, tests were performed for a real-life distribution system taking into account the primary and secondary networks.