From Broadstone to Zackenberg

Ecological networks are typically complex constructions of species and their interactions. During the last decade, the study of networks has moved from static to dynamic analyses, and has attained a deeper insight into their internal structure, heterogeneity, and temporal and spatial resolution. Here, we review, discuss and suggest research lines in the study of the spatio-temporal heterogeneity of networks and their hierarchical nature. We use case study data from two well-characterized model systems (the food web in Broadstone Stream in England and the pollination network at Zackenberg in Greenland), which are complemented with additional information from other studies. We focus upon eight topics: temporal dynamic space-for-time substitutions linkage constraints habitat borders network modularity individual-based networks invasions of networks and super networks that integrate different network types. Few studies have explicitly examined temporal change in networks, and we present examples that span from daily to decadal change: a common pattern that we see is a stable core surrounded by a group of dynamic, peripheral species, which, in pollinator networks enter the web via preferential linkage to the most generalist species. To some extent, temporal and spatial scales are interchangeable (i.e. networks exhibit ‘ergodicity’) and we explore how space-for-time substitutions can be used in the study of networks. Network structure is commonly constrained by phenological uncoupling (a temporal phenomenon), abundance, body size and population structure. Some potential links are never observed, that is they are ‘forbidden’ (fully constrained) or ‘missing’ (a sampling effect), and their absence can be just as ecologically significant as their presence. Spatial habitat borders can add heterogeneity to network structure, but their importance has rarely been studied: we explore how habitat generalization can be related to other resource dimensions. Many networks are hierarchically structured, with modules forming the basic building blocks, which can result in self-similarity. Scaling down from networks of species reveals another, finer-grained level of individual-based organization, the ecological consequences of which have yet to be fully explored. The few studies of individual-based ecological networks that are available suggest the potential for large intraspecific variance and, in the case of food webs, strong size-structuring. However, such data are still scarce and more studies are required to link individual-level and species-level networks. Invasions by alien species can be tracked by following the topological ‘career’ of the invader as it establishes itself within a network, with potentially important implications for conservation biology. Finally, by scaling up to a higher level of organization, it is possible to combine different network types (e.g. food webs and mutualistic networks) to form super networks, and this new approach has yet to be integrated into mainstream ecological research. We conclude by listing a set of research topics that we see as emerging candidates for ecological network studies in the near future.

An Architecture to offer Cloud-Based Radio Access Network as a Service

This paper addresses the novel notion of offering a radio access network as a service. Its components may be instantiated on general purpose platforms with pooled resources (both radio and hardware ones) dimensioned on-demand, elastically and following the pay-per-use principle. A novel architecture is proposed that supports this concept. The architecture's success is in its modularity, well-defined functional elements and clean separation between operational and control functions. By moving much processing traditionally located in hardware for computation in the cloud, it allows the optimisation of hardware utilization and reduction of deployment and operation costs. It enables operators to upgrade their network as well as quickly deploy and adapt resources to demand. Also, new players may easily enter the market, permitting a virtual network operator to provide connectivity to its users.

Delegation Proxies: The Power of Propagation

Scoping behavioral variations to dynamic extents is useful to support non-functional requirements that otherwise result in cross-cutting code. Unfortunately, such variations are difficult to achieve with traditional reflection or aspects. We show that with a modification of dynamic proxies, called delegation proxies, it becomes possible to reflectively implement variations that propagate to all objects accessed in the dynamic extent of a message send. We demonstrate our approach with examples of variations scoped to dynamic extents that help simplify code related to safety, reliability, and monitoring.

Spatio-temporal Rho GTPase signaling - where are we now?

Rho-family GTPases are molecular switches that transmit extracellular cues to intracellular signaling pathways. Their regulation is likely to be highly regulated in space and in time, but most of what is known about Rho-family GTPase signaling has been derived from techniques that do not resolve these dimensions. New imaging technologies now allow the visualization of Rho GTPase signaling with high spatio-temporal resolution. This has led to insights that significantly extend classic models and call for a novel conceptual framework. These approaches clearly show three things. First, Rho GTPase signaling dynamics occur on micrometer length scales and subminute timescales. Second, multiple subcellular pools of one given Rho GTPase can operate simultaneously in time and space to regulate a wide variety of morphogenetic events (e.g. leading-edge membrane protrusion, tail retraction, membrane ruffling). These different Rho GTPase subcellular pools might be described as 'spatio-temporal signaling modules' and might involve the specific interaction of one GTPase with different guanine nucleotide exchange factors (GEFs), GTPase-activating proteins (GAPs) and effectors. Third, complex spatio-temporal signaling programs that involve precise crosstalk between multiple Rho GTPase signaling modules regulate specific morphogenetic events. The next challenge is to decipher the molecular circuitry underlying this complex spatio-temporal modularity to produce integrated models of Rho GTPase signaling.

The Secret Life of Mundane Transaction Costs

Transaction costs, one often hears, are the economic equivalent of friction in physical systems. Like physicists, economists can sometimes neglect friction in formulating theories; but like engineers, they can never neglect friction in studying how the system actually does let alone should work. Interestingly, however, the present-day economics of organization also ignores friction. That is, almost single-mindedly, the literature analyzes transactions from the point of view of misaligned incentives and (especially) transaction-specific assets. The costs involved are certainly costs of running the economic system in some sense, but they are not obviously frictions. Stories about frictions in trade are not nearly as intriguing as stories about guileful trading partners and expensive assets placed at risk. But I will argue that these seemingly dull categories of cost what Baldwin and Clark (2003) call mundane transaction costs actually have a secret life. They are at least as important as, and quite probably far more important than, the more glamorous costs of asset specificity in explaining the partition between firm and market. These costs also have a secret life in another sense: they have a secret life cycle. I will argue that these mundane transaction costs provide much better material for helping us understanding how the boundaries among firms, markets, and hybrid forms change over time.

Modular extensions for modular (Logic) languages

We address the problem of developing mechanisms for easily implementing modular extensions to modular (logic) languages. By(language) extensions we refer to different groups of syntactic definitions and translation rules that extend a language. Our use of the concept of modularity in this context is twofold. We would like these extensions to be modular, in the sense above, i.e., we should be able to develop different extensions mostly separately. At the same time, the sources and targets for the extensions are modular languages, i.e., such extensions may take as input sepárate pieces of code and also produce sepárate pieces of code. Dealing with this double requirement involves interesting challenges to ensure that modularity is not broken: first, combinations of extensions (as if they were a single extensión) must be given a precise meaning. Also, the sepárate translation of múltiple sources (as if they were a single source) must be feasible. We present a detailed description of a code expansion-based framework that proposes novel solutions for these problems. We argüe that the approach, while implemented for Ciao, can be adapted for other Prolog-based systems and languages.

Desintegración vertical en la industria del automóvil en España: un caso de estudio = Vertical disintegration in the automotive industry in Spain: a case study

En los años recientes se ha producido un rápido crecimiento del comercio internacional en productos semielaborados que son diseñados, producidos y ensamblados en diferentes localizaciones a lo largo de diferentes países, debido principalmente a los siguientes motivos: el desarrollo de las tecnologías de la información, la reducción de los costes de transporte, la liberalización de los mercados de capitales, la armonización de factores institucionales, la integración económica regional que implica la reducción y la eliminación de las barreras al comercio, el desarrollo económico de los países emergentes, el uso de economías de escala, así como una desregulación del comercio internacional. Todo ello ha incrementado la competencia a nivel mundial en los mercados y ha posibilitado a las compañías tener más facilidad de acceso a potenciales mercados, así como a la adquisición de capacidades y conocimientos en otros países y a la realización de alianzas estratégicas internacionales con terceros, creando un entorno con mayor incertidumbre y más exigente para las compañías que componen una industria, y que tiene consecuencias directas en las operaciones de las compañías y en la organización de su producción. Las compañías, para adaptarse, ser competitivas y beneficiarse de este nuevo escenario globalizado y más competitivo, han externalizado partes del proceso productivo hacia proveedores especializados, creando un nuevo mercado intermedio que divide el proceso productivo, anteriormente integrado en las compañías que conforman una industria, entre dos conjuntos de empresas especializadas en esa industria. Dicho proceso suele ocurrir conservando la industria en que tiene lugar, los mismos servicios y productos, la tecnología empleada y las compañías originales que la conformaban previamente a la desintegración vertical. Todo ello es así debido a que es beneficioso tanto para las compañías originales de la industria como para las nuevas compañías de este mercado intermedio por diversos motivos. La desintegración vertical en una industria tiene unas consecuencias que la transforman completamente, así como la forma de operar de las compañías que la integran, incluso para aquellas que permanecen verticalmente integradas. Una de las características más importantes de esta desintegración vertical en una industria es la posibilidad que tiene una compañía de adquirir a una tercera la primera parte del proceso productivo o un bien semielaborado, que posteriormente será finalizado por la compañía adquiriente con la práctica del outsourcing; así mismo, una compañía puede realizar la primera parte del proceso productivo o un bien semielaborado, que posteriormente será finalizado por una tercera compañía con la práctica de la fragmentación. El principal objetivo de la presente investigación es el estudio de los motivos, los facilitadores, los efectos, las consecuencias y los principales factores significativos, microeconómicos y macroeconómicos, que desencadenan o incrementan la práctica de la desintegración vertical en una industria; para ello, la investigación se divide en dos líneas completamente diferenciadas: el estudio de la práctica del outsourcing y, por otro lado, el estudio de la fragmentación por parte de las compañías que componen la industria del automóvil en España, puesto que se trata de una de las industrias más desintegradas verticalmente y fragmentadas, y este sector posee una gran importancia en la economía del país. En primer lugar, se hace una revisión de la literatura existente relativa a los siguientes aspectos: desintegración vertical, outsourcing, fragmentación, teoría del comercio internacional, historia de la industria del automóvil en España y el uso de las aglomeraciones geográficas y las tecnologías de la información en el sector del automóvil. La metodología empleada en cada uno de ellos ha sido diferente en función de la disponibilidad de los datos y del enfoque de investigación: los factores microeconómicos, utilizando el outsourcing, y los factores macroeconómicos, empleando la fragmentación. En el estudio del outsourcing, se usa un índice basado en las compras externas sobre el valor total de la producción. Así mismo, se estudia su correlación y significación con las variables económicas más importantes que definen a una compañía del sector del automóvil, utilizando la técnica estadística de regresión lineal. Aquellas variables relacionadas con la competencia en el mercado, la externalización de las actividades de menor valor añadido y el incremento de la modularización de las actividades de la cadena de valor, han resultado significativas con la práctica del outsourcing. En el estudio de la fragmentación se seleccionan un conjunto de factores macroeconómicos, comúnmente usados en este tipo de investigaciones, relacionados con las principales magnitudes económicas de un país, y un conjunto de factores macroeconómicos, no comúnmente usados en este tipo de investigaciones, relacionados con la libertad económica y el comercio internacional de un país. Se emplea un modelo de regresión logística para identificar qué factores son significativos en la práctica de la fragmentación. De entre todos los factores usados en el modelo, los relacionados con las economías de escala y los costes de servicio han resultado significativos. Los resultados obtenidos de los test estadísticos realizados en el modelo de regresión logística han resultado satisfactorios; por ello, el modelo propuesto de regresión logística puede ser considerado sólido, fiable y versátil; además, acorde con la realidad. De los resultados obtenidos en el estudio del outsourcing y de la fragmentación, combinados conjuntamente con el estado del arte, se concluye que el principal factor que desencadena la desintegración vertical en la industria del automóvil es la competencia en el mercado de vehículos. Cuanto mayor es la demanda de vehículos, más se reducen los beneficios y la rentabilidad para sus fabricantes. Estos, para ser competitivos, diferencian sus productos de la competencia centrándose en las actividades que mayor valor añadido aportan al producto final, externalizando las actividades de menor valor añadido a proveedores especializados, e incrementando la modularidad de las actividades de la cadena de valor. Las compañías de la industria del automóvil se especializan en alguna o varias de estas actividades modularizadas que, combinadas con el uso de factores facilitadores como las economías de escala, las tecnologías de la información, las ventajas de la globalización económica y la aglomeración geográfica de una industria, incrementan y motivan la desintegración vertical en la industria del automóvil, desencadenando la coespecialización en dos sectores claramente diferenciados: el sector de fabricantes de vehículos y el sector de proveedores especializados. Cada uno de ellos se especializa en unas actividades y en unos productos o servicios específicos de la cadena de valor, lo cual genera las siguientes consecuencias en la industria del automóvil: se reducen los costes de transacción en los productos o servicios intercambiados; se incrementan la relación de dependencia entre fabricantes de vehículos y proveedores especializados, provocando un aumento en la cooperación y la coordinación, acelerando el proceso de aprendizaje, posibilitando a ambos adquirir nuevas capacidades, conocimientos y recursos, y creando nuevas ventajas competitivas para ambos; por último, las barreras de entrada a la industria del automóvil y el número de compañías se ven alteradas cambiando su estructura. Como futura línea de investigación, los fabricantes de vehículos tenderán a centrarse en investigar, diseñar y comercializar el producto o servicio, delegando el ensamblaje en manos de nuevos especialistas en la materia, el contract manufacturer; por ello, sería conveniente investigar qué factores motivantes o facilitadores existen y qué consecuencias tendría la implantación de los contract manufacturer en la industria del automóvil. 1.1. ABSTRACT In recent years there has been a rapid growth of international trade in semi-finished products designed, produced and assembled in different locations across different countries, mainly due to the following reasons: development of information technologies, reduction of transportation costs, liberalisation of capital markets, harmonisation of institutional factors, regional economic integration, which involves the reduction and elimination of trade barriers, economic development of emerging countries, use of economies of scale and deregulation of international trade. All these factors have increased competition in markets at a global level and have allowed companies to gain easier access to potential markets and to the acquisition of skills and knowledge in other countries, as well as to the completion of international strategic alliances with third parties, thus creating a more demanding and uncertain environment for these companies constituting an industry, which has a direct impact on the companies' operations and the organization of their production. In order to adapt, be competitive and benefit from this new and more competitive global scenario, companies have outsourced some parts of their production process to specialist suppliers, generating a new intermediate market which divides the production process, previously integrated in the companies that made up the industry, into two sets of companies specialized in that industry. This process often occurs while preserving the industry where it takes place, its same services and products, the technology used and the original companies that formed it prior to vertical disintegration. This is because it is beneficial for both the industry's original companies and the companies belonging to this new intermediate market, for various reasons. Vertical disintegration has consequences which completely transform the industry where it takes place as well as the modus operandi of the companies that are part of it, even of those who remain vertically integrated. One of the most important features of vertical disintegration of an industry is the possibility for a company to acquire from a third one the first part of the production process or a semi-finished product, which will then be finished by the acquiring company through the practice of outsourcing; also, a company can perform the first part of the production process or a semi-finish product, which will then be completed by a third company through the practice of fragmentation. The main objective of this research is to study the motives, facilitators, effects, consequences and major significant microeconomic and macroeconomic factors that trigger or increase the practice of vertical disintegration in a certain industry; in order to do so, research is divided into two completely differentiated lines: on the one hand, the study of the practise of outsourcing and, on the other, the study of fragmentation by companies constituting the automotive industry in Spain, since this is one of the most vertically disintegrated and fragmented industries and this particular sector is of major significance in this country's economy. First, a review is made of the existing literature, on the following aspects: vertical disintegration, outsourcing, fragmentation, international trade theory, history of the automobile industry in Spain and the use of geographical agglomeration and information technologies in the automotive sector. The methodology used for each of these aspects has been different depending on the availability of data and the research approach: the microeconomic factors, using outsourcing, and the macroeconomic factors, using fragmentation. In the study on outsourcing, an index is used based on external purchases in relation to the total value of production. Likewise, their significance and correlation with the major economic variables that define an automotive company are studied, using the statistical technique of linear regression. Variables related to market competition, outsourcing of lowest value-added activities and increased modularisation of the activities of the value chain have turned out to be significant with the practice of outsourcing. In the study of fragmentation, a set of macroeconomic factors commonly used for this type of research, is selected, related to the main economic indicators of a country, as well as a set of macroeconomic factors, not commonly used for this type of research, which are related to economic freedom and the international trade of a certain country. A logistic regression model is used to identify which factors are significant in the practice of fragmentation. Amongst all factors used in the model, those related to economies of scale and service costs have turned out to be significant. The results obtained from the statistical tests performed on the logistic regression model have been successful; hence, the suggested logistic regression model can be considered to be solid, reliable and versatile; likewise, it is in line with reality. From the results obtained in the study of outsourcing and fragmentation, combined with the state of the art, it is concluded that the main factor that triggers vertical disintegration in the automotive industry is competition within the vehicle market. The greater the vehicle demand, the lower the earnings and profitability for manufacturers. These, in order to be competitive, differentiate their products from the competition by focusing on those activities that contribute with the highest added value to the final product, outsourcing the lower valueadded activities to specialist suppliers, and increasing the modularity of the activities of the value chain. Companies in the automotive industry specialize in one or more of these modularised activities which, combined with the use of enabling factors such as economies of scale, information technologies, the advantages of economic globalisation and the geographical agglomeration of an industry, increase and encourage vertical disintegration in the automotive industry, triggering co-specialization in two clearly distinct sectors: the sector of vehicle manufacturers and the specialist suppliers sector. Each of them specializes in certain activities and specific products or services of the value chain, generating the following consequences in the automotive industry: reduction of transaction costs of the goods or services exchanged; growth of the relationship of dependency between vehicle manufacturers and specialist suppliers, which causes an increase in cooperation and coordination, accelerates the learning process, enables both to acquire new skills, knowledge and resources, and creates new competitive advantages for both; finally, barriers to entry the automotive industry and the number of companies are altered, changing their structure. As a future line of research, vehicle manufacturers will tend to focus on researching, designing and marketing the product or service, delegating the assembly in the hands of new specialists in the field, the contract manufacturer; for this reason, it would be useful to investigate what motivating or facilitating factors exist in this respect and what consequences would the implementation of contract manufacturers have in the automotive industry.

Towards modular extensions for a modular language

Modularity allows the construction of complex designs from simpler, independent units that most of the time can be developed separately. In this paper we are concerned with developing mechanisms for easily implementing modular extensions to modular (logic) languages. By (language) extensions we refer to different groups of syntactic definitions and translation rules that extend a language. Our application of the concept of modularity in this context is twofold. We would like these extensions to be modular, in the above sense, i.e., we should be able to develop different extensions mostly separately. At the same time, the sources and targets for the extensions are modular languages, i.e., such extensions may take as input separate pieces of code and also produce separate pieces of code. Dealing with this double requirement involves interesting challenges to ensure that modularity is not broken: first, combinations of extensions (as if they were a single extension) must be given a precise meaning. Also, the separate translation of multiple sources (as if they were a single source) must be feasible. We present a detailed description of a code expansion-based framework that proposes novel solutions for these problems. We argue that the approach, while implemented for Ciao, can be adapted for other languages and Prolog-based systems.

An overview of ciao and its design philosophy

We provide an overall description of the Ciao multiparadigm programming system emphasizing some of the novel aspects and motivations behind its design and implementation. An important aspect of Ciao is that, in addition to supporting logic programming (and, in particular, Prolog), it provides the programmer with a large number of useful features from different programming paradigms and styles and that the use of each of these features (including those of Prolog) can be turned on and off at will for each program module. Thus, a given module may be using, e.g., higher order functions and constraints, while another module may be using assignment, predicates, Prolog meta-programming, and concurrency. Furthermore, the language is designed to be extensible in a simple and modular way. Another important aspect of Ciao is its programming environment, which provides a powerful preprocessor (with an associated assertion language) capable of statically finding non-trivial bugs, verifying that programs comply with specifications, and performing many types of optimizations (including automatic parallelization). Such optimizations produce code that is highly competitive with other dynamic languages or, with the (experimental) optimizing compiler, even that of static languages, all while retaining the flexibility and interactive development of a dynamic language. This compilation architecture supports modularity and separate compilation throughout. The environment also includes a powerful autodocumenter and a unit testing framework, both closely integrated with the assertion system. The paper provides an informal overview of the language and program development environment. It aims at illustrating the design philosophy rather than at being exhaustive, which would be impossible in a single journal paper, pointing instead to previous Ciao literature.

Using global analysis, partial specifications, and an extensible assertion language for program validation and debugging

We present a framework for the application of abstract interpretation as an aid during program development, rather than in the more traditional application of program optimization. Program validation and detection of errors is first performed statically by comparing (partial) specifications written in terms of assertions against information obtained from static analysis of the program. The results of this process are expressed in the user assertion language. Assertions (or parts of assertions) which cannot be verified statically are translated into run-time tests. The framework allows the use of assertions to be optional. It also allows using very general properties in assertions, beyond the predefined set understandable by the static analyzer and including properties defined by means of user programs. We also report briefly on an implementation of the framework. The resulting tool generates and checks assertions for Prolog, CLP(R), and CHIP/CLP(fd) programs, and integrates compile-time and run-time checking in a uniform way. The tool allows using properties such as types, modes, non-failure, determinacy, and computational cost, and can treat modules separately, performing incremental analysis. In practice, this modularity allows detecting statically bugs in user programs even if they do not contain any assertions.

The Ciao clp(FD) library. A modular CLP extension for Prolog

We present a new free library for Constraint Logic Programming over Finite Domains, included with the Ciao Prolog system. The library is entirely written in Prolog, leveraging on Ciao's module system and code transformation capabilities in order to achieve a highly modular design without compromising performance. We describe the interface, implementation, and design rationale of each modular component. The library meets several design goals: a high level of modularity, allowing the individual components to be replaced by different versions; highefficiency, being competitive with other TT> implementations; a glass-box approach, so the user can specify new constraints at different levels; and a Prolog implementation, in order to ease the integration with Ciao's code analysis components. The core is built upon two small libraries which implement integer ranges and closures. On top of that, a finite domain variable datatype is defined, taking care of constraint reexecution depending on range changes. These three libraries form what we call the TT> kernel of the library. This TT> kernel is used in turn to implement several higher-level finite domain constraints, specified using indexicals. Together with a labeling module this layer forms what we name the TT> solver. A final level integrates the CLP (J7©) paradigm with our TT> solver. This is achieved using attributed variables and a compiler from the CLP (J7©) language to the set of constraints provided by the solver. It should be noted that the user of the library is encouraged to work in any of those levels as seen convenient: from writing a new range module to enriching the set of TT> constraints by writing new indexicals.

Topological measure locating the effective crossover between segregation and integration in a modular network

We introduce an easily computable topological measure which locates the effective crossover between segregation and integration in a modular network. Segregation corresponds to the degree of network modularity, while integration is expressed in terms of the algebraic connectivity of an associated hypergraph. The rigorous treatment of the simplified case of cliques of equal size that are gradually rewired until they become completely merged, allows us to show that this topological crossover can be made to coincide with a dynamical crossover from cluster to global synchronization of a system of coupled phase oscillators. The dynamical crossover is signaled by a peak in the product of the measures of intracluster and global synchronization, which we propose as a dynamical measure of complexity. This quantity is much easier to compute than the entropy (of the average frequencies of the oscillators), and displays a behavior which closely mimics that of the dynamical complexity index based on the latter. The proposed topological measure simultaneously provides information on the dynamical behavior, sheds light on the interplay between modularity and total integration, and shows how this affects the capability of the network to perform both local and distributed dynamical tasks.

Assortative and modular networks are shaped by adaptive synchronization processes

Modular organization and degree-degree correlations are ubiquitous in the connectivity structure of biological, technological, and social interacting systems. So far most studies have concentrated on unveiling both features in real world networks, but a model that succeeds in generating them simultaneously is needed. We consider a network of interacting phase oscillators, and an adaptation mechanism for the coupling that promotes the connection strengths between those elements that are dynamically correlated. We show that, under these circumstances, the dynamical organization of the oscillators shapes the topology of the graph in such a way that modularity and assortativity features emerge spontaneously and simultaneously. In turn, we prove that such an emergent structure is associated with an asymptotic arrangement of the collective dynamical state of the network into cluster synchronization.

A Three-Dimensional B.I.E.M. Program

The program PECET (Boundary Element Program in Three-Dimensional Elasticity) is presented in this paper. This program, written in FORTRAN V and implemen ted on a UNIVAC 1100,has more than 10,000 sentences and 96 routines and has a lot of capabilities which will be explained in more detail. The object of the program is the analysis of 3-D piecewise heterogeneous elastic domains, using a subregionalization process and 3-D parabolic isopara, metric boundary elements. The program uses special data base management which will be described below, and the modularity followed to write it gives a great flexibility to the package. The Method of Analysis includes an adaptive integration process, an original treatment of boundary conditions, a complete treatment of body forces, the utilization of a Modified Conjugate Gradient Method of solution and an original process of storage which makes it possible to save a lot of memory.

Run-Time Scalable Hardware for Reconfigurable Systems

La optimización de parámetros tales como el consumo de potencia, la cantidad de recursos lógicos empleados o la ocupación de memoria ha sido siempre una de las preocupaciones principales a la hora de diseñar sistemas embebidos. Esto es debido a que se trata de sistemas dotados de una cantidad de recursos limitados, y que han sido tradicionalmente empleados para un propósito específico, que permanece invariable a lo largo de toda la vida útil del sistema. Sin embargo, el uso de sistemas embebidos se ha extendido a áreas de aplicación fuera de su ámbito tradicional, caracterizadas por una mayor demanda computacional. Así, por ejemplo, algunos de estos sistemas deben llevar a cabo un intenso procesado de señales multimedia o la transmisión de datos mediante sistemas de comunicaciones de alta capacidad. Por otra parte, las condiciones de operación del sistema pueden variar en tiempo real. Esto sucede, por ejemplo, si su funcionamiento depende de datos medidos por el propio sistema o recibidos a través de la red, de las demandas del usuario en cada momento, o de condiciones internas del propio dispositivo, tales como la duración de la batería. Como consecuencia de la existencia de requisitos de operación dinámicos es necesario ir hacia una gestión dinámica de los recursos del sistema. Si bien el software es inherentemente flexible, no ofrece una potencia computacional tan alta como el hardware. Por lo tanto, el hardware reconfigurable aparece como una solución adecuada para tratar con mayor flexibilidad los requisitos variables dinámicamente en sistemas con alta demanda computacional. La flexibilidad y adaptabilidad del hardware requieren de dispositivos reconfigurables que permitan la modificación de su funcionalidad bajo demanda. En esta tesis se han seleccionado las FPGAs (Field Programmable Gate Arrays) como los dispositivos más apropiados, hoy en día, para implementar sistemas basados en hardware reconfigurable De entre todas las posibilidades existentes para explotar la capacidad de reconfiguración de las FPGAs comerciales, se ha seleccionado la reconfiguración dinámica y parcial. Esta técnica consiste en substituir una parte de la lógica del dispositivo, mientras el resto continúa en funcionamiento. La capacidad de reconfiguración dinámica y parcial de las FPGAs es empleada en esta tesis para tratar con los requisitos de flexibilidad y de capacidad computacional que demandan los dispositivos embebidos. La propuesta principal de esta tesis doctoral es el uso de arquitecturas de procesamiento escalables espacialmente, que son capaces de adaptar su funcionalidad y rendimiento en tiempo real, estableciendo un compromiso entre dichos parámetros y la cantidad de lógica que ocupan en el dispositivo. A esto nos referimos con arquitecturas con huellas escalables. En particular, se propone el uso de arquitecturas altamente paralelas, modulares, regulares y con una alta localidad en sus comunicaciones, para este propósito. El tamaño de dichas arquitecturas puede ser modificado mediante la adición o eliminación de algunos de los módulos que las componen, tanto en una dimensión como en dos. Esta estrategia permite implementar soluciones escalables, sin tener que contar con una versión de las mismas para cada uno de los tamaños posibles de la arquitectura. De esta manera se reduce significativamente el tiempo necesario para modificar su tamaño, así como la cantidad de memoria necesaria para almacenar todos los archivos de configuración. En lugar de proponer arquitecturas para aplicaciones específicas, se ha optado por patrones de procesamiento genéricos, que pueden ser ajustados para solucionar distintos problemas en el estado del arte. A este respecto, se proponen patrones basados en esquemas sistólicos, así como de tipo wavefront. Con el objeto de poder ofrecer una solución integral, se han tratado otros aspectos relacionados con el diseño y el funcionamiento de las arquitecturas, tales como el control del proceso de reconfiguración de la FPGA, la integración de las arquitecturas en el resto del sistema, así como las técnicas necesarias para su implementación. Por lo que respecta a la implementación, se han tratado distintos aspectos de bajo nivel dependientes del dispositivo. Algunas de las propuestas realizadas a este respecto en la presente tesis doctoral son un router que es capaz de garantizar el correcto rutado de los módulos reconfigurables dentro del área destinada para ellos, así como una estrategia para la comunicación entre módulos que no introduce ningún retardo ni necesita emplear recursos configurables del dispositivo. El flujo de diseño propuesto se ha automatizado mediante una herramienta denominada DREAMS. La herramienta se encarga de la modificación de las netlists correspondientes a cada uno de los módulos reconfigurables del sistema, y que han sido generadas previamente mediante herramientas comerciales. Por lo tanto, el flujo propuesto se entiende como una etapa de post-procesamiento, que adapta esas netlists a los requisitos de la reconfiguración dinámica y parcial. Dicha modificación la lleva a cabo la herramienta de una forma completamente automática, por lo que la productividad del proceso de diseño aumenta de forma evidente. Para facilitar dicho proceso, se ha dotado a la herramienta de una interfaz gráfica. El flujo de diseño propuesto, y la herramienta que lo soporta, tienen características específicas para abordar el diseño de las arquitecturas dinámicamente escalables propuestas en esta tesis. Entre ellas está el soporte para el realojamiento de módulos reconfigurables en posiciones del dispositivo distintas a donde el módulo es originalmente implementado, así como la generación de estructuras de comunicación compatibles con la simetría de la arquitectura. El router has sido empleado también en esta tesis para obtener un rutado simétrico entre nets equivalentes. Dicha posibilidad ha sido explotada para aumentar la protección de circuitos con altos requisitos de seguridad, frente a ataques de canal lateral, mediante la implantación de lógica complementaria con rutado idéntico. Para controlar el proceso de reconfiguración de la FPGA, se propone en esta tesis un motor de reconfiguración especialmente adaptado a los requisitos de las arquitecturas dinámicamente escalables. Además de controlar el puerto de reconfiguración, el motor de reconfiguración ha sido dotado de la capacidad de realojar módulos reconfigurables en posiciones arbitrarias del dispositivo, en tiempo real. De esta forma, basta con generar un único bitstream por cada módulo reconfigurable del sistema, independientemente de la posición donde va a ser finalmente reconfigurado. La estrategia seguida para implementar el proceso de realojamiento de módulos es diferente de las propuestas existentes en el estado del arte, pues consiste en la composición de los archivos de configuración en tiempo real. De esta forma se consigue aumentar la velocidad del proceso, mientras que se reduce la longitud de los archivos de configuración parciales a almacenar en el sistema. El motor de reconfiguración soporta módulos reconfigurables con una altura menor que la altura de una región de reloj del dispositivo. Internamente, el motor se encarga de la combinación de los frames que describen el nuevo módulo, con la configuración existente en el dispositivo previamente. El escalado de las arquitecturas de procesamiento propuestas en esta tesis también se puede beneficiar de este mecanismo. Se ha incorporado también un acceso directo a una memoria externa donde se pueden almacenar bitstreams parciales. Para acelerar el proceso de reconfiguración se ha hecho funcionar el ICAP por encima de la máxima frecuencia de reloj aconsejada por el fabricante. Así, en el caso de Virtex-5, aunque la máxima frecuencia del reloj deberían ser 100 MHz, se ha conseguido hacer funcionar el puerto de reconfiguración a frecuencias de operación de hasta 250 MHz, incluyendo el proceso de realojamiento en tiempo real. Se ha previsto la posibilidad de portar el motor de reconfiguración a futuras familias de FPGAs. Por otro lado, el motor de reconfiguración se puede emplear para inyectar fallos en el propio dispositivo hardware, y así ser capaces de evaluar la tolerancia ante los mismos que ofrecen las arquitecturas reconfigurables. Los fallos son emulados mediante la generación de archivos de configuración a los que intencionadamente se les ha introducido un error, de forma que se modifica su funcionalidad. Con el objetivo de comprobar la validez y los beneficios de las arquitecturas propuestas en esta tesis, se han seguido dos líneas principales de aplicación. En primer lugar, se propone su uso como parte de una plataforma adaptativa basada en hardware evolutivo, con capacidad de escalabilidad, adaptabilidad y recuperación ante fallos. En segundo lugar, se ha desarrollado un deblocking filter escalable, adaptado a la codificación de vídeo escalable, como ejemplo de aplicación de las arquitecturas de tipo wavefront propuestas. El hardware evolutivo consiste en el uso de algoritmos evolutivos para diseñar hardware de forma autónoma, explotando la flexibilidad que ofrecen los dispositivos reconfigurables. En este caso, los elementos de procesamiento que componen la arquitectura son seleccionados de una biblioteca de elementos presintetizados, de acuerdo con las decisiones tomadas por el algoritmo evolutivo, en lugar de definir la configuración de las mismas en tiempo de diseño. De esta manera, la configuración del core puede cambiar cuando lo hacen las condiciones del entorno, en tiempo real, por lo que se consigue un control autónomo del proceso de reconfiguración dinámico. Así, el sistema es capaz de optimizar, de forma autónoma, su propia configuración. El hardware evolutivo tiene una capacidad inherente de auto-reparación. Se ha probado que las arquitecturas evolutivas propuestas en esta tesis son tolerantes ante fallos, tanto transitorios, como permanentes y acumulativos. La plataforma evolutiva se ha empleado para implementar filtros de eliminación de ruido. La escalabilidad también ha sido aprovechada en esta aplicación. Las arquitecturas evolutivas escalables permiten la adaptación autónoma de los cores de procesamiento ante fluctuaciones en la cantidad de recursos disponibles en el sistema. Por lo tanto, constituyen un ejemplo de escalabilidad dinámica para conseguir un determinado nivel de calidad, que puede variar en tiempo real. Se han propuesto dos variantes de sistemas escalables evolutivos. El primero consiste en un único core de procesamiento evolutivo, mientras que el segundo está formado por un número variable de arrays de procesamiento. La codificación de vídeo escalable, a diferencia de los codecs no escalables, permite la decodificación de secuencias de vídeo con diferentes niveles de calidad, de resolución temporal o de resolución espacial, descartando la información no deseada. Existen distintos algoritmos que soportan esta característica. En particular, se va a emplear el estándar Scalable Video Coding (SVC), que ha sido propuesto como una extensión de H.264/AVC, ya que este último es ampliamente utilizado tanto en la industria, como a nivel de investigación. Para poder explotar toda la flexibilidad que ofrece el estándar, hay que permitir la adaptación de las características del decodificador en tiempo real. El uso de las arquitecturas dinámicamente escalables es propuesto en esta tesis con este objetivo. El deblocking filter es un algoritmo que tiene como objetivo la mejora de la percepción visual de la imagen reconstruida, mediante el suavizado de los "artefactos" de bloque generados en el lazo del codificador. Se trata de una de las tareas más intensivas en procesamiento de datos de H.264/AVC y de SVC, y además, su carga computacional es altamente dependiente del nivel de escalabilidad seleccionado en el decodificador. Por lo tanto, el deblocking filter ha sido seleccionado como prueba de concepto de la aplicación de las arquitecturas dinámicamente escalables para la compresión de video. La arquitectura propuesta permite añadir o eliminar unidades de computación, siguiendo un esquema de tipo wavefront. La arquitectura ha sido propuesta conjuntamente con un esquema de procesamiento en paralelo del deblocking filter a nivel de macrobloque, de tal forma que cuando se varía del tamaño de la arquitectura, el orden de filtrado de los macrobloques varia de la misma manera. El patrón propuesto se basa en la división del procesamiento de cada macrobloque en dos etapas independientes, que se corresponden con el filtrado horizontal y vertical de los bloques dentro del macrobloque. Las principales contribuciones originales de esta tesis son las siguientes: - El uso de arquitecturas altamente regulares, modulares, paralelas y con una intensa localidad en sus comunicaciones, para implementar cores de procesamiento dinámicamente reconfigurables. - El uso de arquitecturas bidimensionales, en forma de malla, para construir arquitecturas dinámicamente escalables, con una huella escalable. De esta forma, las arquitecturas permiten establecer un compromiso entre el área que ocupan en el dispositivo, y las prestaciones que ofrecen en cada momento. Se proponen plantillas de procesamiento genéricas, de tipo sistólico o wavefront, que pueden ser adaptadas a distintos problemas de procesamiento. - Un flujo de diseño y una herramienta que lo soporta, para el diseño de sistemas reconfigurables dinámicamente, centradas en el diseño de las arquitecturas altamente paralelas, modulares y regulares propuestas en esta tesis. - Un esquema de comunicaciones entre módulos reconfigurables que no introduce ningún retardo ni requiere el uso de recursos lógicos propios. - Un router flexible, capaz de resolver los conflictos de rutado asociados con el diseño de sistemas reconfigurables dinámicamente. - Un algoritmo de optimización para sistemas formados por múltiples cores escalables que optimice, mediante un algoritmo genético, los parámetros de dicho sistema. Se basa en un modelo conocido como el problema de la mochila. - Un motor de reconfiguración adaptado a los requisitos de las arquitecturas altamente regulares y modulares. Combina una alta velocidad de reconfiguración, con la capacidad de realojar módulos en tiempo real, incluyendo el soporte para la reconfiguración de regiones que ocupan menos que una región de reloj, así como la réplica de un módulo reconfigurable en múltiples posiciones del dispositivo. - Un mecanismo de inyección de fallos que, empleando el motor de reconfiguración del sistema, permite evaluar los efectos de fallos permanentes y transitorios en arquitecturas reconfigurables. - La demostración de las posibilidades de las arquitecturas propuestas en esta tesis para la implementación de sistemas de hardware evolutivos, con una alta capacidad de procesamiento de datos. - La implementación de sistemas de hardware evolutivo escalables, que son capaces de tratar con la fluctuación de la cantidad de recursos disponibles en el sistema, de una forma autónoma. - Una estrategia de procesamiento en paralelo para el deblocking filter compatible con los estándares H.264/AVC y SVC que reduce el número de ciclos de macrobloque necesarios para procesar un frame de video. - Una arquitectura dinámicamente escalable que permite la implementación de un nuevo deblocking filter, totalmente compatible con los estándares H.264/AVC y SVC, que explota el paralelismo a nivel de macrobloque. El presente documento se organiza en siete capítulos. En el primero se ofrece una introducción al marco tecnológico de esta tesis, especialmente centrado en la reconfiguración dinámica y parcial de FPGAs. También se motiva la necesidad de las arquitecturas dinámicamente escalables propuestas en esta tesis. En el capítulo 2 se describen las arquitecturas dinámicamente escalables. Dicha descripción incluye la mayor parte de las aportaciones a nivel arquitectural realizadas en esta tesis. Por su parte, el flujo de diseño adaptado a dichas arquitecturas se propone en el capítulo 3. El motor de reconfiguración se propone en el 4, mientras que el uso de dichas arquitecturas para implementar sistemas de hardware evolutivo se aborda en el 5. El deblocking filter escalable se describe en el 6, mientras que las conclusiones finales de esta tesis, así como la descripción del trabajo futuro, son abordadas en el capítulo 7. ABSTRACT The optimization of system parameters, such as power dissipation, the amount of hardware resources and the memory footprint, has been always a main concern when dealing with the design of resource-constrained embedded systems. This situation is even more demanding nowadays. Embedded systems cannot anymore be considered only as specific-purpose computers, designed for a particular functionality that remains unchanged during their lifetime. Differently, embedded systems are now required to deal with more demanding and complex functions, such as multimedia data processing and high-throughput connectivity. In addition, system operation may depend on external data, the user requirements or internal variables of the system, such as the battery life-time. All these conditions may vary at run-time, leading to adaptive scenarios. As a consequence of both the growing computational complexity and the existence of dynamic requirements, dynamic resource management techniques for embedded systems are needed. Software is inherently flexible, but it cannot meet the computing power offered by hardware solutions. Therefore, reconfigurable hardware emerges as a suitable technology to deal with the run-time variable requirements of complex embedded systems. Adaptive hardware requires the use of reconfigurable devices, where its functionality can be modified on demand. In this thesis, Field Programmable Gate Arrays (FPGAs) have been selected as the most appropriate commercial technology existing nowadays to implement adaptive hardware systems. There are different ways of exploiting reconfigurability in reconfigurable devices. Among them is dynamic and partial reconfiguration. This is a technique which consists in substituting part of the FPGA logic on demand, while the rest of the device continues working. The strategy followed in this thesis is to exploit the dynamic and partial reconfiguration of commercial FPGAs to deal with the flexibility and complexity demands of state-of-the-art embedded systems. The proposal of this thesis to deal with run-time variable system conditions is the use of spatially scalable processing hardware IP cores, which are able to adapt their functionality or performance at run-time, trading them off with the amount of logic resources they occupy in the device. This is referred to as a scalable footprint in the context of this thesis. The distinguishing characteristic of the proposed cores is that they rely on highly parallel, modular and regular architectures, arranged in one or two dimensions. These architectures can be scaled by means of the addition or removal of the composing blocks. This strategy avoids implementing a full version of the core for each possible size, with the corresponding benefits in terms of scaling and adaptation time, as well as bitstream storage memory requirements. Instead of providing specific-purpose architectures, generic architectural templates, which can be tuned to solve different problems, are proposed in this thesis. Architectures following both systolic and wavefront templates have been selected. Together with the proposed scalable architectural templates, other issues needed to ensure the proper design and operation of the scalable cores, such as the device reconfiguration control, the run-time management of the architecture and the implementation techniques have been also addressed in this thesis. With regard to the implementation of dynamically reconfigurable architectures, device dependent low-level details are addressed. Some of the aspects covered in this thesis are the area constrained routing for reconfigurable modules, or an inter-module communication strategy which does not introduce either extra delay or logic overhead. The system implementation, from the hardware description to the device configuration bitstream, has been fully automated by modifying the netlists corresponding to each of the system modules, which are previously generated using the vendor tools. This modification is therefore envisaged as a post-processing step. Based on these implementation proposals, a design tool called DREAMS (Dynamically Reconfigurable Embedded and Modular Systems) has been created, including a graphic user interface. The tool has specific features to cope with modular and regular architectures, including the support for module relocation and the inter-module communications scheme based on the symmetry of the architecture. The core of the tool is a custom router, which has been also exploited in this thesis to obtain symmetric routed nets, with the aim of enhancing the protection of critical reconfigurable circuits against side channel attacks. This is achieved by duplicating the logic with an exactly equal routing. In order to control the reconfiguration process of the FPGA, a Reconfiguration Engine suited to the specific requirements set by the proposed architectures was also proposed. Therefore, in addition to controlling the reconfiguration port, the Reconfiguration Engine has been enhanced with the online relocation ability, which allows employing a unique configuration bitstream for all the positions where the module may be placed in the device. Differently to the existing relocating solutions, which are based on bitstream parsers, the proposed approach is based on the online composition of bitstreams. This strategy allows increasing the speed of the process, while the length of partial bitstreams is also reduced. The height of the reconfigurable modules can be lower than the height of a clock region. The Reconfiguration Engine manages the merging process of the new and the existing configuration frames within each clock region. The process of scaling up and down the hardware cores also benefits from this technique. A direct link to an external memory where partial bitstreams can be stored has been also implemented. In order to accelerate the reconfiguration process, the ICAP has been overclocked over the speed reported by the manufacturer. In the case of Virtex-5, even though the maximum frequency of the ICAP is reported to be 100 MHz, valid operations at 250 MHz have been achieved, including the online relocation process. Portability of the reconfiguration solution to today's and probably, future FPGAs, has been also considered. The reconfiguration engine can be also used to inject faults in real hardware devices, and this way being able to evaluate the fault tolerance offered by the reconfigurable architectures. Faults are emulated by introducing partial bitstreams intentionally modified to provide erroneous functionality. To prove the validity and the benefits offered by the proposed architectures, two demonstration application lines have been envisaged. First, scalable architectures have been employed to develop an evolvable hardware platform with adaptability, fault tolerance and scalability properties. Second, they have been used to implement a scalable deblocking filter suited to scalable video coding. Evolvable Hardware is the use of evolutionary algorithms to design hardware in an autonomous way, exploiting the flexibility offered by reconfigurable devices. In this case, processing elements composing the architecture are selected from a presynthesized library of processing elements, according to the decisions taken by the algorithm, instead of being decided at design time. This way, the configuration of the array may change as run-time environmental conditions do, achieving autonomous control of the dynamic reconfiguration process. Thus, the self-optimization property is added to the native self-configurability of the dynamically scalable architectures. In addition, evolvable hardware adaptability inherently offers self-healing features. The proposal has proved to be self-tolerant, since it is able to self-recover from both transient and cumulative permanent faults. The proposed evolvable architecture has been used to implement noise removal image filters. Scalability has been also exploited in this application. Scalable evolvable hardware architectures allow the autonomous adaptation of the processing cores to a fluctuating amount of resources available in the system. Thus, it constitutes an example of the dynamic quality scalability tackled in this thesis. Two variants have been proposed. The first one consists in a single dynamically scalable evolvable core, and the second one contains a variable number of processing cores. Scalable video is a flexible approach for video compression, which offers scalability at different levels. Differently to non-scalable codecs, a scalable video bitstream can be decoded with different levels of quality, spatial or temporal resolutions, by discarding the undesired information. The interest in this technology has been fostered by the development of the Scalable Video Coding (SVC) standard, as an extension of H.264/AVC. In order to exploit all the flexibility offered by the standard, it is necessary to adapt the characteristics of the decoder to the requirements of each client during run-time. The use of dynamically scalable architectures is proposed in this thesis with this aim. The deblocking filter algorithm is the responsible of improving the visual perception of a reconstructed image, by smoothing blocking artifacts generated in the encoding loop. This is one of the most computationally intensive tasks of the standard, and furthermore, it is highly dependent on the selected scalability level in the decoder. Therefore, the deblocking filter has been selected as a proof of concept of the implementation of dynamically scalable architectures for video compression. The proposed architecture allows the run-time addition or removal of computational units working in parallel to change its level of parallelism, following a wavefront computational pattern. Scalable architecture is offered together with a scalable parallelization strategy at the macroblock level, such that when the size of the architecture changes, the macroblock filtering order is modified accordingly. The proposed pattern is based on the division of the macroblock processing into two independent stages, corresponding to the horizontal and vertical filtering of the blocks within the macroblock. The main contributions of this thesis are: - The use of highly parallel, modular, regular and local architectures to implement dynamically reconfigurable processing IP cores, for data intensive applications with flexibility requirements. - The use of two-dimensional mesh-type arrays as architectural templates to build dynamically reconfigurable IP cores, with a scalable footprint. The proposal consists in generic architectural templates, which can be tuned to solve different computational problems. •A design flow and a tool targeting the design of DPR systems, focused on highly parallel, modular and local architectures. - An inter-module communication strategy, which does not introduce delay or area overhead, named Virtual Borders. - A custom and flexible router to solve the routing conflicts as well as the inter-module communication problems, appearing during the design of DPR systems. - An algorithm addressing the optimization of systems composed of multiple scalable cores, which size can be decided individually, to optimize the system parameters. It is based on a model known as the multi-dimensional multi-choice Knapsack problem. - A reconfiguration engine tailored to the requirements of highly regular and modular architectures. It combines a high reconfiguration throughput with run-time module relocation capabilities, including the support for sub-clock reconfigurable regions and the replication in multiple positions. - A fault injection mechanism which takes advantage of the system reconfiguration engine, as well as the modularity of the proposed reconfigurable architectures, to evaluate the effects of transient and permanent faults in these architectures. - The demonstration of the possibilities of the architectures proposed in this thesis to implement evolvable hardware systems, while keeping a high processing throughput. - The implementation of scalable evolvable hardware systems, which are able to adapt to the fluctuation of the amount of resources available in the system, in an autonomous way. - A parallelization strategy for the H.264/AVC and SVC deblocking filter, which reduces the number of macroblock cycles needed to process the whole frame. - A dynamically scalable architecture that permits the implementation of a novel deblocking filter module, fully compliant with the H.264/AVC and SVC standards, which exploits the macroblock level parallelism of the algorithm. This document is organized in seven chapters. In the first one, an introduction to the technology framework of this thesis, specially focused on dynamic and partial reconfiguration, is provided. The need for the dynamically scalable processing architectures proposed in this work is also motivated in this chapter. In chapter 2, dynamically scalable architectures are described. Description includes most of the architectural contributions of this work. The design flow tailored to the scalable architectures, together with the DREAMs tool provided to implement them, are described in chapter 3. The reconfiguration engine is described in chapter 4. The use of the proposed scalable archtieectures to implement evolvable hardware systems is described in chapter 5, while the scalable deblocking filter is described in chapter 6. Final conclusions of this thesis, and the description of future work, are addressed in chapter 7.