Energy recovery from high-frequency clocks using DC-DC converters

Large digital chips use a significant amount of energy to distribute a multi-GHz clock. By discharging the clock network to ground every cycle, the energy stored in this large capacitor is wasted. Instead, the energy can be recovered using an on-chip DC-DC converter. This paper investigates the integration of two DC-DC converter topologies, boost and buck-boost, with a high-speed clock driver. The high operating frequency significantly shrinks the required size of the L and C components so they can be placed on-chip; typical converters place them off-chip. The clock driver and DC-DC converter are able to share the entire tapered buffer chain, including the widest drive transistors in the final stage. To achieve voltage regulation, the clock duty cycle must be modulated; implying only single-edge-triggered flops should be used. However, this minor drawback is eclipsed by the benefits: by recovering energy from the clock, the output power can actually exceed the additional power needed to operate the converter circuitry, resulting in an effective efficiency greater than 100%. Furthermore, the converter output can be used to operate additional power-saving features like low-voltage islands or body bias voltages. ©2008 IEEE.

Conduction bottleneck in silicon nanochain single electron transistors operating at room temperature

Single electron transistors are fabricated on single Si nanochains, synthesised by thermal evaporation of SiO solid sources. The nanochains consist of one-dimensional arrays of ~10nm Si nanocrystals, separated by SiO 2 regions. At 300 K, strong Coulomb staircases are seen in the drain-source current-voltage (I ds-V ds) characteristics, and single-electron oscillations are seen in the drain-source current-gate voltage (I ds-V ds) characteristics. From 300-20 K, a large increase in the Coulomb blockade region is observed. The characteristics are explained using singleelectron Monte Carlo simulation, where an inhomogeneous multiple tunnel junction represents a nanochain. Any reduction in capacitance at a nanocrystal well within the nanochain creates a conduction " bottleneck", suppressing current at low voltage and improving the Coulomb staircase. The single-electron charging energy at such an island can be very high, ~20k BT at 300 K. © 2012 The Japan Society of Applied Physics.

Electron-beam-induced direct etching of graphene

We present electron-beam-induced oxidation of single- and bilayer graphene devices in a low-voltage scanning electron microscope. We show that the injection of oxygen leads to targeted etching at the focal point, enabling us to pattern graphene with a resolution of better than 20 nm. Voltage-contrast imaging, in conjunction with finite-element simulations, explain the secondary-electron intensities and correlate them to the etch profile. © 2013 Elsevier Ltd. All rights reserved.

Experimental LVRT performance of a 250 kW brushless DFIG

Nowadays, all new wind turbine generators have to meet strict grid codes, especially riding through certain grid faults, such as a low voltage caused by grid short circuits. The Low-Voltage Ride Through (LVRT) capability has become a key issue in assessing the performance of wind turbine generators. The mediumspeed Brushless DFIG in combination with a simplified two-stage gearbox shows commercial promise as a replacement for conventional DFIGs due to its lower cost and higher reliability. Furthermore, the Brushless DFIG has significantly improved LVRT performance when compared with the DFIG due to its inherent design characteristics. In this paper, the authors propose a control strategy for the Brushless DFIG to improve its LVRT performance. The controller has been implemented on a prototype 250 kW Brushless DFIG and test results show that LVRT is possible without a need for any external protective hardware such as a crowbar.

Performance analysis and testing of a 250 kW medium-speed brushless doubly-fed induction generator

This study presents the performance analysis and testing of a 250 kW medium-speed brushless doubly-fed induction generator (DFIG), and its associated power electronics and control systems. The experimental tests confirm the design, and showthe system's steady-state and dynamic performance and grid low-voltage ride- through capability. The medium-speed brushless DFIG in combination with a simplified two-stage gearbox promises a low-cost low-maintenance and reliable drivetrain for wind turbine applications. © The Institution of Engineering and Technology 2013.

Optimising the dynamic performance of an all-wide-bandgap cascode switch

A SPICE simulation model of a novel cascode switch that combines a high voltage normally-on silicon carbide (SiC) junction field effect transistor (JFET) with a low voltage enhancement-mode gallium nitride field effect transistor (eGaN FET) has been developed, with the aim of optimising cascode switching performance. The effect of gate resistance on stability and switching losses is investigated and optimum values chosen. The effects of stray inductance on cascode switching performance are considered and the benefits of low inductance packaging discussed. The use of a positive JFET gate bias in a cascode switch is shown to reduce switching losses as well as reducing on-state losses. The findings of the simulation are used to produce a list of priorities for the design and layout of wide-bandgap cascode switches, relevant to both SiC and GaN high voltage devices. © 2013 IEEE.

A study of converter rating for brushless DFIG wind turbines

This paper studies the converter rating requirement of a Brushless Doubly-Fed Induction Generator for wind turbine applications by considering practical constraints such as generator torque-speed requirement, reactive power management and grid low-voltage ride-through (LVRT). Practical data have been used to obtain a realistic system model of a Brushless DFIG wind turbine using steady-state and dynamic models. A converter rating optimization is performed based on the given constraints. The converter current and voltage requirements are examined and the resulting inverter rating is compared to optimization algorithm results. In addition, the effects of rotor leakage inductance on LVRT performance and hence converter rating is investigated.

Stretchable liquid-crystal blue-phase gels.

Liquid-crystalline polymers are materials of considerable scientific interest and technological value. An important subset of these materials exhibit rubber-like elasticity, combining the optical properties of liquid crystals with the mechanical properties of rubber. Moreover, they exhibit behaviour not seen in either type of material independently, and many of their properties depend crucially on the particular mesophase employed. Such stretchable liquid-crystalline polymers have previously been demonstrated in the nematic, chiral-nematic, and smectic mesophases. Here, we report the fabrication of a stretchable gel of blue phase I, which forms a self-assembled, three-dimensional photonic crystal that remains electro-optically switchable under a moderate applied voltage, and whose optical properties can be manipulated by an applied strain. We also find that, unlike its undistorted counterpart, a mechanically deformed blue phase exhibits a Pockels electro-optic effect, which sets out new theoretical challenges and possibilities for low-voltage electro-optic devices.

A Fully Integrated 900-MHz Passive RFID Transponder Front End With Novel Zero-Threshold RF-DC Rectifier

This paper presents a fully integrated CMOS analog front end for a passive 900-MHz radio-frequency identification (RFID) transponder. The power supply in this front end is generated from the received RF electromagnetic energy by using an RF-dc voltage rectifier. In order to improve the compatibility with standard CMOS technology, Schottky diodes in conventional RF-dc rectifiers are replaced by diode-connected MOS transistors with zero threshold. Meanwhile, theoretical analyses for the proposed rectifier are provided and verified by both simulation and measurement results. The design considerations of the pulsewidth-modulation (PWM) demodulator and the backscatter modulator in the front end are also discussed for low-power applications. The proposed front end is implemented in a 0.35-mu m 2P4M CMOS technology. The whole chip occupies a die area of 490 x 780 mu m(2) and consumes only 2.1 mu W in reading mode under a self-generated 1.5-V supply voltage. The measurement results show that the proposed rectifier can properly operate with a - 14.7-dBm input RF power at a power conversion efficiency of 13.0%. In the proposed RFID applications, this sensitivity corresponds to 10.88-m communication distance at 4-W equivalent isotropically radiated power from a reader base station.

Design and fabrication of 1.06 mu m resonant-cavity enhanced reflective modulator with GaInAs/GaAs quantum wells

A resonant-cavity enhanced reflective optical modulator is designed and frabricated, with three groups of three highly strained InGaAS/GaAs quantum wells in the cavity, for the low voltage and high contrast ratio operation. The quantum wells are positioned in antinodes of the optical standing wave. The modulator is grown in a single growth step in an molecular beam epitaxy system, using GaAs/AIAs distributed Bragg reflectors as both the top and bottom mirrors. Results show that the reflection device has a modulation extinction of 3 dB at -4.5 V bias.

A novel DC-DC charge pump circuit for passive RFID transponder

This paper presents a low-voltage, high performance charge pump circuit suitable for implementation in standard CMOS technologies. The proposed charge pump has been used as a part of the power supply section of fully integrated passive radio frequency identification(RFID) transponder IC, which has been implemented in a 0.35-um CMOS technology with embedded EEPROM offered by Chartered Semiconductor. The proposed DC/DC charge pump can generate stable output for RFID applications with low power dissipation and high pumping efficiency. The analytical model of the voltage multiplier, the comparison with other charge pumps, the simulation results, and the chip testing results are presented.

VCSEL-based parallel optical transmission module

This paper describes the design process and performance of the optimized parallel optical transmission module. Based on 1x12 VCSEL (Vertical Cavity Surface Emitting Laser) array, we designed and fabricated the high speed parallel optical modules. Our parallel optical module contains a 1x12 VCSEL array, a 12 channel CMOS laser driver circuit, a high speed PCB (Printed Circuit Board), a MT fiber connector and a packaging housing. The L-I-V characteristics of the 850nm VCSEL was measured at the operating current 8mA, 3dB frequency bandwidth more than 3GHz and the optical output 1mW. The transmission rate of all 12 channels is 30Gbit/s, with a single channel 2.5Gbit/s. By adopting the integration of the 1x12 VCSEL array and the driver array, we make a high speed PCB (Printed Circuit Board) to provide the optoelectronic chip with the operating voltage and high speed signals current. The LVDS (Low-Voltage Differential Signals) was set as the input signal to achieve better high frequency performance. The active coupling was adopted with a MT connector (8 degrees slant fiber array). We used the Small Form Factor Pluggable (SFP) packaging. With the edge connector, the module could be inserted into the system dispense with bonding process.

CMOS兼容光电单片接收机的模拟与设计

设计了与CMOS工艺兼容的光电单片接收机电路，其中包括光电探测器、前置放大器和主放大器。它采用0.6μm CMOS工艺，可在自血的高阻外延片上使用MPW (multi-project wafer)进行流水。其中光电探测器的工作波长为850nm，响应度为0.2A/W，接收灵敏度为-16dBm，带宽为800MHz，因此适用于VSR(versy short reach)系统。前置放大器采用电流模反馈放大器，主放大器输出为LVDS(low voltage differential signals)电平。通过器件模拟与电路模拟统一的方法将光电探测器与接收机放大电路进行统一模拟，分析了电路的限制因素，并提出了相应的改进方法。

Kicker电源数字延迟线及低压监测系统设计

踢轨磁铁（Kicker）电源系统是HIRFL-CSR注入引出系统中实现快引出的一个关键元件，主要功能是为踢轨磁铁提供快脉冲励磁电流以产生所需要的快脉冲磁场。Kicker电源提供的是高电压大电流的快脉冲，电流脉冲上升沿和下降沿为150ns,脉冲宽度为650ns,其脉冲峰值电流为2700A，工作周期为10s-17s。因此及时监控Kicker电源闸流管的工作状况以及电流脉冲波形特性至关重要。本文针对踢轨磁铁（Kicker）电源的需要，进行了Kicker电源监测系统的设计，主要针对闸流管误漏导通检测、电流脉冲宽度过宽过窄检测、脉冲宽度测量及脉冲计数等功能提出了电路的工作原理，并设计了具体电路。系统输入端采用光纤接口，而输出端采用了PLC数字I/O接口。由于采用PLC接收监测电路板的信号来完成对Kicker电源的监控报警，基于此编写了相关PLC程序，并调试通过。该监测系统电路板已调试完成，可以很好地完成对Kicker电源系统较为全面的状态监测，方便地对Kicker电源系统状态进行监控。另外，为了解决Kicker电源系统脉冲同步的问题，以满足兰州重离子加速器冷却储存环（HIRFL-CSR）环踢轨磁铁（Kicker）电源对电流脉冲进行适当延迟的要求，还分别设计了ECL高速可程控数字延迟线电路系统和基于CPLD的数字延迟线系统，分析介绍了数字延迟线系统结构、工作原理及PCB版图设计等。ECL高速可程控数字延迟线电路已初步调试通过，而基于CPLD的数字延迟线系统已完成了程序编程及仿真工作，它克服了ECL数字延迟线不能实现零延迟的缺点，且可以通过修改VHDL程序来设置出更多位的可编程数字延迟线，方便灵活

Kicker电源数字延迟线及低压监测系统设计

踢轨磁铁（Kicker）电源系统是兰州重离子加速器冷却储存环（HIRFL-CSR）注入引出系统中实现快引出的一个关键元件，主要功能是为踢轨磁铁提供快脉冲励磁电流以产生所需要的快脉冲磁场。踢轨磁铁（Kicker）电源系统各触发脉冲是否同步关系到束流能否顺利注入引出以及有好的束流品质。基于此，本文介绍了基于CPLD-EPM1270T144的数字延迟线系统，以满足HIRFL-CSR踢轨磁铁（Kicker）电源对触发脉冲进行适当延迟的要求；分析介绍了数字延迟线系统结构、工作原理、PCB制版及系统调试。实际检验证明本设计通过修改VHDL程序来调节延迟时间能够方便灵活的完成Kicker电源系统对脉冲同步的要求，延迟精度达到10ns。另外，由于Kicker电源提供的是高电压大电流的快脉冲，电流脉冲上升沿和下降沿为150ns、脉冲宽度为650ns,其脉冲峰值电流为2700A、工作周期为10s-17s，因此及时监控Kicker电源闸流管的工作状况以及电流脉冲波形特性非常重要。基于此，本文还进行了Kicker电源监测系统的设计。该设计主要针对闸流管误漏导通检测、电流脉冲宽度过宽过窄检测、脉冲宽度测量及脉冲计数等功能提出了电路的系统结构、工作原理，并完成了程序编程、仿真及外围电路设计