Boy on gate to Ferry Field, Commencement, June 1940

Original image is missing. Duplicate in Bentley Historical Library record group, Box 10, Daybook image #1

Ferry Field [Gate at northeast corner]

Regents purchased south ten acres for $3000 in 1890. In 1902 UM received seven acres of land to the north from Dexter M. Ferry; became Ferry Field. In 1904 brick wall constructed on three sides and in 1906 gate and ticket office at northeast corner added (gift of Mr. Ferry). Wooden stands to accommodate 400 put up in 1893; burned in 1895. Rebuilt to seat 800 with later additions to facililties. By 1914, 13,600 accommodated. New stadium built in 1927.

Ferry Field. Football. Northeast gate

Regents purchased south ten acres for $3000 in 1890. In 1902 UM received seven acres of land to the north from Dexter M. Ferry; became Ferry Field. In 1904 brick wall constructed on three sides and in 1906 gate and ticket office at northeast corner added (gift of Mr. Ferry). Wooden stands to accommodate 400 put up in 1893; burned in 1895. Rebuilt to seat 800 with later additions to facililties. By 1914, 13,600 accommodated. New stadium built in 1927.

Fan's looking through Ferry Field gate

[side gate off State Street]

Ferry Field Gate, ca 1907

[cropped from image bl004238]

Ferry Field Gate, ca 1907

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Quantum gate based on Stark tunable nanocrystal interactions with ultrahigh-Q/V field modes in fused silica microcavities

We investigate the use of nanocrystal quantum dots as a quantum bus element for preparing various quantum resources for use in photonic quantum technologies. Using the Stark-tuning property of nanocrystal quantum dots as well as the biexciton transition, we demonstrate a photonic controlled-NOT (CNOT) interaction between two logical photonic qubits comprising two cavity field modes each. We find the CNOT interaction to be a robust generator of photonic Bell states, even with relatively large biexciton losses. These results are discussed in light of the current state of the art of both microcavity fabrication and recent advances in nanocrystal quantum dot technology. Overall, we find that such a scheme should be feasible in the near future with appropriate refinements to both nanocrystal fabrication technology and microcavity design. Such a gate could serve as an active element in photonic-based quantum technologies.

Enhancement of field emission from multistage structure of carbon nanotube arrays

The field emission measurements for the multistage structured nanotubes (i.e., thin-multiwall and single wall carbon nanotubes grown on multiwall carbon nanotubes) were carried out and a low turn-on field of ~0.45 V/ μm, high emission current of 450 μA at a field of IV/μm and a large field enhancement factor of ~26200 were obtained. The thin multiwall carbon nanotubes (thin-MWNTs) and single wall carbon nanotubes (SWNTs) were grown on the regular arrays of vertically aligned multi wall carbon nanotubes (MWNTs) on porous silicon substrate by Chemical Vapor Deposition (CVD) method. The thin-MWNTs and SWNTs grown on MWNTs in this way have a multistage structure which gives higher enhancement of the electric field and hence the electron field emission.

A III-V channel field effect transistor for non-classical CMOS: process optimisation for improved gate stack function

This thesis describes a collection of studies into the electrical response of a III-V MOS stack comprising metal/GaGdO/GaAs layers as a function of fabrication process variables and the findings of those studies. As a result of this work, areas of improvement in the gate process module of a III-V heterostructure MOSFET were identified. Compared to traditional bulk silicon MOSFET design, one featuring a III-V channel heterostructure with a high-dielectric-constant oxide as the gate insulator provides numerous benefits, for example: the insulator can be made thicker for the same capacitance, the operating voltage can be made lower for the same current output, and improved output characteristics can be achieved without reducing the channel length further. It is known that transistors composed of III-V materials are most susceptible to damage induced by radiation and plasma processing. These devices utilise sub-10 nm gate dielectric films, which are prone to contamination, degradation and damage. Therefore, throughout the course of this work, process damage and contamination issues, as well as various techniques to mitigate or prevent those have been investigated through comparative studies of III-V MOS capacitors and transistors comprising various forms of metal gates, various thicknesses of GaGdO dielectric, and a number of GaAs-based semiconductor layer structures. Transistors which were fabricated before this work commenced, showed problems with threshold voltage control. Specifically, MOSFETs designed for normally-off (VTH > 0) operation exhibited below-zero threshold voltages. With the results obtained during this work, it was possible to gain an understanding of why the transistor threshold voltage shifts as the gate length decreases and of what pulls the threshold voltage downwards preventing normally-off device operation. Two main culprits for the negative VTH shift were found. The first was radiation damage induced by the gate metal deposition process, which can be prevented by slowing down the deposition rate. The second was the layer of gold added on top of platinum in the gate metal stack which reduces the effective work function of the whole gate due to its electronegativity properties. Since the device was designed for a platinum-only gate, this could explain the below zero VTH. This could be prevented either by using a platinum-only gate, or by matching the layer structure design and the actual gate metal used for the future devices. Post-metallisation thermal anneal was shown to mitigate both these effects. However, if post-metallisation annealing is used, care should be taken to ensure it is performed before the ohmic contacts are formed as the thermal treatment was shown to degrade the source/drain contacts. In addition, the programme of studies this thesis describes, also found that if the gate contact is deposited before the source/drain contacts, it causes a shift in threshold voltage towards negative values as the gate length decreases, because the ohmic contact anneal process affects the properties of the underlying material differently depending on whether it is covered with the gate metal or not. In terms of surface contamination; this work found that it causes device-to-device parameter variation, and a plasma clean is therefore essential. This work also demonstrated that the parasitic capacitances in the system, namely the contact periphery dependent gate-ohmic capacitance, plays a significant role in the total gate capacitance. This is true to such an extent that reducing the distance between the gate and the source/drain ohmic contacts in the device would help with shifting the threshold voltages closely towards the designed values. The findings made available by the collection of experiments performed for this work have two major applications. Firstly, these findings provide useful data in the study of the possible phenomena taking place inside the metal/GaGdO/GaAs layers and interfaces as the result of chemical processes applied to it. In addition, these findings allow recommendations as to how to best approach fabrication of devices utilising these layers.

Study of high-quality ALD gate dielectrics in radiation sensitive oxide field effect transistors

Radiation dosimetry is crucial in many fields, where the exposure of ionizing radiation must be precisely controlled to avoid health and environmental safety issues. Radiotherapy and radioprotection are two examples in which fast and reliable detectors are needed. Compact and large area wearable detectors are being developed to address real-life radiation dosimetry applications, their ideal properties include flexibility, lightness, and low-cost. This thesis contributed to the development of Radiation sensitive OXide Field Effect Transistors (ROXFETs), which are detectors able to provide fast and real-time radiation read out. ROXFETs are based on thin film transistors fabricated with high-mobility amorphous oxide semiconductor, making them compatible with large area, flexible, and low cost production over plastic substrates. The gate dielectric material has high dielectric constant and high atomic number, which results in high performances and high radiation sensitivity, respectively. The aim of this work was to establish a stable and reliable fabrication process for ROXFETs made with atomic layer deposited gate dielectric. A study on the effect of gate dielectric materials was performed, focusing the attention on the properties of the dielectric-semiconductor interface. Single and multi layer dielectric structures were compared during this work. Furthermore, the effect of annealing temperature was studied. The device performances were tested to understand the underlying physical processes. In this way, it was possible to determine a reliable fabrication procedure and an optimal structure for ROXFETs. An outstanding sensitivity of (65±3)V/Gy was measured in detectors with a bi-layer Ta₂O₅-Al₂O₃ gate dielectric with low temperature annealing performed at 180°C.

Bilayer graphene dual-gate nanodevice: An ab initio simulation

We study the electronic transport properties of a dual-gated bilayer graphene nanodevice via first-principles calculations. We investigate the electric current as a function of gate length and temperature. Under the action of an external electrical field we show that even for gate lengths up 100 angstrom, a nonzero current is exhibited. The results can be explained by the presence of a tunneling regime due the remanescent states in the gap. We also discuss the conditions to reach the charge neutrality point in a system free of defects and extrinsic carrier doping.

Low-frequency noise and static analysis of the impact of the TiN metal gate thicknesses on n- and p-channel MuGFETs

The impact of the titanium nitride (TIN) gate electrode thickness has been investigated in n and p channel SOI multiple gate field effect transistors (MuGFETs) through low frequency noise charge pumping and static measurements as well as capacitance-voltage curves The results suggest that a thicker TIN metal gate electrode gives rise to a higher EOT a lower mobility and a higher interface trap density The devices have also been studied for different back gate biases where the GIFBE onset occurs at lower front-gate voltage for thinner TIN metal gate thickness and at higher V(GF) In addition it is demonstrated that post deposition nitridation of the MOCVD HfSiO gate dielectric exhibits an unexpected trend with TIN gate electrode thickness where a continuous variation of EOT and an increase on the degradation of the interface quality are observed (C) 2010 Elsevier Ltd All rights reserved