976 resultados para CMOS transistor
Resumo:
An 8 × 8 pipelined parallel multiplier which uses the Dadda scheme is presented. The multiplier has been implemented in a 3-μm n-well CMOS process with two layers of metal using a standard cell automatic placement and routing program. The design uses a form of pipelined carry look-ahead adder in the final stage of summation, thus providing a significant contribution to the high performance of the multiplier. The design is expected to operate at a clock frequency of at least 50 MHz and has a flush time of seven clock cycles. The design illustrates a possible method of implementing an irregular architecture in VLSI using multiple levels of low-resistance, low-capacitance interconnect and automated layout techniques.
Resumo:
A new idea of power device, which contains highly nitrogen-doped CVD diamond and Schottky contact, is proposed to actualise a power device with diamond. Two-dimensional simulation is conducted using ISE TCAD device simulator. While comparably high current is obtained in a transient simulation as expected, this current does not contribute to the drain-source current because of the symmetry of the device. Using an asymmetric structure or bias conditions, the device has high potential as an electric device for extremely high power, high frequency and high temperature. © 2003 Elsevier Science B.V. All rights reserved.
Resumo:
We demonstrate a room temperature processed ferroelectric (FE) nonvolatile memory based on a ZnO nanowire (NW) FET where the NW channel is coated with FE nanoparticles. A single device exhibits excellent memory characteristics with the large modulation in channel conductance between ON and OFF states exceeding 10(4), a long retention time of over 4 × 10(4) s, and multibit memory storage ability. Our findings provide a viable way to create new functional high-density nonvolatile memory devices compatible with simple processing techniques at low temperature for flexible devices made on plastic substrates.
Resumo:
Here we demonstrate a novel technique to grow carbon nanotubes (CNTs) on addressable localized areas, at wafer level, on a fully processed CMOS substrate. The CNTs were grown using tungsten micro-heaters (local growth technique) at elevated temperature on wafer scale by connecting adjacent micro-heaters through metal tracks in the scribe lane. The electrical and optical characterization show that the CNTs are identical and reproducible. We believe this wafer level integration of CNTs with CMOS circuitry enables the low-cost mass production of CNT sensors, such as chemical sensors.
Resumo:
The integration of multiple functionalities into individual nanoelectronic components is increasingly explored as a means to step up computational power, or for advanced signal processing. Here, we report the fabrication of a coupled nanowire transistor, a device where two superimposed high-performance nanowire field-effect transistors capable of mutual interaction form a thyristor-like circuit. The structure embeds an internal level of signal processing, showing promise for applications in analogue computation. The device is naturally derived from a single NW via a self-aligned fabrication process.
Resumo:
The direct deposition of carbon nanotubes on CMOS microhotplates is demonstrated in this paper. Tungsten microhotplates, fabricated on thin SOI membranes aside CMOS control circuitry, are used to locally grow carbon nanotubes by chemical vapour deposition. Unlike bulk heating of the entire chip, which could cause degradation to CMOS devices and interconnects due to high growth temperatures in excess of 500 °C, this novel technique allows carbon nanotubes to be grown on-chip in localized regions. The microfabricated heaters are thermally isolated from the rest of the CMOS chip as they are on the membranes. This allows carbon nanotubes to be grown alongside CMOS circuitry on the same wafer without any external heating, thus enabling new applications (e.g. smart gas sensing) where the integration of CMOS and carbon nanotubes is required.
Resumo:
This paper describes the growth of Carbon Nanotubes (CNTs) both aligned and non-aligned on fully processed CMOS substrates containing high temperature tungsten metallization. While the growth method has been demonstrated in fabricating CNT gas sensitive layers for high temperatures SOI CMOS sensors, it can be employed in a variety of applications which require the use of CNTs or other nanomaterials with CMOS electronics. In our experiments we have grown CNTs both on SOI CMOS substrates and SOI CMOS microhotplates (suspended on membranes formed by post-CMOS deep RIE etching). The fully processed SOI substrates contain CMOS devices and circuits and additionally, some wafers contained high current LDMOSFETs and bipolar structures such as Lateral Insulated Gate Bipolar Transistors. All these devices were used as test structures to investigate the effect of additional post-CMOS processing such as CNT growth, membrane formation, high temperature annealing, etc. Electrical characterisation of the devices with CNTs were performed along with SEM and Raman spectroscopy. The CNTs were grown both at low and high temperatures, the former being compatible with Aluminium metallization while the latter being possible through the use of the high temperature CMOS metallization (Tungsten). In both cases we have found that there is no change in the electrical behaviour of the CMOS devices, circuits or the high current devices. A slight degradation of the thermal performance of the CMOS microhotplates was observed due to the extra heat dissipation path created by the CNT layers, but this is expected as CNTs exhibit a high thermal conductance. In addition we also observed that in the case of high temperature CNT growth a slight degradation in the manufacturing yield was observed. This is especially the case where large area membranes with a diameter in excess of 500 microns are used.
Resumo:
We have studied the response of a sol-gel based TiO(2), high k dielectric field effect transistor structure to microwave radiation. Under fixed bias conditions the transistor shows frequency dependent current fluctuations when exposed to continuous wave microwave radiation. Some of these fluctuations take the form of high Q resonances. The time dependent characteristics of these responses were studied by modulating the microwaves with a pulse signal. The measurements show that there is a shift in the centre frequency of these high Q resonances when the pulse time is varied. The measured lifetime of these resonances is high enough to be useful for non-classical information processing.