The influence of the Palestinian sociocultural values in shaping the vernacular architecture of Nablus city

Recently, environmental architecture and sustainable construction has been ranked on top of the worldâ s interests. Making use of natural resources helps in reducing energy consumption and costs associated with the operation of buildings. The current architectural approaches and designs in Palestine are far away from environmental concepts, copying and simulating abroad approaches, without taking into account the culture, climate, and inhabitant's needs. On the contrast, vernacular architecture has achieved environmental concepts and has given suitable approaches and samples - without any need to simulate or copy - which come from people and land. This paper discusses how the Palestinian socio-cultural context shaped the residential vernacular architecture in Palestine, taking the old city of Nablus as a case-study. The research concept depends on analysing and trying to understand the effect of the socio-cultural context on vernacular architecture and trying to reach some rules or understandings of how it works in order to reach a modern environmental dwelling that is suitable to this concept. The research method goes through analysing study cases from the traditional architecture models and the Nablus city is selected as a case study. This analytical and qualitative method can lead to deep understanding for how to benefit from vernacular architecture in Palestine in finding the future environmental residential construction. One of the main findings of this research is to set general and special rules for building sustainable buildings in Palestine from the socio-cultural point view, in order to be a reference for designers, stakeholders, ministry of planning, and municipalities.

A modular traffic sampling architecture for flexible network measurements

Dissertação de Mestrado (Programa Doutoral em Informática)

Towards a pervasive data mining engine: architecture overview

Current data mining engines are difficult to use, requiring optimizations by data mining experts in order to provide optimal results. To solve this problem a new concept was devised, by maintaining the functionality of current data mining tools and adding pervasive characteristics such as invisibility and ubiquity which focus on their users, providing better ease of use and usefulness, by providing autonomous and intelligent data mining processes. This article introduces an architecture to implement a data mining engine, composed by four major components: database; Middleware (control); Middleware (processing); and interface. These components are interlinked but provide independent scaling, allowing for a system that adapts to the user’s needs. A prototype has been developed in order to test the architecture. The results are very promising and showed their functionality and the need for further improvements.

The shoulder architecture of bears and other carnivores [by] D. Dwight Davis.

v.31:no.34(1949)

Cellular DBMS : customizable and autonomous data management using a RISC-style architecture

Magdeburg, Univ., Fak. für Informatik, Diss., 2011

Parallel Architecture Prototype for 60 GHz High Data Rate Wireless Single Carrier Receiver

Nowadays a huge attention of the academia and research teams is attracted to the potential of the usage of the 60 GHz frequency band in the wireless communications. The use of the 60GHz frequency band offers great possibilities for wide variety of applications that are yet to be implemented. These applications also imply huge implementation challenges. Such example is building a high data rate transceiver which at the same time would have very low power consumption. In this paper we present a prototype of Single Carrier -SC transceiver system, illustrating a brief overview of the baseband design, emphasizing the most important decisions that need to be done. A brief overview of the possible approaches when implementing the equalizer, as the most complex module in the SC transceiver, is also presented. The main focus of this paper is to suggest a parallel architecture for the receiver in a Single Carrier communication system. This would provide higher data rates that the communication system canachieve, for a price of higher power consumption. The suggested architecture of such receiver is illustrated in this paper,giving the results of its implementation in comparison with its corresponding serial implementation.

A Novel Memory-centric Architecture and Organization of Processors and Computers

The modern computer systems that are in use nowadays are mostly processor-dominant, which means that their memory is treated as a slave element that has one major task – to serve execution units data requirements. This organization is based on the classical Von Neumann's computer model, proposed seven decades ago in the 1950ties. This model suffers from a substantial processor-memory bottleneck, because of the huge disparity between the processor and memory working speeds. In order to solve this problem, in this paper we propose a novel architecture and organization of processors and computers that attempts to provide stronger match between the processing and memory elements in the system. The proposed model utilizes a memory-centric architecture, wherein the execution hardware is added to the memory code blocks, allowing them to perform instructions scheduling and execution, management of data requests and responses, and direct communication with the data memory blocks without using registers. This organization allows concurrent execution of all threads, processes or program segments that fit in the memory at a given time. Therefore, in this paper we describe several possibilities for organizing the proposed memory-centric system with multiple data and logicmemory merged blocks, by utilizing a high-speed interconnection switching network.

Software for Explicitly Parallel Memory-Centric Processor Architecture

Advances in computer memory technology justify research towards new and different views on computer organization. This paper proposes a novel memory-centric computing architecture with the goal to merge memory and processing elements in order to provide better conditions for parallelization and performance. The paper introduces the architectural concepts and afterwards shows the design and implementation of a corresponding assembler and simulator.

Ostrich egg-shell cups of Mesopotamia and the ostrich in ancient and modern times / by Berthold Laufer. 9 plates and 10 text-figures.

no.23(1926)

Restoration of ancient bronzes and cure of malignant patina / by Henry W. Nichols -- foreword by Berthold Laufer -- Oliver C. Farrington -- editor.

no.3(1930)

Sino-Iranica; Chinese contributions to the history of civilization in ancient Iran, with special reference to the history of cultivated plants and products / by Berthold Laufer --

v.15:no.3(1919)

RADIC II: a fault tolerant architecture with flexible dynamic redundancy

The demand for computational power has been leading the improvement of the High Performance Computing (HPC) area, generally represented by the use of distributed systems like clusters of computers running parallel applications. In this area, fault tolerance plays an important role in order to provide high availability isolating the application from the faults effects. Performance and availability form an undissociable binomial for some kind of applications. Therefore, the fault tolerant solutions must take into consideration these two constraints when it has been designed. In this dissertation, we present a few side-effects that some fault tolerant solutions may presents when recovering a failed process. These effects may causes degradation of the system, affecting mainly the overall performance and availability. We introduce RADIC-II, a fault tolerant architecture for message passing based on RADIC (Redundant Array of Distributed Independent Fault Tolerance Controllers) architecture. RADIC-II keeps as maximum as possible the RADIC features of transparency, decentralization, flexibility and scalability, incorporating a flexible dynamic redundancy feature, allowing to mitigate or to avoid some recovery side-effects.