The shoulder architecture of bears and other carnivores [by] D. Dwight Davis.

v.31:no.34(1949)

Cellular DBMS : customizable and autonomous data management using a RISC-style architecture

Magdeburg, Univ., Fak. für Informatik, Diss., 2011

Parallel Architecture Prototype for 60 GHz High Data Rate Wireless Single Carrier Receiver

Nowadays a huge attention of the academia and research teams is attracted to the potential of the usage of the 60 GHz frequency band in the wireless communications. The use of the 60GHz frequency band offers great possibilities for wide variety of applications that are yet to be implemented. These applications also imply huge implementation challenges. Such example is building a high data rate transceiver which at the same time would have very low power consumption. In this paper we present a prototype of Single Carrier -SC transceiver system, illustrating a brief overview of the baseband design, emphasizing the most important decisions that need to be done. A brief overview of the possible approaches when implementing the equalizer, as the most complex module in the SC transceiver, is also presented. The main focus of this paper is to suggest a parallel architecture for the receiver in a Single Carrier communication system. This would provide higher data rates that the communication system canachieve, for a price of higher power consumption. The suggested architecture of such receiver is illustrated in this paper,giving the results of its implementation in comparison with its corresponding serial implementation.

A Novel Memory-centric Architecture and Organization of Processors and Computers

The modern computer systems that are in use nowadays are mostly processor-dominant, which means that their memory is treated as a slave element that has one major task – to serve execution units data requirements. This organization is based on the classical Von Neumann's computer model, proposed seven decades ago in the 1950ties. This model suffers from a substantial processor-memory bottleneck, because of the huge disparity between the processor and memory working speeds. In order to solve this problem, in this paper we propose a novel architecture and organization of processors and computers that attempts to provide stronger match between the processing and memory elements in the system. The proposed model utilizes a memory-centric architecture, wherein the execution hardware is added to the memory code blocks, allowing them to perform instructions scheduling and execution, management of data requests and responses, and direct communication with the data memory blocks without using registers. This organization allows concurrent execution of all threads, processes or program segments that fit in the memory at a given time. Therefore, in this paper we describe several possibilities for organizing the proposed memory-centric system with multiple data and logicmemory merged blocks, by utilizing a high-speed interconnection switching network.

Software for Explicitly Parallel Memory-Centric Processor Architecture

Advances in computer memory technology justify research towards new and different views on computer organization. This paper proposes a novel memory-centric computing architecture with the goal to merge memory and processing elements in order to provide better conditions for parallelization and performance. The paper introduces the architectural concepts and afterwards shows the design and implementation of a corresponding assembler and simulator.

Ostrich egg-shell cups of Mesopotamia and the ostrich in ancient and modern times / by Berthold Laufer. 9 plates and 10 text-figures.

no.23(1926)

Restoration of ancient bronzes and cure of malignant patina / by Henry W. Nichols -- foreword by Berthold Laufer -- Oliver C. Farrington -- editor.

no.3(1930)

Sino-Iranica; Chinese contributions to the history of civilization in ancient Iran, with special reference to the history of cultivated plants and products / by Berthold Laufer --

v.15:no.3(1919)

RADIC II: a fault tolerant architecture with flexible dynamic redundancy

The demand for computational power has been leading the improvement of the High Performance Computing (HPC) area, generally represented by the use of distributed systems like clusters of computers running parallel applications. In this area, fault tolerance plays an important role in order to provide high availability isolating the application from the faults effects. Performance and availability form an undissociable binomial for some kind of applications. Therefore, the fault tolerant solutions must take into consideration these two constraints when it has been designed. In this dissertation, we present a few side-effects that some fault tolerant solutions may presents when recovering a failed process. These effects may causes degradation of the system, affecting mainly the overall performance and availability. We introduce RADIC-II, a fault tolerant architecture for message passing based on RADIC (Redundant Array of Distributed Independent Fault Tolerance Controllers) architecture. RADIC-II keeps as maximum as possible the RADIC features of transparency, decentralization, flexibility and scalability, incorporating a flexible dynamic redundancy feature, allowing to mitigate or to avoid some recovery side-effects.

System analysis of a Peer-to-Peer Video-on-Demand architecture: Kangaroo

Architectural design and deployment of Peer-to-Peer Video-on-Demand (P2PVoD) systems which support VCR functionalities is attracting the interest of an increasing number of research groups within the scientific community; especially due to the intrinsic characteristics of such systems and the benefits that peers could provide at reducing the server load. This work focuses on the performance analysis of a P2P-VoD system considering user behaviors obtained from real traces together with other synthetic user patterns. The experiments performed show that it is feasible to achieve a performance close to the best possible. Future work will consider monitoring the physical characteristics of the network in order to improve the design of different aspects of a VoD system.

Siliceous deep-sea sponge Monorhaphis chuni: A potential paleoclimate archive in ancient animals

The deep-sea sponge Monorhaphis chuni forms giant basal spicules, which can reach lengths of 3 m; they represent the largest biogenic silica structures on Earth that is formed from an individual metazoan. The spicules offer a unique opportunity to record environmental change of past oceanic and climatic conditions. A giant spicule collected in the East China Sea in a depth of 1110 m was investigated. The oxygen isotopic composition and Mg/Ca ratios determined along center-to-surface segments are used as geochemical proxies for the assessment of seawater paleotemperatures. Calculations are based on the assumption that the calculated temperature near the surface of the spicule is identical with the average ambient temperature of 4 degrees C. A seawater temperature of 1.9 degrees C is inferred for the beginning of the lifespan of the Monorhaphis specimen. The temperature increases smoothly to 2.3 degrees C, to be followed by sharply increased and variable temperatures up to 6-10 degrees C. In the outer part of the spicule, the inferred seawater temperature is about 4 degrees C. The lifespan of the spicule can be estimated to 11,000 +/- 3000 years using the long-term trend of the inferred temperatures fitted to the seawater temperature age relationships since the Last Glacial Maximum. Specimens of Monorhaphis therefore represents one the oldest living animals on Earth. The remarkable temperature spikes of the ambient seawater occurring 9500-3100 years B.P. are explained by discharges of hydrothermal fluids in the neighborhood of the spicule. The irregular lamellar organization of the spicule and the elevated Mn concentrations during the high-temperature growth are consistent with a hydrothermal fluid input. (C) 2012 Elsevier B.V. All rights reserved.