Pancyclicity of Mobius cubes with faulty nodes

An interconnection network with n nodes is four-pancyclic if it contains a cycle of length l for each integer l with 4 <= l <= n. An interconnection network is fault-tolerant four-pancyclic if the surviving network is four-pancyclic in the presence of faults. The fault-tolerant four-pancyclicity of interconnection networks is a desired property because many classical parallel algorithms can be mapped onto such networks in a communication-efficient fashion, even in the presence of failing nodes or edges. Due to some attractive properties as compared with its hypercube counterpart of the same size, the Mobius cube has been proposed as a promising candidate for interconnection topology. Hsieh and Chen [S.Y. Hsieh, C.H. Chen, Pancyclicity on Mobius cubes with maximal edge faults, Parallel Computing, 30(3) (2004) 407-421.] showed that an n-dimensional Mobius cube is four-pancyclic in the presence of up to n-2 faulty edges. In this paper, we show that an n-dimensional Mobius cube is four-pancyclic in the presence of up to n-2 faulty nodes. The obtained result is optimal in that, if n-1 nodes are removed, the surviving network may not be four-pancyclic. (C) 2005 Elsevier B.V. All rights reserved.

Largest connected component of a star graph with faulty vertices

In order to make a full evaluation of an interconnection network, it is essential to estimate the minimum size of a largest connected component of this network provided the faulty vertices in the network may break its connectedness. Star graphs are recognized as promising candidates for interconnection networks. This article addresses the size of a largest connected component of a faulty star graph. We prove that, in an n-star graph (n >= 3) with up to 2n-4 faulty vertices, all fault-free vertices but at most two form a connected component. Moreover, all fault-free vertices but exactly two form a connected component if and only if the set of all faulty vertices is equal to the neighbourhood of a pair of fault-free adjacent vertices. These results show that star graphs exhibit excellent fault-tolerant abilities in the sense that there exists a large functional network in a faulty star graph.

Epidemic K-Means clustering

The K-Means algorithm for cluster analysis is one of the most influential and popular data mining methods. Its straightforward parallel formulation is well suited for distributed memory systems with reliable interconnection networks. However, in large-scale geographically distributed systems the straightforward parallel algorithm can be rendered useless by a single communication failure or high latency in communication paths. This work proposes a fully decentralised algorithm (Epidemic K-Means) which does not require global communication and is intrinsically fault tolerant. The proposed distributed K-Means algorithm provides a clustering solution which can approximate the solution of an ideal centralised algorithm over the aggregated data as closely as desired. A comparative performance analysis is carried out against the state of the art distributed K-Means algorithms based on sampling methods. The experimental analysis confirms that the proposed algorithm is a practical and accurate distributed K-Means implementation for networked systems of very large and extreme scale.

A general treatment of geometric phases and dynamical invariants

Based only on the parallel-transport condition, we present a general method to compute Abelian or non-Abelian geometric phases acquired by the basis states of pure or mixed density operators, which also holds for nonadiabatic and noncyclic evolution. Two interesting features of the non-Abelian geometric phase obtained by our method stand out: i) it is a generalization of Wilczek and Zee`s non-Abelian holonomy, in that it describes nonadiabatic evolution where the basis states are parallelly transported between distinct degenerate subspaces, and ii) the non-Abelian character of our geometric phase relies on the transitional evolution of the basis states, even in the nondegenerate case. We apply our formalism to a two-level system evolving nonadiabatically under spontaneous decay to emphasize the non- Abelian nature of the geometric phase induced by the reservoir. We also show, through the generalized invariant theory, that our general approach encompasses previous results in the literature. Copyright (c) EPLA, 2008.

WRITING ELECTRONIC FERROMAGNETIC STATES IN A HIGH-TEMPERATURE PARAMAGNETIC NUCLEAR SPIN SYSTEM

In this paper, we use Nuclear Magnetic Resonance (NMR) to write electronic states of a ferromagnetic system into high-temperature paramagnetic nuclear spins. Through the control of phase and duration of radio frequency pulses, we set the NMR density matrix populations, and apply the technique of quantum state tomography to experimentally obtain the matrix elements of the system, from which we calculate the temperature dependence of magnetization for different magnetic fields. The effects of the variation of temperature and magnetic field over the populations can be mapped in the angles of spin rotations, carried out by the RF pulses. The experimental results are compared to the Brillouin functions of ferromagnetic ordered systems in the mean field approximation for two cases: the mean field is given by (i) B = B(0) + lambda M and (ii) B = B(0) + lambda M + lambda`M(3), where B(0) is the external magnetic field, and lambda, lambda` are mean field parameters. The first case exhibits second order transition, whereas the second case has first order transition with temperature hysteresis. The NMR simulations are in good agreement with the magnetic predictions.

Formalization of an architectural model for exception handling coordination based on CA action concepts

Architectures based on Coordinated Atomic action (CA action) concepts have been used to build concurrent fault-tolerant systems. This conceptual model combines concurrent exception handling with action nesting to provide a general mechanism for both enclosing interactions among system components and coordinating forward error recovery measures. This article presents an architectural model to guide the formal specification of concurrent fault-tolerant systems. This architecture provides built-in Communicating Sequential Processes (CSPs) and predefined channels to coordinate exception handling of the user-defined components. Hence some safety properties concerning action scoping and concurrent exception handling can be proved by using the FDR (Failure Divergence Refinement) verification tool. As a result, a formal and general architecture supporting software fault tolerance is ready to be used and proved as users define components with normal and exceptional behaviors. (C) 2010 Elsevier B.V. All rights reserved.

Um método para abordar todo o ciclo de desenvolvimento de aplicações tempo real

Neste trabalho apresenta-se um método de desenvolvimento integrado baseado no paradigma de orientação a objetos, que visa abordar todo o ciclo de desenvolvimento de uma aplicação tempo real. Na fase de especificação o método proposto baseia-se no uso de restrições temporais padronizadas pelo perfil da UML-TR, sendo que uma alternativa de mapeamento destas restrições para o nível de programação é apresentada. Este mapeamento serve para guiar a fase de projeto, onde utilizou-se como alvo a interface de programação orientada a objetos denominada TAFT-API, a qual foi projetada para atuar junto ao ambiente de execução desenvolvido no âmbito desta tese. Esta API é baseada na especificação padronizada para o Java-TR. Este trabalho também discute o ambiente de execução para aplicações tempo real desenvolvido. Este ambiente faz uso da política de escalonamento tolerante a falhas denominada TAFT (Time-Aware Fault- Tolerant). O presente trabalho apresenta uma estratégia eficiente para a implementação dos conceitos presentes no escalonador TAFT, que garante o atendimento a todos os deadlines mesmo em situações de sobrecarga transiente. A estratégia elaborada combina algoritmos baseados no Earliest Deadline, sendo que um escalonador de dois níveis é utilizado para suportar o escalonamento combinado das entidades envolvidas. Adicionalmente, também se apresenta uma alternativa de validação dos requisitos temporais especificados. Esta alternativa sugere o uso de uma ferramenta que permite uma análise qualitativa dos dados a partir de informações obtidas através de monitoração da aplicação. Um estudo de caso baseado em uma aplicação real é usado para demonstrar o uso da metodologia proposta.

Designing single event upset mitigation techniques for large SRAM-Based FPGA components

This thesis presents the study and development of fault-tolerant techniques for programmable architectures, the well-known Field Programmable Gate Arrays (FPGAs), customizable by SRAM. FPGAs are becoming more valuable for space applications because of the high density, high performance, reduced development cost and re-programmability. In particular, SRAM-based FPGAs are very valuable for remote missions because of the possibility of being reprogrammed by the user as many times as necessary in a very short period. SRAM-based FPGA and micro-controllers represent a wide range of components in space applications, and as a result will be the focus of this work, more specifically the Virtex® family from Xilinx and the architecture of the 8051 micro-controller from Intel. The Triple Modular Redundancy (TMR) with voters is a common high-level technique to protect ASICs against single event upset (SEU) and it can also be applied to FPGAs. The TMR technique was first tested in the Virtex® FPGA architecture by using a small design based on counters. Faults were injected in all sensitive parts of the FPGA and a detailed analysis of the effect of a fault in a TMR design synthesized in the Virtex® platform was performed. Results from fault injection and from a radiation ground test facility showed the efficiency of the TMR for the related case study circuit. Although TMR has showed a high reliability, this technique presents some limitations, such as area overhead, three times more input and output pins and, consequently, a significant increase in power dissipation. Aiming to reduce TMR costs and improve reliability, an innovative high-level technique for designing fault-tolerant systems in SRAM-based FPGAs was developed, without modification in the FPGA architecture. This technique combines time and hardware redundancy to reduce overhead and to ensure reliability. It is based on duplication with comparison and concurrent error detection. The new technique proposed in this work was specifically developed for FPGAs to cope with transient faults in the user combinational and sequential logic, while also reducing pin count, area and power dissipation. The methodology was validated by fault injection experiments in an emulation board. The thesis presents comparison results in fault coverage, area and performance between the discussed techniques.

Eosi: um modelo para desenvolvimento de sistemas embarcados tolerantes a falhas

The semiconductor technologies evolutions leads devices to be developed with higher processing capability. Thus, those components have been used widely in more fields. Many industrial environment such as: oils, mines, automotives and hospitals are frequently using those devices on theirs process. Those industries activities are direct related to environment and health safe. So, it is quite important that those systems have extra safe features yield more reliability, safe and availability. The reference model eOSI that will be presented by this work is aimed to allow the development of systems under a new view perspective which can improve and make simpler the choice of strategies for fault tolerant. As a way to validate the model na architecture FPGA-based was developed.

Biomobile: sistema de identificação de usuários em dispositivos móveis na plataforma Android utilizando reconhecimento de faces a partir de vídeo

Pós-graduação em Ciência da Computação - IBILCE

Ensaios sobre computação e informação quânticas: fundamentação e simulações sobre o efeito da entropia

Pós-graduação em Ciência da Computação - IBILCE

Implementação de duas arquiteturas microcontroladas tolerantes a falhas para controle da temperatura

Pós-graduação em Física - IGCE

Hipercomplexos: um estudo da analicidade e da hiperperiodicidade de funções octoniônicas

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

Protecting the root SWAP operation from general and residual errors by continuous dynamical decoupling

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

Computational speed-up with a single qudit

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)