Signal Processing Techniques for Chipless UWB RFID Thermal Threshold Detector Detection.

This letter presents signal processing techniques to detect a passive thermal threshold detector based on a chipless time-domain ultrawideband (UWB) radio frequency identification (RFID) tag. The tag is composed by a UWB antenna connected to a transmission line, in turn loaded with a biomorphic thermal switch. The working principle consists of detecting the impedance change of the thermal switch. This change occurs when the temperature exceeds a threshold. A UWB radar is used as the reader. The difference between the actual time sample and a reference signal obtained from the averaging of previous samples is used to determine the switch transition and to mitigate the interferences derived from clutter reflections. A gain compensation function is applied to equalize the attenuation due to propagation loss. An improved method based on the continuous wavelet transform with Morlet wavelet is used to overcome detection problems associated to a low signal-to-noise ratio at the receiver. The average delay profile is used to detect the tag delay. Experimental measurements up to 5 m are obtained.

A Survey on FPGA-Based Sensor Systems: Towards Intelligent and Reconfigurable Low-Power Sensors for Computer Vision, Control and Signal Processing

The current trend in the evolution of sensor systems seeks ways to provide more accuracy and resolution, while at the same time decreasing the size and power consumption. The use of Field Programmable Gate Arrays (FPGAs) provides specific reprogrammable hardware technology that can be properly exploited to obtain a reconfigurable sensor system. This adaptation capability enables the implementation of complex applications using the partial reconfigurability at a very low-power consumption. For highly demanding tasks FPGAs have been favored due to the high efficiency provided by their architectural flexibility (parallelism, on-chip memory, etc.), reconfigurability and superb performance in the development of algorithms. FPGAs have improved the performance of sensor systems and have triggered a clear increase in their use in new fields of application. A new generation of smarter, reconfigurable and lower power consumption sensors is being developed in Spain based on FPGAs. In this paper, a review of these developments is presented, describing as well the FPGA technologies employed by the different research groups and providing an overview of future research within this field.

Waveform generator signal processing software. Final report.

National Highway Traffic Safety Administration, Office of Research and Development, Washington, D.C.

Seismic signal processing via the ILLIAC IV computer,

Bibliography: p. [12]

Quadrature-phase noise penalties of optically and electro-optically phase-locked lasers

Focussing particularly on solid-state laser systems, the phase-noise penalties of laser injection-locking and electro-optical phase-locking are derived using linearised quantum mechanical models. The fundamental performance limit (minimum achievable output phase noise) for an injection-locked laser (IJL) system at low frequencies is equal to that of a standard phase-insensitive amplifier, whereas, in principle, that of a phase-locked laser (PLL) system can be better. At high frequencies, the output phase noise of the IJL system is limited by that of the master laser, while that of the PLL system tends to a weighted sum of contributions from the master and slave laser fields. Under conditions of large amplification, particularly where there has been significant attenuation, the noise penalties are shown to be substantial. Nonideal photodetector characteristics are shown to add significantly to the noise penalties for the PLL system. (C) 2005 Elsevier B.V. All rights reserved.

Design of MIMO testbed with an FPGA board for fast signal processing

This paper describes the design of a Multiple Input Multiple Output testbed for assessing various MIMO transmission schemes in rich scattering indoor environments. In the undertaken design, a Field Programmable Gate Array (FPGA) board is used for fast processing of Intermediate Frequency signals. At the present stage, the testbed performance is assessed when the channel emulator between transmitter and receiver modules is introduced. Here, the results are presented for the case when a 2x2 Alamouti scheme for space time coding/decoding at transmitter and receiver is used. Various programming details of the FPGA board along with the obtained simulation results are reported

Design Strategies and Modelling of Low-Power Sigma-Delta Analog-to-Digital Converters

Oggi, i dispositivi portatili sono diventati la forza trainante del mercato consumer e nuove sfide stanno emergendo per aumentarne le prestazioni, pur mantenendo un ragionevole tempo di vita della batteria. Il dominio digitale è la miglior soluzione per realizzare funzioni di elaborazione del segnale, grazie alla scalabilità della tecnologia CMOS, che spinge verso l'integrazione a livello sub-micrometrico. Infatti, la riduzione della tensione di alimentazione introduce limitazioni severe per raggiungere un range dinamico accettabile nel dominio analogico. Minori costi, minore consumo di potenza, maggiore resa e una maggiore riconfigurabilità sono i principali vantaggi dell'elaborazione dei segnali nel dominio digitale. Da più di un decennio, diverse funzioni puramente analogiche sono state spostate nel dominio digitale. Ciò significa che i convertitori analogico-digitali (ADC) stanno diventando i componenti chiave in molti sistemi elettronici. Essi sono, infatti, il ponte tra il mondo digitale e analogico e, di conseguenza, la loro efficienza e la precisione spesso determinano le prestazioni globali del sistema. I convertitori Sigma-Delta sono il blocco chiave come interfaccia in circuiti a segnale-misto ad elevata risoluzione e basso consumo di potenza. I tools di modellazione e simulazione sono strumenti efficaci ed essenziali nel flusso di progettazione. Sebbene le simulazioni a livello transistor danno risultati più precisi ed accurati, questo metodo è estremamente lungo a causa della natura a sovracampionamento di questo tipo di convertitore. Per questo motivo i modelli comportamentali di alto livello del modulatore sono essenziali per il progettista per realizzare simulazioni veloci che consentono di identificare le specifiche necessarie al convertitore per ottenere le prestazioni richieste. Obiettivo di questa tesi è la modellazione del comportamento del modulatore Sigma-Delta, tenendo conto di diverse non idealità come le dinamiche dell'integratore e il suo rumore termico. Risultati di simulazioni a livello transistor e dati sperimentali dimostrano che il modello proposto è preciso ed accurato rispetto alle simulazioni comportamentali.

Adaptive Signal Processing for Power Line Communications

This thesis represents a significant part of the research activity conducted during the PhD program in Information Technologies, supported by Selta S.p.A, Cadeo, Italy, focused on the analysis and design of a Power Line Communications (PLC) system. In recent times the PLC technologies have been considered for integration in Smart Grids architectures, as they are used to exploit the existing power line infrastructure for information transmission purposes on low, medium and high voltage lines. The characterization of a reliable PLC system is a current object of research as well as it is the design of modems for communications over the power lines. In this thesis, the focus is on the analysis of a full-duplex PLC modem for communication over high-voltage lines, and, in particular, on the design of the echo canceller device and innovative channel coding schemes.

Simultaneous demultiplexing, data regeneration, and clock recovery with a single semiconductor optical amplifier-based nonlinear-optical loop mirror

We demonstrate simultaneous demultiplexing, data regeneration and clock recovery at 10Gbits/s, using a single semiconductor optical amplifier–based nonlinear-optical loop mirror in a phase-locked loop configuration.

Simultaneous clock recovery and data regeneration using a nonlinear optical loop mirror as an all-optical mixer

High-speed optical clock recovery, demultiplexing and data regeneration will be integral parts of any future photonic network based on high bit-rate OTDM. Much research has been conducted on devices that perform these functions, however to date each process has been demonstrated independently. A very promising method of all-optical switching is that of a semiconductor optical amplifier-based nonlinear optical loop mirror (SOA-NOLM). This has various advantages compared with the standard fiber NOLM, most notably low switching power, compact size and stability. We use the SOA-NOLM as an all-optical mixer in a classical phase-locked loop arrangement to achieve optical clock recovery, while at the same time achieving data regeneration in a single compact device