Optimization of breast tomosynthesis image reconstruction using parallel computing

Breast cancer is the most common cancer among women, being a major public health problem. Worldwide, X-ray mammography is the current gold-standard for medical imaging of breast cancer. However, it has associated some well-known limitations. The false-negative rates, up to 66% in symptomatic women, and the false-positive rates, up to 60%, are a continued source of concern and debate. These drawbacks prompt the development of other imaging techniques for breast cancer detection, in which Digital Breast Tomosynthesis (DBT) is included. DBT is a 3D radiographic technique that reduces the obscuring effect of tissue overlap and appears to address both issues of false-negative and false-positive rates. The 3D images in DBT are only achieved through image reconstruction methods. These methods play an important role in a clinical setting since there is a need to implement a reconstruction process that is both accurate and fast. This dissertation deals with the optimization of iterative algorithms, with parallel computing through an implementation on Graphics Processing Units (GPUs) to make the 3D reconstruction faster using Compute Unified Device Architecture (CUDA). Iterative algorithms have shown to produce the highest quality DBT images, but since they are computationally intensive, their clinical use is currently rejected. These algorithms have the potential to reduce patient dose in DBT scans. A method of integrating CUDA in Interactive Data Language (IDL) is proposed in order to accelerate the DBT image reconstructions. This method has never been attempted before for DBT. In this work the system matrix calculation, the most computationally expensive part of iterative algorithms, is accelerated. A speedup of 1.6 is achieved proving the fact that GPUs can accelerate the IDL implementation.

Incremental compilation and deployment for OutSystems Platform

OutSystems Platform is used to develop, deploy, and maintain enterprise web an mobile web applications. Applications are developed through a visual domain specific language, in an integrated development environment, and compiled to a standard stack of web technologies. In the platform’s core, there is a compiler and a deployment service that transform the visual model into a running web application. As applications grow, compilation and deployment times increase as well, impacting the developer’s productivity. In the previous model, a full application was the only compilation and deployment unit. When the developer published an application, even if he only changed a very small aspect of it, the application would be fully compiled and deployed. Our goal is to reduce compilation and deployment times for the most common use case, in which the developer performs small changes to an application before compiling and deploying it. We modified the OutSystems Platform to support a new incremental compilation and deployment model that reuses previous computations as much as possible in order to improve performance. In our approach, the full application is broken down into smaller compilation and deployment units, increasing what can be cached and reused. We also observed that this finer model would benefit from a parallel execution model. Hereby, we created a task driven Scheduler that executes compilation and deployment tasks in parallel. Our benchmarks show a substantial improvement of the compilation and deployment process times for the aforementioned development scenario.

A public transport bus assignment problem: parallel metaheuristics assessment

Combinatorial Optimization Problems occur in a wide variety of contexts and generally are NP-hard problems. At a corporate level solving this problems is of great importance since they contribute to the optimization of operational costs. In this thesis we propose to solve the Public Transport Bus Assignment problem considering an heterogeneous fleet and line exchanges, a variant of the Multi-Depot Vehicle Scheduling Problem in which additional constraints are enforced to model a real life scenario. The number of constraints involved and the large number of variables makes impracticable solving to optimality using complete search techniques. Therefore, we explore metaheuristics, that sacrifice optimality to produce solutions in feasible time. More concretely, we focus on the development of algorithms based on a sophisticated metaheuristic, Ant-Colony Optimization (ACO), which is based on a stochastic learning mechanism. For complex problems with a considerable number of constraints, sophisticated metaheuristics may fail to produce quality solutions in a reasonable amount of time. Thus, we developed parallel shared-memory (SM) synchronous ACO algorithms, however, synchronism originates the straggler problem. Therefore, we proposed three SM asynchronous algorithms that break the original algorithm semantics and differ on the degree of concurrency allowed while manipulating the learned information. Our results show that our sequential ACO algorithms produced better solutions than a Restarts metaheuristic, the ACO algorithms were able to learn and better solutions were achieved by increasing the amount of cooperation (number of search agents). Regarding parallel algorithms, our asynchronous ACO algorithms outperformed synchronous ones in terms of speedup and solution quality, achieving speedups of 17.6x. The cooperation scheme imposed by asynchronism also achieved a better learning rate than the original one.

Estudo de viabilidade de paralelização de códigos de análise de dados em PROOF

Dissertação de mestrado em Engenharia Informática

Parallel improved Schnorr-Euchner enumeration SE++ for the CVP and SVP

The Closest Vector Problem (CVP) and the Shortest Vector Problem (SVP) are prime problems in lattice-based cryptanalysis, since they underpin the security of many lattice-based cryptosystems. Despite the importance of these problems, there are only a few CVP-solvers publicly available, and their scalability was never studied. This paper presents a scalable implementation of an enumeration-based CVP-solver for multi-cores, which can be easily adapted to solve the SVP. In particular, it achieves super-linear speedups in some instances on up to 8 cores and almost linear speedups on 16 cores when solving the CVP on a 50-dimensional lattice. Our results show that enumeration-based CVP-solvers can be parallelized as effectively as enumeration-based solvers for the SVP, based on a comparison with a state of the art SVP-solver. In addition, we show that we can optimize the SVP variant of our solver in such a way that it becomes 35%-60% faster than the fastest enumeration-based SVP-solver to date.

Desenvolvimento de um laboratório pedagógico de vias de comunicação na Universidade do Minho

Dissertação de mestrado integrado em Engenharia Civil

Cognitive processes affect the gait of subjects with Parkinson’s and Alzheimer’s disease in dual tasks

Objective To investigate the relation between gait parameters and cognitive impairments in subjects with Parkinson’s disease (PD) and Alzheimer’s disease (AD) during the performance of dual tasks. Methods This was a cross-sectional study involving 126 subjects divided into three groups: Parkinson group (n = 43), Alzheimer group (n = 38), and control group (n = 45). The subjects were evaluated using the Timed Up and Go test administered with motor and cognitive distracters. Gait analyses consisted of cadence and speed measurements, with cognitive functions being assessed by the Brief Cognitive Screening Battery and the Clock Drawing Test. Statistical procedures included mixed-design analyses of variance to observe the gait patterns between groups and tasks and the linear regression model to investigate the influence of cognitive functions in this process. A 5% significant level was adopted. Results Regarding the subjects’ speed, the data show a significant difference between group vs task interaction (p = 0.009), with worse performance of subjects with PD in motor dual task and of subjects with AD in cognitive dual task. With respect to cadence, no statistical differences was seen between group vs task interaction (p = 0.105), showing low interference of the clinical conditions on such parameter. The linear regression model showed that up to 45.79%, of the variance in gait can be explained by the interference of cognitive processes. Conclusion Dual task activities affect gait pattern in subjects with PD and AD. Differences between groups reflect peculiarities of each disease and show a direct interference of cognitive processes on complex tasks.

An evolutionary approach to the use of Petri net based models: from parallel controllers to HW/SW co-design

"A workshop within the 19th International Conference on Applications and Theory of Petri Nets - ICATPN’1998"

An illustrated flora of the northern United States, Canada and the British possessions : from Newfoundland to the parallel of the southern boundary of Virginia, and from the Atlantic Ocean westward to the 102d meridian / by Nathaniel Lord Britton and Hon. Addison Brown.

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An illustrated flora of the northern United States, Canada and the British possessions : from Newfoundland to the parallel of the southern boundary of Virginia, and from the Atlantic Ocean westward to the 102d meridian / by Nathaniel Lord Britton and Hon. Addison Brown.

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An illustrated flora of the northern United States, Canada and the British possessions : from Newfoundland to the parallel of the southern boundary of Virginia, and from the Atlantic Ocean westward to the 102d meridian / by Nathaniel Lord Britton and Hon. Addison Brown.

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Direct numerical simulation of turbulent flames on parallel computers

Magdeburg, Univ., Fak. für Verfahrens- und Systemtechnik, Diss., 2012

Simulation of lime calcination in normal shaft an parallel flow regenerative kilns

Magdeburg, Univ., Fak. für Verfahrens- und Systemtechnik, Diss., 2012

Parallel Architecture Prototype for 60 GHz High Data Rate Wireless Single Carrier Receiver

Nowadays a huge attention of the academia and research teams is attracted to the potential of the usage of the 60 GHz frequency band in the wireless communications. The use of the 60GHz frequency band offers great possibilities for wide variety of applications that are yet to be implemented. These applications also imply huge implementation challenges. Such example is building a high data rate transceiver which at the same time would have very low power consumption. In this paper we present a prototype of Single Carrier -SC transceiver system, illustrating a brief overview of the baseband design, emphasizing the most important decisions that need to be done. A brief overview of the possible approaches when implementing the equalizer, as the most complex module in the SC transceiver, is also presented. The main focus of this paper is to suggest a parallel architecture for the receiver in a Single Carrier communication system. This would provide higher data rates that the communication system canachieve, for a price of higher power consumption. The suggested architecture of such receiver is illustrated in this paper,giving the results of its implementation in comparison with its corresponding serial implementation.

Efficiency of parallel transmission methods at 7T magnetic resonance

Magdeburg, Univ., Fak. für Naturwiss., Diss., 2014