Simulação em tempo real de sistemas de distribuição de energia elétrica utilizando-se estruturas com descrição de hardware em software

Pós-graduação em Engenharia Elétrica - FEIS

A low-power silicon-on-insulator PWM discriminator for biomedical applications

A CMOS/SOI circuit to decode PWM signals is presented as part of a body-implanted neurostimulator for visual prosthesis. Since encoded data is the sole input to the circuit, the decoding technique is based on a double-integration concept and does not require dc filtering. Nonoverlapping control phases are internally derived from the incoming pulses and a fast-settling comparator ensures good discrimination accuracy in the megahertz range. The circuit was integrated on a 2 mu m single-metal SOI fabrication process and has an effective area of 2mm(2) Typically, the measured resolution of encoding parameter a was better than 10% at 6MHz and V-DD=3.3V. Stand-by consumption is around 340 mu W. Pulses with frequencies up to 15MHz and alpha = 10% can be discriminated for V-DD spanning from 2.3V to 3.3V. Such an excellent immunity to V-DD deviations meets a design specification with respect to inherent coupling losses on transmitting data and power by means of a transcutaneous link.

Study of silicon-on-insulator multiple-gate MOS structures including band-gap engineering and self heating effects

The progresses of electron devices integration have proceeded for more than 40 years following the well–known Moore’s law, which states that the transistors density on chip doubles every 24 months. This trend has been possible due to the downsizing of the MOSFET dimensions (scaling); however, new issues and new challenges are arising, and the conventional ”bulk” architecture is becoming inadequate in order to face them. In order to overcome the limitations related to conventional structures, the researchers community is preparing different solutions, that need to be assessed. Possible solutions currently under scrutiny are represented by: • devices incorporating materials with properties different from those of silicon, for the channel and the source/drain regions; • new architectures as Silicon–On–Insulator (SOI) transistors: the body thickness of Ultra-Thin-Body SOI devices is a new design parameter, and it permits to keep under control Short–Channel–Effects without adopting high doping level in the channel. Among the solutions proposed in order to overcome the difficulties related to scaling, we can highlight heterojunctions at the channel edge, obtained by adopting for the source/drain regions materials with band–gap different from that of the channel material. This solution allows to increase the injection velocity of the particles travelling from the source into the channel, and therefore increase the performance of the transistor in terms of provided drain current. The first part of this thesis work addresses the use of heterojunctions in SOI transistors: chapter 3 outlines the basics of the heterojunctions theory and the adoption of such approach in older technologies as the heterojunction–bipolar–transistors; moreover the modifications introduced in the Monte Carlo code in order to simulate conduction band discontinuities are described, and the simulations performed on unidimensional simplified structures in order to validate them as well. Chapter 4 presents the results obtained from the Monte Carlo simulations performed on double–gate SOI transistors featuring conduction band offsets between the source and drain regions and the channel. In particular, attention has been focused on the drain current and to internal quantities as inversion charge, potential energy and carrier velocities. Both graded and abrupt discontinuities have been considered. The scaling of devices dimensions and the adoption of innovative architectures have consequences on the power dissipation as well. In SOI technologies the channel is thermally insulated from the underlying substrate by a SiO2 buried–oxide layer; this SiO2 layer features a thermal conductivity that is two orders of magnitude lower than the silicon one, and it impedes the dissipation of the heat generated in the active region. Moreover, the thermal conductivity of thin semiconductor films is much lower than that of silicon bulk, due to phonon confinement and boundary scattering. All these aspects cause severe self–heating effects, that detrimentally impact the carrier mobility and therefore the saturation drive current for high–performance transistors; as a consequence, thermal device design is becoming a fundamental part of integrated circuit engineering. The second part of this thesis discusses the problem of self–heating in SOI transistors. Chapter 5 describes the causes of heat generation and dissipation in SOI devices, and it provides a brief overview on the methods that have been proposed in order to model these phenomena. In order to understand how this problem impacts the performance of different SOI architectures, three–dimensional electro–thermal simulations have been applied to the analysis of SHE in planar single and double–gate SOI transistors as well as FinFET, featuring the same isothermal electrical characteristics. In chapter 6 the same simulation approach is extensively employed to study the impact of SHE on the performance of a FinFET representative of the high–performance transistor of the 45 nm technology node. Its effects on the ON–current, the maximum temperatures reached inside the device and the thermal resistance associated to the device itself, as well as the dependence of SHE on the main geometrical parameters have been analyzed. Furthermore, the consequences on self–heating of technological solutions such as raised S/D extensions regions or reduction of fin height are explored as well. Finally, conclusions are drawn in chapter 7.

Applications of High Speed Configurable Logic Devices in Modern Particle Physics Experiments

Several activities were conducted during my PhD activity. For the NEMO experiment a collaboration between the INFN/University groups of Catania and Bologna led to the development and production of a mixed signal acquisition board for the Nemo Km3 telescope. The research concerned the feasibility study for a different acquisition technique quite far from that adopted in the NEMO Phase 1 telescope. The DAQ board that we realized exploits the LIRA06 front-end chip for the analog acquisition of anodic an dynodic sources of a PMT (Photo-Multiplier Tube). The low-power analog acquisition allows to sample contemporaneously multiple channels of the PMT at different gain factors in order to increase the signal response linearity over a wider dynamic range. Also the auto triggering and self-event-classification features help to improve the acquisition performance and the knowledge on the neutrino event. A fully functional interface towards the first level data concentrator, the Floor Control Module, has been integrated as well on the board, and a specific firmware has been realized to comply with the present communication protocols. This stage of the project foresees the use of an FPGA, a high speed configurable device, to provide the board with a flexible digital logic control core. After the validation of the whole front-end architecture this feature would be probably integrated in a common mixed-signal ASIC (Application Specific Integrated Circuit). The volatile nature of the configuration memory of the FPGA implied the integration of a flash ISP (In System Programming) memory and a smart architecture for a safe remote reconfiguration of it. All the integrated features of the board have been tested. At the Catania laboratory the behavior of the LIRA chip has been investigated in the digital environment of the DAQ board and we succeeded in driving the acquisition with the FPGA. The PMT pulses generated with an arbitrary waveform generator were correctly triggered and acquired by the analog chip, and successively they were digitized by the on board ADC under the supervision of the FPGA. For the communication towards the data concentrator a test bench has been realized in Bologna where, thanks to a lending of the Roma University and INFN, a full readout chain equivalent to that present in the NEMO phase-1 was installed. These tests showed a good behavior of the digital electronic that was able to receive and to execute command imparted by the PC console and to answer back with a reply. The remotely configurable logic behaved well too and demonstrated, at least in principle, the validity of this technique. A new prototype board is now under development at the Catania laboratory as an evolution of the one described above. This board is going to be deployed within the NEMO Phase-2 tower in one of its floors dedicated to new front-end proposals. This board will integrate a new analog acquisition chip called SAS (Smart Auto-triggering Sampler) introducing thus a new analog front-end but inheriting most of the digital logic present in the current DAQ board discussed in this thesis. For what concern the activity on high-resolution vertex detectors, I worked within the SLIM5 collaboration for the characterization of a MAPS (Monolithic Active Pixel Sensor) device called APSEL-4D. The mentioned chip is a matrix of 4096 active pixel sensors with deep N-well implantations meant for charge collection and to shield the analog electronics from digital noise. The chip integrates the full-custom sensors matrix and the sparsifification/readout logic realized with standard-cells in STM CMOS technology 130 nm. For the chip characterization a test-beam has been set up on the 12 GeV PS (Proton Synchrotron) line facility at CERN of Geneva (CH). The collaboration prepared a silicon strip telescope and a DAQ system (hardware and software) for data acquisition and control of the telescope that allowed to store about 90 million events in 7 equivalent days of live-time of the beam. My activities concerned basically the realization of a firmware interface towards and from the MAPS chip in order to integrate it on the general DAQ system. Thereafter I worked on the DAQ software to implement on it a proper Slow Control interface of the APSEL4D. Several APSEL4D chips with different thinning have been tested during the test beam. Those with 100 and 300 um presented an overall efficiency of about 90% imparting a threshold of 450 electrons. The test-beam allowed to estimate also the resolution of the pixel sensor providing good results consistent with the pitch/sqrt(12) formula. The MAPS intrinsic resolution has been extracted from the width of the residual plot taking into account the multiple scattering effect.

Analog Signal Acquisition and Conditioning for Near-Field Capacitive Communication and Active Combined EEG-EIT Monitoring

The work of the present thesis is focused on the implementation of microelectronic voltage sensing devices, with the purpose of transmitting and extracting analog information between devices of different nature at short distances or upon contact. Initally, chip-to-chip communication has been studied, and circuitry for 3D capacitive coupling has been implemented. Such circuits allow the communication between dies fabricated in different technologies. Due to their novelty, they are not standardized and currently not supported by standard CAD tools. In order to overcome such burden, a novel approach for the characterization of such communicating links has been proposed. This results in shorter design times and increased accuracy. Communication between an integrated circuit (IC) and a probe card has been extensively studied as well. Today wafer probing is a costly test procedure with many drawbacks, which could be overcome by a different communication approach such as capacitive coupling. For this reason wireless wafer probing has been investigated as an alternative approach to standard on-contact wafer probing. Interfaces between integrated circuits and biological systems have also been investigated. Active electrodes for simultaneous electroencephalography (EEG) and electrical impedance tomography (EIT) have been implemented for the first time in a 0.35 um process. Number of wires has been minimized by sharing the analog outputs and supply on a single wire, thus implementing electrodes that require only 4 wires for their operation. Minimization of wires reduces the cable weight and thus limits the patient's discomfort. The physical channel for communication between an IC and a biological medium is represented by the electrode itself. As this is a very crucial point for biopotential acquisitions, large efforts have been carried in order to investigate the different electrode technologies and geometries and an electromagnetic model is presented in order to characterize the properties of the electrode to skin interface.

Cooperative Wireless Systems

This Ph.D. dissertation reports on the work performed at the Wireless Communication Laboratory - University of Bologna and National Research Council - as well as, for six months, at the Fraunhofer Institute for Integrated Circuit (IIS) in Nürnberg. The work of this thesis is in the area of wireless communications, especially with regards to cooperative communications aspects in narrow-band and ultra-wideband systems, cooperative links characterization, network geometry, power allocation techniques,and synchronization between nodes. The underpinning of this work is devoted to developing a general framework for design and analysis of wireless cooperative communication systems, which depends on propagation environment, transmission technique, diversity method, power allocation for various scenarios and relay positions. The optimal power allocation for minimizing the bit error probability at the destination is derived. In addition, a syncronization algorithm for master-slave communications is proposed with the aim of jointly compensate the clock drift and offset of wireless nodes composing the network.

Development of an X-ray spectrometric system and feasibility tests of Silicon Drift Detector for medical and space applications

The thesis work concerns X-ray spectrometry for both medical and space applications and is divided into two sections. The first section addresses an X-ray spectrometric system designed to study radiological beams and is devoted to the optimization of diagnostic procedures in medicine. A parametric semi-empirical model capable of efficiently reconstructing diagnostic X-ray spectra in 'middle power' computers was developed and tested. In addition, different silicon diode detectors were tested as real-time detectors in order to provide a real-time evaluation of the spectrum during diagnostic procedures. This project contributes to the field by presenting an improved simulation of a realistic X-ray beam emerging from a common X-ray tube with a complete and detailed spectrum that lends itself to further studies of added filtration, thus providing an optimized beam for different diagnostic applications in medicine. The second section describes the preliminary tests that have been carried out on the first version of an Application Specific Integrated Circuit (ASIC), integrated with large area position-sensitive Silicon Drift Detector (SDD) to be used on board future space missions. This technology has been developed for the ESA project: LOFT (Large Observatory for X-ray Timing), a new medium-class space mission that the European Space Agency has been assessing since February of 2011. The LOFT project was proposed as part of the Cosmic Vision Program (2015-2025).

Design and implementation of a 3D computer game controller using inertial MEMS sensors

Though 3D computer graphics has seen tremendous advancement in the past two decades, most available mechanisms for computer interaction in 3D are high cost and targeted for industry and virtual reality applications. Recent advances in Micro-Electro-Mechanical-System (MEMS) devices have brought forth a variety of new low-cost, low-power, miniature sensors with high accuracy, which are well suited for hand-held devices. In this work a novel design for a 3D computer game controller using inertial sensors is proposed, and a prototype device based on this design is implemented. The design incorporates MEMS accelerometers and gyroscopes from Analog Devices to measure the three components of the acceleration and angular velocity. From these sensor readings, the position and orientation of the hand-held compartment can be calculated using numerical methods. The implemented prototype is utilizes a USB 2.0 compliant interface for power and communication with the host system. A Microchip dsPIC microcontroller is used in the design. This microcontroller integrates the analog to digital converters, the program memory flash, as well as the core processor, on a single integrated circuit. A PC running Microsoft Windows operating system is used as the host machine. Prototype firmware for the microcontroller is developed and tested to establish the communication between the design and the host, and perform the data acquisition and initial filtering of the sensor data. A PC front-end application with a graphical interface is developed to communicate with the device, and allow real-time visualization of the acquired data.

Experimental investigation of regular fluids and nanofluids during flow boiling in a single microchannel at different heat fluxes and mass fluxes

The dissipation of high heat flux from integrated circuit chips and the maintenance of acceptable junction temperatures in high powered electronics require advanced cooling technologies. One such technology is two-phase cooling in microchannels under confined flow boiling conditions. In macroscale flow boiling bubbles will nucleate on the channel walls, grow, and depart from the surface. In microscale flow boiling bubbles can fill the channel diameter before the liquid drag force has a chance to sweep them off the channel wall. As a confined bubble elongates in a microchannel, it traps thin liquid films between the heated wall and the vapor core that are subject to large temperature gradients. The thin films evaporate rapidly, sometimes faster than the incoming mass flux can replenish bulk fluid in the microchannel. When the local vapor pressure spike exceeds the inlet pressure, it forces the upstream interface to travel back into the inlet plenum and create flow boiling instabilities. Flow boiling instabilities reduce the temperature at which critical heat flux occurs and create channel dryout. Dryout causes high surface temperatures that can destroy the electronic circuits that use two-phase micro heat exchangers for cooling. Flow boiling instability is characterized by periodic oscillation of flow regimes which induce oscillations in fluid temperature, wall temperatures, pressure drop, and mass flux. When nanofluids are used in flow boiling, the nanoparticles become deposited on the heated surface and change its thermal conductivity, roughness, capillarity, wettability, and nucleation site density. It also affects heat transfer by changing bubble departure diameter, bubble departure frequency, and the evaporation of the micro and macrolayer beneath the growing bubbles. Flow boiling was investigated in this study using degassed, deionized water, and 0.001 vol% aluminum oxide nanofluids in a single rectangular brass microchannel with a hydraulic diameter of 229 µm for one inlet fluid temperature of 63°C and two constant flow rates of 0.41 ml/min and 0.82 ml/min. The power input was adjusted for two average surface temperatures of 103°C and 119°C at each flow rate. High speed images were taken periodically for water and nanofluid flow boiling after durations of 25, 75, and 125 minutes from the start of flow. The change in regime timing revealed the effect of nanoparticle suspension and deposition on the Onset of Nucelate Boiling (ONB) and the Onset of Bubble Elongation (OBE). Cycle duration and bubble frequencies are reported for different nanofluid flow boiling durations. The addition of nanoparticles was found to stabilize bubble nucleation and growth and limit the recession rate of the upstream and downstream interfaces, mitigating the spreading of dry spots and elongating the thin film regions to increase thin film evaporation.

Lung Nodule Detection by Microdose CT Versus Chest Radiography (Standard and Dual-Energy Subtracted).

OBJECTIVE The purpose of this study was to investigate the feasibility of microdose CT using a comparable dose as for conventional chest radiographs in two planes including dual-energy subtraction for lung nodule assessment. MATERIALS AND METHODS We investigated 65 chest phantoms with 141 lung nodules, using an anthropomorphic chest phantom with artificial lung nodules. Microdose CT parameters were 80 kV and 6 mAs, with pitch of 2.2. Iterative reconstruction algorithms and an integrated circuit detector system (Stellar, Siemens Healthcare) were applied for maximum dose reduction. Maximum intensity projections (MIPs) were reconstructed. Chest radiographs were acquired in two projections with bone suppression. Four blinded radiologists interpreted the images in random order. RESULTS A soft-tissue CT kernel (I30f) delivered better sensitivities in a pilot study than a hard kernel (I70f), with respective mean (SD) sensitivities of 91.1% ± 2.2% versus 85.6% ± 5.6% (p = 0.041). Nodule size was measured accurately for all kernels. Mean clustered nodule sensitivity with chest radiography was 45.7% ± 8.1% (with bone suppression, 46.1% ± 8%; p = 0.94); for microdose CT, nodule sensitivity was 83.6% ± 9% without MIP (with additional MIP, 92.5% ± 6%; p < 10(-3)). Individual sensitivities of microdose CT for readers 1, 2, 3, and 4 were 84.3%, 90.7%, 68.6%, and 45.0%, respectively. Sensitivities with chest radiography for readers 1, 2, 3, and 4 were 42.9%, 58.6%, 36.4%, and 90.7%, respectively. In the per-phantom analysis, respective sensitivities of microdose CT versus chest radiography were 96.2% and 75% (p < 10(-6)). The effective dose for chest radiography including dual-energy subtraction was 0.242 mSv; for microdose CT, the applied dose was 0.1323 mSv. CONCLUSION Microdose CT is better than the combination of chest radiography and dual-energy subtraction for the detection of solid nodules between 5 and 12 mm at a lower dose level of 0.13 mSv. Soft-tissue kernels allow better sensitivities. These preliminary results indicate that microdose CT has the potential to replace conventional chest radiography for lung nodule detection.

Self-reference Scrubber for TMR Systems Based on Xilinx Virtex FPGAs

SRAM-based FPGAs are sensitive to radiation effects. Soft errors can appear and accumulate, potentially defeating mitigation strategies deployed at the Application Layer. Therefore, Configuration Memory scrubbing is required to improve radiation tolerance of such FPGAs in space applications. Virtex FPGAs allow runtime scrubbing by means of dynamic partial reconfiguration. Even with scrubbing, intra-FPGA TMR systems are subjected to common-mode errors affecting more than one design domain. This is solved in inter-FPGA TMR systems at the expense of a higher cost, power and mass. In this context, a self-reference scrubber for device-level TMR system based on Xilinx Virtex FPGAs is presented. This scrubber allows for a fast SEU/MBU detection and correction by peer frame comparison without needing to access a golden configuration memory

TCAD for PV: a fast method for accurately modelling metal impurity evolution during solar cell processing

Coupled device and process silumation tools, collectively known as technology computer-aided design (TCAD), have been used in the integrated circuit industry for over 30 years. These tools allow researchers to quickly converge on optimized devide designs and manufacturing processes with minimal experimental expenditures. The PV industry has been slower to adopt these tools, but is quickly developing competency in using them. This paper introduces a predictive defect engineering paradigm and simulation tool, while demonstrating its effectiveness at increasing the performance and throughput of current industrial processes. the impurity-to-efficiency (I2E) simulator is a coupled process and device simulation tool that links wafer material purity, processing parameters and cell desigh to device performance. The tool has been validated with experimental data and used successfully with partners in industry. The simulator has also been deployed in a free web-accessible applet, which is available for use by the industrial and academic communities.

Co-creación de semiconductores

El mercado de los semiconductores está saturado de productos similares y de distribuidores con una propuesta de servicios similar. Los procesos de Co-Creación en los que el cliente colabora en la definición y desarrollo del producto y proporciona información sobre su utilidad, prestaciones y valor percibido, con el resultado de un producto que soluciona sus necesidades reales, se están convirtiendo en un paso adelante en la diferenciación y expansión de la cadena de valor. El proceso de diseño y fabricación de semiconductores es bastante complejo, requiere inversiones cada vez mayores y demanda soluciones completas. Se requiere un ecosistema que soporte el desarrollo de los equipos electrónicos basados en dichos semiconductores. La facilidad para el diálogo y compartir información que proporciona internet, las herramientas basadas en web 2.0 y los servicios y aplicaciones en la nube; favorecen la generación de ideas, el desarrollo y evaluación de productos y posibilita la interacción entre diversos co-creadores. Para iniciar un proceso de co-creación se requiere métodos y herramientas adecuados para interactuar con los participantes e intercambiar experiencias, procesos para integrar la co-creación dentro de la operativa de la empresa, y desarrollar una organización y cultura que soporten y fomenten dicho proceso. Entre los métodos más efectivos están la Netnografía que estudia las conversaciones de las comunidades en internet; colaboración con usuarios pioneros que van por delante del Mercado y esperan un gran beneficio de la satisfacción de sus necesidades o deseos; los estudios de innovación que permiten al usuario definir y a menudo crear su propia solución y la externalización a la multitud, que mediante una convocatoria abierta plantea a la comunidad retos a resolver a cambio de algún tipo de recompensa. La especialización de empresas subcontratistas en el desarrollo y fabricación de semiconductores; facilita la innovación abierta colaborando con diversas entidades en las diversas fases del desarrollo del semiconductor y su ecosistema. La co-creación se emplea actualmente en el sector de los semiconductores para detectar ideas de diseños y aplicaciones, a menudo mediante concursos de innovación. El servicio de soporte técnico y la evaluación de los semiconductores con frecuencia es fruto de la colaboración entre los miembros de la comunidad fomentada y soportada por los fabricantes del producto. Con el programa EBVchips se posibilita el acceso a empresas pequeñas y medianas a la co-creación de semiconductores con los fabricantes en un proceso coordinado y patrocinado por el distribuidor EBV. Los semiconductores configurables como las FPGAs constituyen otro ejemplo de co-creación mediante el cual el fabricante proporciona el circuito integrado y el entorno de desarrollo y los clientes crean el producto final definiendo sus características y funcionalidades. Este proceso se enriquece con bloques funcionales de diseño, IP-cores, que a menudo son creados por la comunidad de usuarios. ABSTRACT. The semiconductor market is saturated of similar products and distributors with a similar proposal for services. The processes of co-creation in which the customer collaborates in the definition and development of the product and provides information about its utility, performance and perceived value, resulting in a product that solves their real needs, are becoming a step forward in the differentiation and expansion of the value chain. The design and semiconductor manufacturing process is quite complex, requires increasingly higher investments and demands complete solutions. It requires an ecosystem that supports the development of electronic equipments based on such semiconductors. The ease of dialogue and sharing information that provides internet, web 2.0-based tools and services and applications in the cloud; favor the generation of ideas, the development and evaluation of products and allows the interaction between various co-creators. To start a process of co-creation adequate methods and tools are required to interact with the participants and exchange experiences, processes to integrate the co-creation within the operations of the company, and developing an organization and culture that support and promote such process. Among the most effective methods are the Netnography that studies the conversations of the communities on the internet; collaboration with Lead Users who are ahead of the market and expect a great benefit from the satisfaction of their needs or desires; Innovation studies that allow the user to define and often create their own solution and Crowdsourcing, an open call to the community to solve challenges in exchange for some kind of reward. The specialization of subcontractors in the development and manufacture of semiconductors; facilitates open innovation in the context of collaboration with different entities working in the different phases of the development of the semiconductor and its ecosystem. Co-creation is used currently in the semiconductor sector to detect ideas of designs and applications, often through innovation’s contests. Technical support and evaluation of semiconductors frequently is the result of collaboration between members of the community fostered and supported by the manufacturers of the product. The EBVchips program provides access to small and medium-sized companies to the co-creation of semiconductors with manufacturers in a process coordinated and sponsored by the Distributor EBV. Configurable semiconductors like FPGAs are another example of co-creation whereby the manufacturer provides the integrated circuit and the development environment and customers create the final product by defining their features and functionality. This process is enriched with IP-cores, designs blocks that are often created by the user community.

Entorno histórico y social de la aparición del microchip

El siguiente proyecto es un desarrollo histórico-científico acerca de la notoria importancia que supuso la aparición del microchip o circuito integrado1. El desarrollo de este trabajo ha sido una investigación bibliográfica en contenidos webs, enciclopedias y libros. El trabajo contiene un estudio sobre los transistores que fue el componente que dio paso al circuito integrado además de ser uno de los mayores inventos del siglo XX, además, se propone una pequeña inmersión a la época histórica del momento de la aparición del transistor. Al igual que con el transistor, se hace un estudio acerca del circuito integrado, pero en este caso siendo más extenso ya que es el objeto de estudio de este PFC. Para este componente sí que podemos encontrar una explicación más exhaustiva acerca de su fabricación, materiales. Además también podemos encontrar el momento históricosocial de la época bajo estudio. Para finalizar con el proyecto, se hace un breve repaso de los ejemplos de aplicación del circuito integrado y así poder hacer hincapié de la revolución tecnológica que supuso el descubrimiento del microchip. ABSTRACT. The following work is a historical and scientific development regarding the fundamental importance the emergence of the microchip. The development of this work has consisted of a bibliographic research of web contents, encyclopedias and books. The paper contains a study about the transistors, component that propitiated the integrated circuit and was one of the most important inventions of the XXth century. Also is proposed a short historical immersion in the time that preceded the coming of the transistor. As well as with the transistor, a study of the integrated circuit is carried out, yet with deeper insight, for that is the central aim of this Final Project report. For this component a more exhaustive explanation of its manufacture process, materials and theories can be provided. Also, the historical and social of that time is described. To complete the report, a brief review is done about examples of applications of the integrated circuit and thus highlight the technological revolution that the microchip development brought.

A tool for the automatic analysis of single events effects on electronic circuits

Nowadays integrated circuit reliability is challenged by both variability and working conditions. Environmental radiation has become a major issue when ensuring the circuit correct behavior. The required radiation and later analysis performed to the circuit boards is both fund and time expensive. The lack of tools which support pre-manufacturing radiation hardness analysis hinders circuit designers tasks. This paper describes an extensively customizable simulation tool for the characterization of radiation effects on electronic systems. The proposed tool can produce an in depth analysis of a complete circuit in almost any kind of radiation environment in affordable computation times.