948 resultados para Histograms of Oriented Gradients


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Sediments at the southern summit of Hydrate Ridge display two distinct modes of gas hydrate occurrence. The dominant mode is associated with active venting of gas exsolved from the accretionary prism and leads to high concentrations (15%-40% of pore space) of gas hydrate in seafloor or near-surface sediments at and around the topographic summit of southern Hydrate Ridge. These near-surface gas hydrates are mainly composed of previously buried microbial methane but also contain a significant (10%-15%) component of thermogenic hydrocarbons and are overprinted with microbial methane currently being generated in shallow sediments. Focused migration pathways with high gas saturation (>65%) abutting the base of gas hydrate stability create phase equilibrium conditions that permit the flow of a gas phase through the gas hydrate stability zone. Gas seepage at the summit supports rapid growth of gas hydrates and vigorous anaerobic methane oxidation. The other mode of gas hydrate occurs in slope basins and on the saddle north of the southern summit and consists of lower average concentrations (0.5%-5%) at greater depths (30-200 meters below seafloor [mbsf]) resulting from the buildup of in situ-generated dissolved microbial methane that reaches saturation levels with respect to gas hydrate stability at 30-50 mbsf. Net rates of sulfate reduction in the slope basin and ridge saddle sites estimated from curve fitting of concentration gradients are 2-4 mmol/m**3/yr, and integrated net rates are 20-50 mmol/m**2/yr. Modeled microbial methane production rates are initially 1.5 mmol/m**3/yr in sediments just beneath the sulfate reduction zone but rapidly decrease to rates of <0.1 mmol/m**3/yr at depths >100 mbsf. Integrated net rates of methane production in sediments away from the southern summit of Hydrate Ridge are 25-80 mmol/m**2/yr. Anaerobic methane oxidation is minor or absent in cored sediments away from the summit of southern Hydrate Ridge. Ethane-enriched Structure I gas hydrate solids are buried more rapidly than ethane-depleted dissolved gas in the pore water because of advection from compaction. With subsidence beneath the gas hydrate stability zone, the ethane (mainly of low-temperature thermogenic origin) is released back to the dissolved gas-free gas phases and produces a discontinuous decrease in the C1/C2 vs. depth trend. These ethane fractionation effects may be useful to recognize and estimate levels of gas hydrate occurrence in marine sediments.

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La temperatura es una preocupación que juega un papel protagonista en el diseño de circuitos integrados modernos. El importante aumento de las densidades de potencia que conllevan las últimas generaciones tecnológicas ha producido la aparición de gradientes térmicos y puntos calientes durante el funcionamiento normal de los chips. La temperatura tiene un impacto negativo en varios parámetros del circuito integrado como el retardo de las puertas, los gastos de disipación de calor, la fiabilidad, el consumo de energía, etc. Con el fin de luchar contra estos efectos nocivos, la técnicas de gestión dinámica de la temperatura (DTM) adaptan el comportamiento del chip en función en la información que proporciona un sistema de monitorización que mide en tiempo de ejecución la información térmica de la superficie del dado. El campo de la monitorización de la temperatura en el chip ha llamado la atención de la comunidad científica en los últimos años y es el objeto de estudio de esta tesis. Esta tesis aborda la temática de control de la temperatura en el chip desde diferentes perspectivas y niveles, ofreciendo soluciones a algunos de los temas más importantes. Los niveles físico y circuital se cubren con el diseño y la caracterización de dos nuevos sensores de temperatura especialmente diseñados para los propósitos de las técnicas DTM. El primer sensor está basado en un mecanismo que obtiene un pulso de anchura variable dependiente de la relación de las corrientes de fuga con la temperatura. De manera resumida, se carga un nodo del circuito y posteriormente se deja flotando de tal manera que se descarga a través de las corrientes de fugas de un transistor; el tiempo de descarga del nodo es la anchura del pulso. Dado que la anchura del pulso muestra una dependencia exponencial con la temperatura, la conversión a una palabra digital se realiza por medio de un contador logarítmico que realiza tanto la conversión tiempo a digital como la linealización de la salida. La estructura resultante de esta combinación de elementos se implementa en una tecnología de 0,35 _m. El sensor ocupa un área muy reducida, 10.250 nm2, y consume muy poca energía, 1.05-65.5nW a 5 muestras/s, estas cifras superaron todos los trabajos previos en el momento en que se publicó por primera vez y en el momento de la publicación de esta tesis, superan a todas las implementaciones anteriores fabricadas en el mismo nodo tecnológico. En cuanto a la precisión, el sensor ofrece una buena linealidad, incluso sin calibrar; se obtiene un error 3_ de 1,97oC, adecuado para tratar con las aplicaciones de DTM. Como se ha explicado, el sensor es completamente compatible con los procesos de fabricación CMOS, este hecho, junto con sus valores reducidos de área y consumo, lo hacen especialmente adecuado para la integración en un sistema de monitorización de DTM con un conjunto de monitores empotrados distribuidos a través del chip. Las crecientes incertidumbres de proceso asociadas a los últimos nodos tecnológicos comprometen las características de linealidad de nuestra primera propuesta de sensor. Con el objetivo de superar estos problemas, proponemos una nueva técnica para obtener la temperatura. La nueva técnica también está basada en las dependencias térmicas de las corrientes de fuga que se utilizan para descargar un nodo flotante. La novedad es que ahora la medida viene dada por el cociente de dos medidas diferentes, en una de las cuales se altera una característica del transistor de descarga |la tensión de puerta. Este cociente resulta ser muy robusto frente a variaciones de proceso y, además, la linealidad obtenida cumple ampliamente los requisitos impuestos por las políticas DTM |error 3_ de 1,17oC considerando variaciones del proceso y calibrando en dos puntos. La implementación de la parte sensora de esta nueva técnica implica varias consideraciones de diseño, tales como la generación de una referencia de tensión independiente de variaciones de proceso, que se analizan en profundidad en la tesis. Para la conversión tiempo-a-digital, se emplea la misma estructura de digitalización que en el primer sensor. Para la implementación física de la parte de digitalización, se ha construido una biblioteca de células estándar completamente nueva orientada a la reducción de área y consumo. El sensor resultante de la unión de todos los bloques se caracteriza por una energía por muestra ultra baja (48-640 pJ) y un área diminuta de 0,0016 mm2, esta cifra mejora todos los trabajos previos. Para probar esta afirmación, se realiza una comparación exhaustiva con más de 40 propuestas de sensores en la literatura científica. Subiendo el nivel de abstracción al sistema, la tercera contribución se centra en el modelado de un sistema de monitorización que consiste de un conjunto de sensores distribuidos por la superficie del chip. Todos los trabajos anteriores de la literatura tienen como objetivo maximizar la precisión del sistema con el mínimo número de monitores. Como novedad, en nuestra propuesta se introducen nuevos parámetros de calidad aparte del número de sensores, también se considera el consumo de energía, la frecuencia de muestreo, los costes de interconexión y la posibilidad de elegir diferentes tipos de monitores. El modelo se introduce en un algoritmo de recocido simulado que recibe la información térmica de un sistema, sus propiedades físicas, limitaciones de área, potencia e interconexión y una colección de tipos de monitor; el algoritmo proporciona el tipo seleccionado de monitor, el número de monitores, su posición y la velocidad de muestreo _optima. Para probar la validez del algoritmo, se presentan varios casos de estudio para el procesador Alpha 21364 considerando distintas restricciones. En comparación con otros trabajos previos en la literatura, el modelo que aquí se presenta es el más completo. Finalmente, la última contribución se dirige al nivel de red, partiendo de un conjunto de monitores de temperatura de posiciones conocidas, nos concentramos en resolver el problema de la conexión de los sensores de una forma eficiente en área y consumo. Nuestra primera propuesta en este campo es la introducción de un nuevo nivel en la jerarquía de interconexión, el nivel de trillado (o threshing en inglés), entre los monitores y los buses tradicionales de periféricos. En este nuevo nivel se aplica selectividad de datos para reducir la cantidad de información que se envía al controlador central. La idea detrás de este nuevo nivel es que en este tipo de redes la mayoría de los datos es inútil, porque desde el punto de vista del controlador sólo una pequeña cantidad de datos |normalmente sólo los valores extremos| es de interés. Para cubrir el nuevo nivel, proponemos una red de monitorización mono-conexión que se basa en un esquema de señalización en el dominio de tiempo. Este esquema reduce significativamente tanto la actividad de conmutación sobre la conexión como el consumo de energía de la red. Otra ventaja de este esquema es que los datos de los monitores llegan directamente ordenados al controlador. Si este tipo de señalización se aplica a sensores que realizan conversión tiempo-a-digital, se puede obtener compartición de recursos de digitalización tanto en tiempo como en espacio, lo que supone un importante ahorro de área y consumo. Finalmente, se presentan dos prototipos de sistemas de monitorización completos que de manera significativa superan la características de trabajos anteriores en términos de área y, especialmente, consumo de energía. Abstract Temperature is a first class design concern in modern integrated circuits. The important increase in power densities associated to recent technology evolutions has lead to the apparition of thermal gradients and hot spots during run time operation. Temperature impacts several circuit parameters such as speed, cooling budgets, reliability, power consumption, etc. In order to fight against these negative effects, dynamic thermal management (DTM) techniques adapt the behavior of the chip relying on the information of a monitoring system that provides run-time thermal information of the die surface. The field of on-chip temperature monitoring has drawn the attention of the scientific community in the recent years and is the object of study of this thesis. This thesis approaches the matter of on-chip temperature monitoring from different perspectives and levels, providing solutions to some of the most important issues. The physical and circuital levels are covered with the design and characterization of two novel temperature sensors specially tailored for DTM purposes. The first sensor is based upon a mechanism that obtains a pulse with a varying width based on the variations of the leakage currents on the temperature. In a nutshell, a circuit node is charged and subsequently left floating so that it discharges away through the subthreshold currents of a transistor; the time the node takes to discharge is the width of the pulse. Since the width of the pulse displays an exponential dependence on the temperature, the conversion into a digital word is realized by means of a logarithmic counter that performs both the timeto- digital conversion and the linearization of the output. The structure resulting from this combination of elements is implemented in a 0.35_m technology and is characterized by very reduced area, 10250 nm2, and power consumption, 1.05-65.5 nW at 5 samples/s, these figures outperformed all previous works by the time it was first published and still, by the time of the publication of this thesis, they outnumber all previous implementations in the same technology node. Concerning the accuracy, the sensor exhibits good linearity, even without calibration it displays a 3_ error of 1.97oC, appropriate to deal with DTM applications. As explained, the sensor is completely compatible with standard CMOS processes, this fact, along with its tiny area and power overhead, makes it specially suitable for the integration in a DTM monitoring system with a collection of on-chip monitors distributed across the chip. The exacerbated process fluctuations carried along with recent technology nodes jeop-ardize the linearity characteristics of the first sensor. In order to overcome these problems, a new temperature inferring technique is proposed. In this case, we also rely on the thermal dependencies of leakage currents that are used to discharge a floating node, but now, the result comes from the ratio of two different measures, in one of which we alter a characteristic of the discharging transistor |the gate voltage. This ratio proves to be very robust against process variations and displays a more than suficient linearity on the temperature |1.17oC 3_ error considering process variations and performing two-point calibration. The implementation of the sensing part based on this new technique implies several issues, such as the generation of process variations independent voltage reference, that are analyzed in depth in the thesis. In order to perform the time-to-digital conversion, we employ the same digitization structure the former sensor used. A completely new standard cell library targeting low area and power overhead is built from scratch to implement the digitization part. Putting all the pieces together, we achieve a complete sensor system that is characterized by ultra low energy per conversion of 48-640pJ and area of 0.0016mm2, this figure outperforms all previous works. To prove this statement, we perform a thorough comparison with over 40 works from the scientific literature. Moving up to the system level, the third contribution is centered on the modeling of a monitoring system consisting of set of thermal sensors distributed across the chip. All previous works from the literature target maximizing the accuracy of the system with the minimum number of monitors. In contrast, we introduce new metrics of quality apart form just the number of sensors; we consider the power consumption, the sampling frequency, the possibility to consider different types of monitors and the interconnection costs. The model is introduced in a simulated annealing algorithm that receives the thermal information of a system, its physical properties, area, power and interconnection constraints and a collection of monitor types; the algorithm yields the selected type of monitor, the number of monitors, their position and the optimum sampling rate. We test the algorithm with the Alpha 21364 processor under several constraint configurations to prove its validity. When compared to other previous works in the literature, the modeling presented here is the most complete. Finally, the last contribution targets the networking level, given an allocated set of temperature monitors, we focused on solving the problem of connecting them in an efficient way from the area and power perspectives. Our first proposal in this area is the introduction of a new interconnection hierarchy level, the threshing level, in between the monitors and the traditional peripheral buses that applies data selectivity to reduce the amount of information that is sent to the central controller. The idea behind this new level is that in this kind of networks most data are useless because from the controller viewpoint just a small amount of data |normally extreme values| is of interest. To cover the new interconnection level, we propose a single-wire monitoring network based on a time-domain signaling scheme that significantly reduces both the switching activity over the wire and the power consumption of the network. This scheme codes the information in the time domain and allows a straightforward obtention of an ordered list of values from the maximum to the minimum. If the scheme is applied to monitors that employ TDC, digitization resource sharing is achieved, producing an important saving in area and power consumption. Two prototypes of complete monitoring systems are presented, they significantly overcome previous works in terms of area and, specially, power consumption.

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Swift heavy ion irradiation (ions with mass heavier than 15 and energy exceeding MeV/amu) transfer their energy mainly to the electronic system with small momentum transfer per collision. Therefore, they produce linear regions (columnar nano-tracks) around the straight ion trajectory, with marked modifications with respect to the virgin material, e.g., phase transition, amorphization, compaction, changes in physical or chemical properties. In the case of crystalline materials the most distinctive feature of swift heavy ion irradiation is the production of amorphous tracks embedded in the crystal. Lithium niobate is a relevant optical material that presents birefringence due to its anysotropic trigonal structure. The amorphous phase is certainly isotropic. In addition, its refractive index exhibits high contrast with those of the crystalline phase. This allows one to fabricate waveguides by swift ion irradiation with important technological relevance. From the mechanical point of view, the inclusion of an amorphous nano-track (with a density 15% lower than that of the crystal) leads to the generation of important stress/strain fields around the track. Eventually these fields are the origin of crack formation with fatal consequences for the integrity of the samples and the viability of the method for nano-track formation. For certain crystal cuts (X and Y), these fields are clearly anisotropic due to the crystal anisotropy. We have used finite element methods to calculate the stress/strain fields that appear around the ion- generated amorphous nano-tracks for a variety of ion energies and doses. A very remarkable feature for X cut-samples is that the maximum shear stress appears on preferential planes that form +/-45º with respect to the crystallographic planes. This leads to the generation of oriented surface cracks when the dose increases. The growth of the cracks along the anisotropic crystal has been studied by means of novel extended finite element methods, which include cracks as discontinuities. In this way we can study how the length and depth of a crack evolves as function of the ion dose. In this work we will show how the simulations compare with experiments and their application in materials modification by ion irradiation.

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The study of temperature gradients in cold stores and containers is a critical issue in the food industry for the quality assurance of products during transport, as well as forminimizing losses. The objective of this work is to develop a new methodology of data analysis based on phase space graphs of temperature and enthalpy, collected by means of multidistributed, low cost and autonomous wireless sensors and loggers. A transoceanic refrigerated transport of lemons in a reefer container ship from Montevideo (Uruguay) to Cartagena (Spain) was monitored with a network of 39 semi-passive TurboTag RFID loggers and 13 i-button loggers. Transport included intermodal transit from transoceanic to short shipping vessels and a truck trip. Data analysis is carried out using qualitative phase diagrams computed on the basis of Takens?Ruelle reconstruction of attractors. Fruit stress is quantified in terms of the phase diagram area which characterizes the cyclic behaviour of temperature. Areas within the enthalpy phase diagram computed for the short sea shipping transport were 5 times higher than those computed for the long sea shipping, with coefficients of variation above 100% for both periods. This new methodology for data analysis highlights the significant heterogeneity of thermohygrometric conditions at different locations in the container.