989 resultados para FPGA (Field programmable gate arrays)
Resumo:
Report for the scientific sojourn carried out at the Université Catholique de Louvain, Belgium, from March until June 2007. In the first part, the impact of important geometrical parameters such as source and drain thickness, fin spacing, spacer width, etc. on the parasitic fringing capacitance component of multiple-gate field-effect transistors (MuGFET) is deeply analyzed using finite element simulations. Several architectures such as single gate, FinFETs (double gate), triple-gate represented by Pi-gate MOSFETs are simulated and compared in terms of channel and fringing capacitances for the same occupied die area. Simulations highlight the great impact of diminishing the spacing between fins for MuGFETs and the trade-off between the reduction of parasitic source and drain resistances and the increase of fringing capacitances when Selective Epitaxial Growth (SEG) technology is introduced. The impact of these technological solutions on the transistor cut-off frequencies is also discussed. The second part deals with the study of the effect of the volume inversion (VI) on the capacitances of undoped Double-Gate (DG) MOSFETs. For that purpose, we present simulation results for the capacitances of undoped DG MOSFETs using an explicit and analytical compact model. It monstrates that the transition from volume inversion regime to dual gate behaviour is well simulated. The model shows an accurate dependence on the silicon layer thickness,consistent withtwo dimensional numerical simulations, for both thin and thick silicon films. Whereas the current drive and transconductance are enhanced in volume inversion regime, our results show thatintrinsic capacitances present higher values as well, which may limit the high speed (delay time) behaviour of DG MOSFETs under volume inversion regime.
Resumo:
We report on a field-effect light emitting device based on silicon nanocrystals in silicon oxide deposited by plasma-enhanced chemical vapor deposition. The device shows high power efficiency and long lifetime. The power efficiency is enhanced up to 0.1 %25 by the presence of a silicon nitride control layer. The leakage current reduction induced by this nitride buffer effectively increases the power efficiency two orders of magnitude with regard to similarly processed devices with solely oxide. In addition, the nitride cools down the electrons that reach the polycrystalline silicon gate lowering the formation of defects, which significantly reduces the device degradation.
Resumo:
The thesis presented here includes the designing of underwater transducer arrays, taking into account the ‘interaction effects’ [30] among the closely packed radiators. Methods of minimizing the ‘interaction effects‘ by modifying the radiating aperture, are investigated. The need for this study arises as it is one of the important peculiar limitations that stands in the way of achieving maximum range of transmission of acoustic signals. Application of the modified array format for the generation of narrow beam low frequency sound waves, through nonlinear interactions, is discussed. Other techniques that can be advantageously exploited in array synthesis are also investigated
Resumo:
The aim of this study was to develop a laboratory method for time response evaluation on electronically controlled spray equipment using Programmable Logic Controllers (PLCs). For that purpose, a PLC controlled digital drive inverter was set up to drive an asynchronous electric motor linked to a centrifugal pump on a experimental sprayer equipped with electronic flow control. The PLC was operated via RS232 serial communication from a PC computer. A user program was written to control de motor by adjusting the following system variables, all related to the motor speed: time stopped; ramp up and ramp down times, time running at a given constant speed and ramp down time to stop the motor. This set up was used in conjunction with a data acquisition system to perform laboratory tests with an electronically controlled sprayer. Time response for pressure stabilization was measured while changing the pump speed by +/-20%. The results showed that for a 0.2 s ramp time increasing the motor speed, as an example, an AgLogix Flow Control system (Midwest Technologies Inc.) took 22 s in average to readjust the pressure. When decreasing the motor speed, this time response was down to 8 s. General results also showed that this kind of methodology could make easier the definition of standards for tests on electronically controlled application equipment.
Resumo:
In the course of this study, stiffness of a fibril array of mineralized collagen fibrils modeled with a mean field method was validated experimentally at site-matched two levels of tissue hierarchy using mineralized turkey leg tendons (MTLT). The applied modeling approaches allowed to model the properties of this unidirectional tissue from nanoscale (mineralized collagen fibrils) to macroscale (mineralized tendon). At the microlevel, the indentation moduli obtained with a mean field homogenization scheme were compared to the experimental ones obtained with microindentation. At the macrolevel, the macroscopic stiffness predicted with micro finite element (μFE) models was compared to the experimental stiffness measured with uniaxial tensile tests. Elastic properties of the elements in μFE models were injected from the mean field model or two-directional microindentations. Quantitatively, the indentation moduli can be properly predicted with the mean-field models. Local stiffness trends within specific tissue morphologies are very weak, suggesting additional factors responsible for the stiffness variations. At macrolevel, the μFE models underestimate the macroscopic stiffness, as compared to tensile tests, but the correlations are strong.
Resumo:
In this paper, an architecture based on a scalable and flexible set of Evolvable Processing arrays is presented. FPGA-native Dynamic Partial Reconfiguration (DPR) is used for evolution, which is done intrinsically, letting the system to adapt autonomously to variable run-time conditions, including the presence of transient and permanent faults. The architecture supports different modes of operation, namely: independent, parallel, cascaded or bypass mode. These modes of operation can be used during evolution time or during normal operation. The evolvability of the architecture is combined with fault-tolerance techniques, to enhance the platform with self-healing features, making it suitable for applications which require both high adaptability and reliability. Experimental results show that such a system may benefit from accelerated evolution times, increased performance and improved dependability, mainly by increasing fault tolerance for transient and permanent faults, as well as providing some fault identification possibilities. The evolvable HW array shown is tailored for window-based image processing applications.