A Feasibility Study on Embedded Micro-Electromechanical Sensors and Systems (MEMS) for Monitoring Highway Structures, TR-575, 2011

Micro-electromechanical systems (MEMS) provide vast improvements over existing sensing methods in the context of structural health monitoring (SHM) of highway infrastructure systems, including improved system reliability, improved longevity and enhanced system performance, improved safety against natural hazards and vibrations, and a reduction in life cycle cost in both operating and maintaining the infrastructure. Advancements in MEMS technology and wireless sensor networks provide opportunities for long-term continuous, real-time structural health monitoring of pavements and bridges at low cost within the context of sustainable infrastructure systems. The primary objective of this research was to investigate the use of MEMS in highway structures for health monitoring purposes. This study focused on investigating the use of MEMS and their potential applications in concrete through a comprehensive literature review, a vendor survey, and a laboratory study, as well as a small-scale field study. Based on the comprehensive literature review and vendor survey, the latest information available on off-the-shelf MEMS devices, as well as research prototypes, for bridge, pavement, and traffic applications were synthesized. A commercially-available wireless concrete monitoring system based on radio-frequency identification (RFID) technology and off-the-shelf temperature and humidity sensors were tested under controlled laboratory and field conditions. The test results validated the ability of the RFID wireless concrete monitoring system in accurately measuring the temperature both inside the laboratory and in the field under severe weather conditions. In consultation with the project technical advisory committee (TAC), the most relevant MEMS-based transportation infrastructure research applications to explore in the future were also highlighted and summarized.

Iowa System of Bridge Deck Rehabilitation with Cathodic Protection, HR-1044, 1986

Bridge deck and substructure deterioration due to the corrosive effects of deicing chemicals on reinforcing steel is a problem facing many transportation agencies. The main concern is protection of older bridges with uncoated reinforcing steel. Many different methods have been tried over the past years to repair bridge decks. The Iowa system of bridge deck rehabilitation has proven to be very effective. It consists of scarifying the deck surface, removing any deteriorated concrete, and overlaying with low slump dense concrete. Another rehabilitation method that has emerged is cathodic protection. It has been used for many years in the protection of underground pipelines and in 1973 was first installed on a bridge deck. Cathodic protection works by applying an external source of direct current to the embedded reinforcing steel, thereby changing the electrochemical process of corrosion. The corroding steel, which is anodic, is protected by changing it to a cathodic state. The technology involved in cathodic protection as applied to bridge decks has improved over the last 12 years. One company marketing new technology in cathodic protection systems is Raychem Corporation of Menlo Park, California. Their system utilizes a Ferex anode mesh that distributes the impressed direct current over the deck surface. Ferex mesh was selected because it seemed readily adaptable to the Iowa system of bridge deck rehabilitation. The bridge deck would be scarified, deteriorated concrete removed, Ferex anode mesh installed, and overlaid with low slump dense concrete. The Federal Highway Administration (FHWA) promotes cathodic protection under Demonstration Project No. 34, "Cathodic Protection for Reinforced Concrete Bridge Decks."

Efficient self-synchronised blind audio watermarking system based on time domain and FFT amplitude modification

Many audio watermarking schemes divide the audio signal into several blocks such that part of the watermark is embedded into each of them. One of the key issues in these block-oriented watermarking schemes is to preserve the synchronisation, i.e. to recover the exact position of each block in the mark recovery process. In this paper, a novel time domain synchronisation technique is presented together with a new blind watermarking scheme which works in the Discrete Fourier Transform (DFT or FFT) domain. The combined scheme provides excellent imperceptibility results whilst achieving robustness against typical attacks. Furthermore, the execution of the scheme is fast enough to be used in real-time applications. The excellent transparency of the embedding algorithm makes it particularly useful for professional applications, such as the embedding of monitoring information in broadcast signals. The scheme is also compared with some recent results of the literature.

Design of an Embedded Computer Board for Networking Applications

Tämä diplomityö tehtiin Convergens Oy:lle. Convergens on elektroniikan suunnittelutoimisto, joka on erikoistunut sulautettuihin järjestelmiin sekä tietoliikennetekniikkaan. Diplomityön tavoitteena oli suunnitella tietokonekortti tietoliikennesovelluksia varten asiakkaalle, jolta vaatimusmäärittelyt tulivat. Työ on rajattu koskemaan laitteen prototyypin suunnittelua. Työssä suunnitellaan pääasiassa WLAN-tukiaseman tietokone. Tukiasema onasennettavissa toimistoihin, varastoihin, kauppoihin sekä myös liikkuvaan ajoneuvoon. Suunnittelussa on otettu nämä asiat huomioon, ja laitteen akun pystyy lataamaan muun muassa auton akulla. Langattomat tekniikat ovat voimakkaasti yleistymässä, ja tämän työn tukiasema tarjoaakin varteenotettavan vaihtoehdon lukuisilla ominaisuuksillaan. Mukana on mm. GPS, Bluetooth sekä Ethernet-valmius. Langattomien tekniikoiden lisäksi myös sulautetut järjestelmät ovat voimakkaasti yleistymässä, ja nykyään mikroprosessoreita löytääkin lähesmistä vain. Tässä projektissa käytetty prosessori on nopeutensa puolesta kilpailukykyinen, ja siitä löytyy useita eri rajapintoja. Jatkossa tietokonekortille on myös tulossa WiMAX-tuki, joka lisää tukiaseman tulevaisuuden arvoa asiakkaalle. Projektiin valittu Freescalen MPC8321E-prosessori on PowerPC-arkkitehtuuriin perustuva ja juuri markkinoille ilmestynyt. Tämä toi mukanaan lisähaasteen, sillä kyseisestä prosessorista ei ollut vielä kaikkea tietoa saatavilla. Mekaniikka toi omat haasteensa mukanaan, sillä se rajoitti piirilevyn koonniin, että ylimääräistä piirilevytilaa ei juurikaan jäänyt. Tämän takia esimerkiksi DDR-muistit olivat haastavia reitittää, sillä muistivetojen on oltava melko samanpituisia keskenään. Käyttöjärjestelmänä projektissa käytetään Linuxia. Suunnittelu alkoi keväällä 2007 ja toimiva prototyyppi oli valmis alkusyksystä. Prototyypin testaus osoitti, että tietokonekortti kykenee täyttämään kaikki asiakkaan vaatimukset. Prototyypin testauksessa löytyneet viat ja optimoinnit on tarkoitus korjata tuotantomalliin, joten se antaa hyvän pohjan jatkosuunnittelua varten.

A System-Level Simulation Model for a Protocol Processor

As the development of integrated circuit technology continues to follow Moore’s law the complexity of circuits increases exponentially. Traditional hardware description languages such as VHDL and Verilog are no longer powerful enough to cope with this level of complexity and do not provide facilities for hardware/software codesign. Languages such as SystemC are intended to solve these problems by combining the powerful expression of high level programming languages and hardware oriented facilities of hardware description languages. To fully replace older languages in the desing flow of digital systems SystemC should also be synthesizable. The devices required by modern high speed networks often share the same tight constraints for e.g. size, power consumption and price with embedded systems but have also very demanding real time and quality of service requirements that are difficult to satisfy with general purpose processors. Dedicated hardware blocks of an application specific instruction set processor are one way to combine fast processing speed, energy efficiency, flexibility and relatively low time-to-market. Common features can be identified in the network processing domain making it possible to develop specialized but configurable processor architectures. One such architecture is the TACO which is based on transport triggered architecture. The architecture offers a high degree of parallelism and modularity and greatly simplified instruction decoding. For this M.Sc.(Tech) thesis, a simulation environment for the TACO architecture was developed with SystemC 2.2 using an old version written with SystemC 1.0 as a starting point. The environment enables rapid design space exploration by providing facilities for hw/sw codesign and simulation and an extendable library of automatically configured reusable hardware blocks. Other topics that are covered are the differences between SystemC 1.0 and 2.2 from the viewpoint of hardware modeling, and compilation of a SystemC model into synthesizable VHDL with Celoxica Agility SystemC Compiler. A simulation model for a processor for TCP/IP packet validation was designed and tested as a test case for the environment.

A Co-Processor Approach for Efficient Java Execution in Embedded Systems

This thesis deals with a hardware accelerated Java virtual machine, named REALJava. The REALJava virtual machine is targeted for resource constrained embedded systems. The goal is to attain increased computational performance with reduced power consumption. While these objectives are often seen as trade-offs, in this context both of them can be attained simultaneously by using dedicated hardware. The target level of the computational performance of the REALJava virtual machine is initially set to be as fast as the currently available full custom ASIC Java processors. As a secondary goal all of the components of the virtual machine are designed so that the resulting system can be scaled to support multiple co-processor cores. The virtual machine is designed using the hardware/software co-design paradigm. The partitioning between the two domains is flexible, allowing customizations to the resulting system, for instance the floating point support can be omitted from the hardware in order to decrease the size of the co-processor core. The communication between the hardware and the software domains is encapsulated into modules. This allows the REALJava virtual machine to be easily integrated into any system, simply by redesigning the communication modules. Besides the virtual machine and the related co-processor architecture, several performance enhancing techniques are presented. These include techniques related to instruction folding, stack handling, method invocation, constant loading and control in time domain. The REALJava virtual machine is prototyped using three different FPGA platforms. The original pipeline structure is modified to suit the FPGA environment. The performance of the resulting Java virtual machine is evaluated against existing Java solutions in the embedded systems field. The results show that the goals are attained, both in terms of computational performance and power consumption. Especially the computational performance is evaluated thoroughly, and the results show that the REALJava is more than twice as fast as the fastest full custom ASIC Java processor. In addition to standard Java virtual machine benchmarks, several new Java applications are designed to both verify the results and broaden the spectrum of the tests.

RTOS Framework for Real-Time Control System

This thesis is done as a complementary part for the active magnet bearing (AMB) control software development project in Lappeenranta University of Technology. The main focus of the thesis is to examine an idea of a real-time operating system (RTOS) framework that operates in a dedicated digital signal processor (DSP) environment. General use real-time operating systems do not necessarily provide sufficient platform for periodic control algorithm utilisation. In addition, application program interfaces found in real-time operating systems are commonly non-existent or provided as chip-support libraries, thus hindering platform independent software development. Hence, two divergent real-time operating systems and additional periodic extension software with the framework design are examined to find solutions for the research problems. The research is discharged by; tracing the selected real-time operating system, formulating requirements for the system, and designing the real-time operating system framework (OSFW). The OSFW is formed by programming the framework and conjoining the outcome with the RTOS and the periodic extension. The system is tested and functionality of the software is evaluated in theoretical context of the Rate Monotonic Scheduling (RMS) theory. The performance of the OSFW and substance of the approach are discussed in contrast to the research theme. The findings of the thesis demonstrates that the forged real-time operating system framework is a viable groundwork solution for periodic control applications.

Dynamic Ownership in Family Business System – A Portfolio Business Approach

Family businesses are among the longest-lived most prevalent institutions in the world and they are an important source of economic development and growth. Ownership is a key to the business life of the firm and also one main key in family business definition. There is only a little portfolio entrepreneurship or portfolio business research within family business context. The absence of empirical evidence on the long-term relationship between family ownership and portfolio development presents an important gap in the family business literature. This study deals with the family business ownership changes and the development of portfolios in the family business and it is positioned in to the conversation of family business, growth, ownership, management and strategy. This study contributes and expands the existing body of theory on family business and ownership. From the theoretical point of view this study combines insights from the fields of portfolio entrepreneurship, ownership, and family business and integrate them. This crossfertilization produces interesting empirical and theoretical findings that can constitute a basis for solid contributions to the understanding of ownership dynamics and portfolio entrepreneurship in family firms. The research strategy chosen for this study represents longitudinal, qualitative, hermeneutic, and deductive approaches.The empirical part of study is using a case study approach with embedded design, that is, multiple levels of analysis within a single study. The study consists of two cases and it begins with a pilot case which will form a preunderstanding on the phenomenon. Pilot case develops the methodology approach to build in the main case and the main case will deepen the understanding of the phenomenon. This study develops and tests a research method of family business portfolio development focusing on investigating how ownership changes are influencing to the family business structures over time. This study reveals the linkages between dimensions of ownership and how they give rise to portfolio business development within the context of the family business. The empirical results of the study suggest that family business ownership is dynamic and owners are using ownership as a tool for creating business portfolios.

Automatic system identification and optimization of centrifugal pump operation

Centrifugal pumps are a notable end-consumer of electrical energy. Typical application of a centrifugal pump is the filling or emptying of a reservoir tank, where the pump is often operated at a constant speed until the process is completed. Installing a frequency converter to control the motor substitutes the traditional fixed-speed pumping system, allows the optimization of rotational speed profile for the pumping tasks and enables the estimation of rotational speed and shaft torque of an induction motor without any additional measurements from the motor shaft. Utilization of variable-speed operation provides the possibility to decrease the overall energy consumption of the pumping task. The static head of the pumping process may change during the pumping task. In such systems, the minimum rotational speed changes during reservoir filling or emptying, and the minimum energy consumption can’t be achieved with a fixed rotational speed. This thesis presents embedded algorithms to automatically identify, optimize and monitor pumping processes between supply and destination reservoirs, and evaluates the changing static head –based optimization method.

Histopathological, immunohistochemical, and molecular study of BHV-5 infection in the central nervous system of experimentally infected calves

Bovine meningoencephalitis caused by BHV-5, a double-stranded DNA enveloped virus that belongs to the family Herpesviridae and subfamily Alphaherpesvirinae, is an important differential diagnosis of central nervous diseases. The aim of this study was to describe the histological changes in the central nervous system of calves experimentally infected with BHV-5 and compare these changes with the PCR and IHC results. Formalin-fixed paraffin-embedded central nervous system samples from calves previously inoculated with BHV-5 were microscopically evaluated and tested using IHC and PCR. All the animals presented with nonsuppurative meningoencephalitis. From 18 evaluated areas of each calf, 32.41% and 35.19% were positive by IHC and PCR, respectively. The telencephalon presented more accentuated lesions and positive areas in the PCR than other encephalic areas and was the best sampling area for diagnostic purposes. Positive areas in the IHC and PCR were more injured than IHC and PCR negative areas. The animal with neurological signs showed more PCR- and IHC-positive areas than the other animals.

A Model-Based Development and Verification Framework for Distributed System-on-Chip Architecture

The capabilities and thus, design complexity of VLSI-based embedded systems have increased tremendously in recent years, riding the wave of Moore’s law. The time-to-market requirements are also shrinking, imposing challenges to the designers, which in turn, seek to adopt new design methods to increase their productivity. As an answer to these new pressures, modern day systems have moved towards on-chip multiprocessing technologies. New architectures have emerged in on-chip multiprocessing in order to utilize the tremendous advances of fabrication technology. Platform-based design is a possible solution in addressing these challenges. The principle behind the approach is to separate the functionality of an application from the organization and communication architecture of hardware platform at several levels of abstraction. The existing design methodologies pertaining to platform-based design approach don’t provide full automation at every level of the design processes, and sometimes, the co-design of platform-based systems lead to sub-optimal systems. In addition, the design productivity gap in multiprocessor systems remain a key challenge due to existing design methodologies. This thesis addresses the aforementioned challenges and discusses the creation of a development framework for a platform-based system design, in the context of the SegBus platform - a distributed communication architecture. This research aims to provide automated procedures for platform design and application mapping. Structural verification support is also featured thus ensuring correct-by-design platforms. The solution is based on a model-based process. Both the platform and the application are modeled using the Unified Modeling Language. This thesis develops a Domain Specific Language to support platform modeling based on a corresponding UML profile. Object Constraint Language constraints are used to support structurally correct platform construction. An emulator is thus introduced to allow as much as possible accurate performance estimation of the solution, at high abstraction levels. VHDL code is automatically generated, in the form of “snippets” to be employed in the arbiter modules of the platform, as required by the application. The resulting framework is applied in building an actual design solution for an MP3 stereo audio decoder application.

The Russian National Innovation System - an International Perspective

Russia inherited a large research and development (R&D) sector from the Soviet times, and has retained a substantial R&D sector today, compared with other emerging economies. However, Russia is falling behind in all indicators measuring innovative output in comparison with most developed countries. Russia’s innovation performance is disappointing, despite the available stock of human capital and overall investment in R&D. The communist legacy still influences the main actors of the innovation system. The federal state is still the most important funding source for R&D. Private companies are not investing in innovative activities, preferring to “import” innovations embedded in foreign technologies. Universities are outsiders in the innovation system, only a few universities carry out research activities. Nowadays, Russia is a resource-depended country. The economy depends on energy and metals for growth. The Russian economy faces the challenge of diversification and should embrace innovation, and shift to a knowledge economy to remain competitive in the long run. Therefore, Russia has to tackle the challenge of developing an efficient innovation system with its huge potential in science expertise and engineering know-how.

Embedded Service Bus for Internet of Things Interoperability

Internet of Things (IoT) technologies are developing rapidly, and therefore there exist several standards of interconnection protocols and platforms. The existence of heterogeneous protocols and platforms has become a critical challenge for IoT system developers. To mitigate this challenge, few alliances and organizations have taken the initiative to build a framework that helps to integrate application silos. Some of these frameworks focus only on a specific domain like home automation. However, the resource constraints in the large proportion of connected devices make it difficult to build an interoperable system using such frameworks. Therefore, a general purpose, lightweight interoperability framework that can be used for a range of devices is required. To tackle the heterogeneous nature, this work introduces an embedded, distributed and lightweight service bus, Lightweight IoT Service bus Architecture (LISA), which fits inside the network stack of a small real-time operating system for constrained nodes. LISA provides a uniform application programming interface for an IoT system on a range of devices with variable resource constraints. It hides platform and protocol variations underneath it, thus facilitating interoperability in IoT implementations. LISA is inspired by the Network on Terminal Architecture, a service centric open architecture by Nokia Research Center. Unlike many other interoperability frameworks, LISA is designed specifically for resource constrained nodes and it provides essential features of a service bus for easy service oriented architecture implementation. The presented architecture utilizes an intermediate computing layer, a Fog layer, between the small nodes and the cloud, thereby facilitating the federation of constrained nodes into subnetworks. As a result of a modular and distributed design, the part of LISA running in the Fog layer handles the heavy lifting to assist the lightweight portion of LISA inside the resource constrained nodes. Furthermore, LISA introduces a new networking paradigm, Node Centric Networking, to route messages across protocol boundaries to facilitate interoperability. This thesis presents a concept implementation of the architecture and creates a foundation for future extension towards a comprehensive interoperability framework for IoT.

The pancreatic islet system of the rock bass /|nby Edward Francis Squires. -- 260 St. Catharines, Ont. : [s. n.],

The endocrine pancreas of the rock bass (Ambloplites rupestris) was examined by light and electron microscopy. Two cell types with staining properties similar to mammalian A and B cells, and a third, non-staining cell type were found in the spherical pancreatic islets that were surrounded by a connective tissue capsule and embedded in two small masses of exocrine tissue. From an analysis of the ultrastructure of the A and B cells, a secretory cycle for each of these cell types was proposed. The secretory cycle of the A cell consisted of three well defined stages: (1) A cell production stage: during which A granule formation occurred in the sacs of the Golgi apparatus and the cell was characterized by the presence of numerous secretory granules, some elements of lamellar endoplasmic reticulum, and a homogeneously granular nucleus. The cytoplasm contained few distended cisternae, variable numbers of free ribosomes, microtubules and small vesicles. (2) A cell release stage: during which the release of A granules occurred and the cell usually contained several large distended cisternae and variable numbers of secretory granules. Granule release mechanisms included exocytosis, by which individual granules were released into the extracellular space after their membranes fused with the plasmalemma, and emiocytosis, by which one or more granules were released into a large cisterna whose membrane fused with the plasmalemma and formed a pore through which the cisternal contents passed out of the cell. (3) A cell reorganization stage: during which the changeover from the release stage to the production stage occurred and the reorganization of organelles and membrane structures took place. The cell contained few secretory granules and numerous small endoplasmic reticular cisternae. The cytoplasm exhibited less electron density than either of the other two stages. The A granule after formation underwent a series of morphological changes which were described in four numerically identified phases. The secretory cycle of the B cell consisred of two stages: (1) B cell production stage: during which the B granule formation occurred in the sacs of the Go1gi apparatus. The cell was characterized by an irregular outline, the presence of numerous secretory granules, and an irregularly shaped nucleus which contained variable amounts of clumped chromatin. The cytoplasm contained moderate amounts of lamellar endoplasmic reticulum studded with ribosomes, several small vesicles, and an active Go1gi apparatus. (2) B cell release stage: during which the release of B granules occurred. The cell contained a rounded nucleus with dispersed chromatin, several distended endoplasmic reticular cisternae and a variable number of secretory granules. Granule release occu~ by emiocytosis and exocytosis similar to that found for the A cell.

Dual-frequency dual-polarized slot -coupled compact microstrip antenna for communication system

A new design of' a dual-frequency dual-polarized square microsh'ip antenna fed along the diagonal, embedded with a square slot having three extended stubs for frequency tuning, is introduced. The proposed antenna was fabricated using a standard photolithographic method and the antenna was tested using the HP 3510(:; Vector Network Analyser. The antenna is capable of generating dual resonant frequencies with mutually perpendicular polarizations and broad radiation pattern characteristics. Such dual-frequency designs find wide applications in personal mobile handsets combining GSM and CDS 1800 modes, and applications in which different frequencies are used for emission and reception such as personal satellite communications and cellular network systems.