On-chip deposition of carbon nanotubes using CMOS microhotplates.

The direct deposition of carbon nanotubes on CMOS microhotplates is demonstrated in this paper. Tungsten microhotplates, fabricated on thin SOI membranes aside CMOS control circuitry, are used to locally grow carbon nanotubes by chemical vapour deposition. Unlike bulk heating of the entire chip, which could cause degradation to CMOS devices and interconnects due to high growth temperatures in excess of 500 °C, this novel technique allows carbon nanotubes to be grown on-chip in localized regions. The microfabricated heaters are thermally isolated from the rest of the CMOS chip as they are on the membranes. This allows carbon nanotubes to be grown alongside CMOS circuitry on the same wafer without any external heating, thus enabling new applications (e.g. smart gas sensing) where the integration of CMOS and carbon nanotubes is required.

Millisecond processing beyond chip technology: From electronics to photonics

There is a clear and increasing interest in short time annealing processing far below one second, i.e. the lower limit of Rapid Thermal Processing (RTP) called spike annealing. This was driven by the need of suppressing the so-called Transient Enhanced Diffusion in advanced boronimplanted shallow pn-junctions in silicon technology. Meanwhile the interest in flash lamp annealing (FLA) in the millisecond range spread out into other fields related to silicon technology and beyond. This paper reports on recent experiments regarding shallow junction engineering in germanium, annealing of ITO layers on glass and plastic foil to form an conductive layer as well as investigations which we did during the last years in the field of wide band gap semiconductor materials (SiC, ZnO). A more common feature evolving from our work was related to the modeling of wafer stress during millisecond thermal processing with flash lamps. Finally recent achievements in the field of silicon-based light emission basing on Metal-Oxide-Semiconductor Light Emitting Devices will be reported. © 2007 IEEE.

Thickness control of Molecular Beam Epitaxy grown layers at the 0.01-0.1 monolayer level

Electron tunnelling through semiconductor tunnel barriers is exponentially sensitive to the thickness of the barrier layer, and in the most common system, the AlAs tunnel barrier in GaAs, a one monolayer variation in thickness results in a 300% variation in the tunnelling current for a fixed bias voltage. We use this degree of sensitivity to demonstrate that the level of control at 0.06 monolayer can be achieved in the growth by molecular beam epitaxy, and the geometrical variation of layer thickness across a wafer at the 0.01 monolayer level can be detected.

High-efficiency InGaN/GaN quantum well structures on large area silicon substrates

The growth techniques which have enabled the realization of InGaN-based multi-quantum-well (MQW) structures with high internal quantum efficiencies (IQE) on 150mm (6-in.) silicon substrates are reviewed. InGaN/GaN MQWs are deposited onto GaN templates on large-area (111) silicon substrates, using AlGaN strain-mediating interlayers to inhibit thermal-induced cracking and wafer-bowing, and using a SiN x interlayer to reduce threading dislocation densities in the active region of the MQW structure. MQWs with high IQE approaching 60% have been demonstrated. Atomic resolution electron microscopy and EELS analysis have been used to study the nature of the important interface between the Si(111) substrate and the AlN nucleation layer. We demonstrate an amorphous SiN x interlayer at the interface about 2nm wide, which does not, however, prevent good epitaxy of the AlN on the Si(111) substrate. Copyright © 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Turn-off failure mechanism in large area IGCTs

The destruction mechanism in large area IGCTs (Integrated Gate Commutated Thyristors) under inductive switching conditions is analyzed in detail. The three-dimensional nature of the turn-off process in a 91mm diameter wafer is simulated with a two-dimensional representation. Simulation results show that the final destruction is caused by the uneven dynamic avalanche current distribution across the wafer. © 2011 IEEE.

A simple combinatorial method aiding research on single-walled carbon nanotube growth on substrates

Establishing fabrication methods of carbon nanotubes (CNTs) is essential to realize many applications expected for CNTs. Catalytic growth of CNTs on substrates by chemical vapor deposition (CVD) is promising for direct fabrication of CNT devices, and catalyst nanoparticles play a crucial role in such growth. We have developed a simple method called "combinatorial masked deposition (CMD)", in which catalyst particles of a given series of sizes and compositions are formed on a single substrate by annealing gradient catalyst layers formed by sputtering through a mask. CMD enables preparation of hundreds of catalysts on a wafer, growth of single-walled CNTs (SWCNTs), and evaluation of SWCNT diameter distributions by automated Raman mapping in a single day. CMD helps determinations of the CVD and catalyst windows realizing millimeter-tall SWCNT forest growth in 10 min, and of growth curves for a series of catalysts in a single measurement when combined with realtime monitoring. A catalyst library prepared using CMD yields various CNTs, ranging from individuals, networks, spikes, and to forests of both SWCNTs and multi-walled CNTs, and thus can be used to efficiently evaluate self-organized CNT field emitters, for example. The CMD method is simple yet effective for research of CNT growth methods. © 2010 The Japan Society of Applied Physics.

Highly chiral-selective growth of single-walled carbon nanotubes with a simple monometallic Co catalyst

We report on the growth of single-walled carbon nanotubes from a monometallic Co catalyst on an oxidized Si wafer support by the most simple growth recipe (vacuum annealing, growth by undiluted C 2H 2). Nevertheless, multiwavelength Raman spectroscopy and transmission electron spectroscopy show a remarkable selectivity for chiral indices and thus, e.g., high abundance with a single chirality representing 58% of all semiconducting tubes. In situ x-ray photoelectron spectroscopy monitors the catalyst chemistry during carbon nanotube growth and shows interfacial Co-Si interactions that may help to stabilize the nanoparticle/nanotube diameter. We outline a two-mechanism model explaining the selective growth. © 2012 American Physical Society.

Controlled growth orientation of carbon nanotube pillars by catalyst patterning in microtrenches

We present a novel method for controlling the growth orientation of individual carbon nanotube (CNT) microstructures on a silicon wafer substrate. Our method controls the CNT forest orientation by patterning the catalyst layer used in the CNTs growth on slanted KOH edges. The overlap of catalyst area on the horizontal bottom and sloped sidewall surfaces of the KOH-etched substrate enables precise variation of the growth direction. These inclined structures can profit from the outstanding mechanical, electrical, thermal, and optical properties of CNTs and can therefore improve the performance of several MEMS devices. Inclined CNT microstructures could for instance be used as cantilever springs in probe card arrays, as tips in dip-pen lithography, and as sensing element in advanced transducers. ©2009 IEEE.

A single FBAR-based temperature and pressure sensors

A novel temperature and pressure sensor based on a single film bulk acoustic resonator (FBAR) is designed. This FBAR support two resonant modes, which response opposite to the change of temperature. By sealed the back cavity of a back-trench membrane type FBAR with silicon wafer, an on-chip single FBAR sensor suitable for measuring temperature and pressure simultaneously is proposed. For unsealed device, the experimental results show that the first resonant mode has a temperature coefficient of frequency (TCF) of 69.5ppm/K, and the TCF of the second mode is -8.1ppm/K. After sealed the back trench, it can be used as a pressure sensor, the pressure coefficient of frequency (PCF) for the two resonant mode is -17.4ppm/kPa and -6.1 ppm/kPa respectively, both of them being more sensitive than other existing pressure sensors. © 2013 Trans Tech Publications Ltd, Switzerland.

Prospects of III-nitride optoelectronics grown on Si.

The use of III-nitride-based light-emitting diodes (LEDs) is now widespread in applications such as indicator lamps, display panels, backlighting for liquid-crystal display TVs and computer screens, traffic lights, etc. To meet the huge market demand and lower the manufacturing cost, the LED industry is moving fast from 2 inch to 4 inch and recently to 6 inch wafer sizes. Although Al2O3 (sapphire) and SiC remain the dominant substrate materials for the epitaxy of nitride LEDs, the use of large Si substrates attracts great interest because Si wafers are readily available in large diameters at low cost. In addition, such wafers are compatible with existing processing lines for 6 inch and larger wafers commonly used in the electronics industry. During the last decade, much exciting progress has been achieved in improving the performance of GaN-on-Si devices. In this contribution, the status and prospects of III-nitride optoelectronics grown on Si substrates are reviewed. The issues involved in the growth of GaN-based LED structures on Si and possible solutions are outlined, together with a brief introduction to some novel in situ and ex situ monitoring/characterization tools, which are especially useful for the growth of GaN-on-Si structures.

Growth kinetics and uniform scaling-up of graphene synthesis

Chemical vapor deposition on copper is the most widely used method to synthesize graphene at large scale. However, the clear understanding of the fundamental mechanisms that govern this synthesis is lacking. Using a vertical-flow, cold-wall reactor with short gas residence time we observe the early growths to study the kinetics of chemical vapor deposition of graphene on copper foils and demonstrate uniform synthesis at wafer scale. Our results indicate that the growth is limited by the catalytic dissociative dehydrogenation on the surface and copper sublimation hinders the graphene growth. We report an activation energy of 3.1 eV for ethylene-based graphene synthesis. © The Electrochemical Society.

Low-cost high-efficiency GaN LED on large-area si substrate

The use of large size Si substrates for epitaxy of nitride light emitting diode (LED) structures has attracted great interest because Si wafers are readily available in large diameter at low cost. In addition, such wafers are compatible with existing processing lines for the 6-inch and larger wafer sizes commonly used in the electronics industry. With the development of various methods to avoid wafer cracking and reduce the defect density, the performance of GaN-based LED and electronic devices has been greatly improved. In this paper, we review our methods of growing crack-free InGaN-GaN multiple quantum well (MQW) LED structures of high crystalline quality on Si(111) substrates. The performance of processed LED devices and its dependence on the threading dislocation density were studied. Full wafer-level LED processing using a conventional 6-inch III-V processing line is also presented, demonstrating the great advantage of using large-size Si substrates for mass production of GaN LED devices.

Analytical formulation of modal frequency split in the elliptical mode of SCS micromechanical disk resonators

This paper presents an analytical formulation of frequency splitting observed in the elliptical modes of single crystal silicon (SCS) micromechanical disk resonators. Taking the anisotropic elasticity of SCS into account, new formulae for computing modal mass and modal stiffness are first derived for accurate prediction of the modal frequency. The derived results are in good agreement with finite element simulation, showing a factor of 10 improvement in the prediction accuracy as compared to using the formula for the isotropic case. In addition, the analysis successfully explains the effect of anisotropy on the modal frequency splitting of primary elliptical modes, for which the maximum modal displacement is aligned with the directions of maximum (1 1 0) and minimum (1 0 0) elasticity respectively on a (1 0 0) SCS wafer. The measured frequency splitting of other degenerate modes is due to the manufacturing imperfections. © 2014 IOP Publishing Ltd.

Parameters influencing the maximum controllable current in gate commutated thyristors

The model of interconnected numerical device segments can give a prediction on the dynamic performance of large area full wafer devices such as the Gate Commutated Thyristors (GCTs) and can be used as an optimisation tool for designing GCTs. In this study the authors evaluate the relative importance of the shallow p-base thickness, its peak concentration, the depth of the p-base and the buffer peak concentration. © The Institution of Engineering and Technology 2014.

Directional emission InP/GaInAsP square-resonator microlasers

InP/GaInAsP square-resonator microlasers with an output waveguide connected to the midpoint of one side of the square are fabricated by standard photolithography and inductively-coupled-plasma etching technique. For a 20-mu m-side square microlaser with a 2-mu m-wide output waveguide, cw threshold current is 11 mA at room temperature, and the highest mode Q factor is 1.0 X 10(4) measured from the mode linewidth at the injection current of 10 mA. Multimode oscillation is observed with the lasing mode wavelength 1546 nm and the side-mode suppression ratio of 20 dB at the injection current of 15 mA. (C) 2008 Optical Society of America