Optimal incentive timing strategies for product marketing on social networks

We consider the problem of devising incentive strategies for viral marketing of a product. In particular, we assume that the seller can influence penetration of the product by offering two incentive programs: a) direct incentives to potential buyers (influence) and b) referral rewards for customers who influence potential buyers to make the purchase (exploit connections). The problem is to determine the optimal timing of these programs over a finite time horizon. In contrast to algorithmic perspective popular in the literature, we take a mean-field approach and formulate the problem as a continuous-time deterministic optimal control problem. We show that the optimal strategy for the seller has a simple structure and can take both forms, namely, influence-and-exploit and exploit-and-influence. We also show that in some cases it may optimal for the seller to deploy incentive programs mostly for low degree nodes. We support our theoretical results through numerical studies and provide practical insights by analyzing various scenarios.

Delay optimal scheduling of a discrete-time batch service queue for point-to-point channel code rate selection

We consider the problem of characterizing the minimum average delay, or equivalently the minimum average queue length, of message symbols randomly arriving to the transmitter queue of a point-to-point link which dynamically selects a (n, k) block code from a given collection. The system is modeled by a discrete time queue with an IID batch arrival process and batch service. We obtain a lower bound on the minimum average queue length, which is the optimal value for a linear program, using only the mean (λ) and variance (σ2) of the batch arrivals. For a finite collection of (n, k) codes the minimum achievable average queue length is shown to be Θ(1/ε) as ε ↓ 0 where ε is the difference between the maximum code rate and λ. We obtain a sufficient condition for code rate selection policies to achieve this optimal growth rate. A simple family of policies that use only one block code each as well as two other heuristic policies are shown to be weakly optimal in the sense of achieving the 1/ε growth rate. An appropriate selection from the family of policies that use only one block code each is also shown to achieve the optimal coefficient σ2/2 of the 1/ε growth rate. We compare the performance of the heuristic policies with the minimum achievable average queue length and the lower bound numerically. For a countable collection of (n, k) codes, the optimal average queue length is shown to be Ω(1/ε). We illustrate the selectivity among policies of the growth rate optimality criterion for both finite and countable collections of (n, k) block codes.

Using Relationships for Matching Textual Domain Models with Existing Code

We address the task of mapping a given textual domain model (e.g., an industry-standard reference model) for a given domain (e.g., ERP), with the source code of an independently developed application in the same domain. This has applications in improving the understandability of an existing application, migrating it to a more flexible architecture, or integrating it with other related applications. We use the vector-space model to abstractly represent domain model elements as well as source-code artifacts. The key novelty in our approach is to leverage the relationships between source-code artifacts in a principled way to improve the mapping process. We describe experiments wherein we apply our approach to the task of matching two real, open-source applications to corresponding industry-standard domain models. We demonstrate the overall usefulness of our approach, as well as the role of our propagation techniques in improving the precision and recall of the mapping task.

Selection and thermodynamic analysis of a turbocharger for a producer gas-fuelled multi-cylinder engine

The current work addresses the use of producer gas, a bio-derived gaseous alternative fuel, in engines designed for natural gas, derived from diesel engine frames. Impact of the use of producer gas on the general engine performance with specific focus on turbo-charging is addressed. The operation of a particular engine frame with diesel, natural gas and producer gas indicates that the peak load achieved is highest with diesel fuel (in compression ignition mode) followed by natural gas and producer gas (both in spark ignite mode). Detailed analysis of the engine power de-rating on fuelling with natural gas and producer gas indicates that the change in compression ratio (migration from compression to spark ignited mode), difference in mixture calorific value and turbocharger mismatch are the primary contributing factors. The largest de-rating occurs due to turbocharger mismatch. Turbocharger selection and optimization is identified as the strategy to recover the non-thermodynamic power loss, identified as the recovery potential (the loss due to mixture calorific value and turbocharger mismatch) on operating the engine with a fuel different from the base fuel. A turbocharged after-cooled six cylinder, 5.9 l, 90 kWe (diesel rating) engine (12.2 bar BMEP) is available commercially as a naturally aspirated natural gas engine delivering a peak load of 44.0 kWe (6.0 bar BMEP). The engine delivers a load of 27.3 kWe with producer gas under naturally aspirated mode. On charge boosting the engine with a turbocharger similar in configuration to the diesel engine turbocharger, the peak load delivered with producer gas is 36 kWe (4.8 bar BMEP) indicating a de-rating of about 60% over the baseline diesel mode. Estimation of knock limited peak load for producer gas-fuelled operation on the engine frame using a Wiebe function-based zero-dimensional code indicates a knock limited peak load of 76 kWe, indicating the potential to recover about 40 kWe. As a part of the recovery strategy, optimizing the ignition timing for maximum brake torque based on both spark sweep tests and established combustion descriptors and engine-turbocharger matching for producer gas-fuelled operation resulted in a knock limited peak load of 72.8 kWe (9.9 bar BMEP) at a compressor pressure ratio of 2.30. The de-rating of about 17.0 kWe compared to diesel rating is attributed to the reduction in compression ratio. With load recovery, the specific biomass consumption reduces from 1.2 kg/kWh to 1.0 kg/kWh, an improvement of over 16% while the engine thermal efficiency increases from 28% to 32%. The thermodynamic analysis of the compressor and the turbine indicates an isentropic efficiency of 74.5% and 73%, respectively.

Generating Efficient Data Movement Code for Heterogeneous Architectures with Distributed-Memory

Programming for parallel architectures that do not have a shared address space is extremely difficult due to the need for explicit communication between memories of different compute devices. A heterogeneous system with CPUs and multiple GPUs, or a distributed-memory cluster are examples of such systems. Past works that try to automate data movement for distributed-memory architectures can lead to excessive redundant communication. In this paper, we propose an automatic data movement scheme that minimizes the volume of communication between compute devices in heterogeneous and distributed-memory systems. We show that by partitioning data dependences in a particular non-trivial way, one can generate data movement code that results in the minimum volume for a vast majority of cases. The techniques are applicable to any sequence of affine loop nests and works on top of any choice of loop transformations, parallelization, and computation placement. The data movement code generated minimizes the volume of communication for a particular configuration of these. We use a combination of powerful static analyses relying on the polyhedral compiler framework and lightweight runtime routines they generate, to build a source-to-source transformation tool that automatically generates communication code. We demonstrate that the tool is scalable and leads to substantial gains in efficiency. On a heterogeneous system, the communication volume is reduced by a factor of 11X to 83X over state-of-the-art, translating into a mean execution time speedup of 1.53X. On a distributed-memory cluster, our scheme reduces the communication volume by a factor of 1.4X to 63.5X over state-of-the-art, resulting in a mean speedup of 1.55X. In addition, our scheme yields a mean speedup of 2.19X over hand-optimized UPC codes.

Depression biased non-Hebbian spike-timing-dependent synaptic plasticity in the rat subiculum

The subiculum is a structure that forms a bridge between the hippocampus and the entorhinal cortex (EC), and plays a major role in the memory consolidation process. Here, we demonstrate spike-timing-dependent plasticity (STDP) at the proximal excitatory inputs on the subicular pyramidal neurons of juvenile rat. Causal (positive) pairing of a single EPSP with a single back-propagating action potential (bAP) after a time interval of 10 ms (+10 ms) failed to induce plasticity. However, increasing the number of bAPs in a burst to three, at two different frequencies of 50 Hz (bAP burst) and 150 Hz, induced long-term depression (LTD) after a time interval of +10 ms in both the regular-firing (RF), and the weak burst firing (WBF) neurons. The LTD amplitude decreased with increasing time interval between the EPSP and the bAP burst. Reversing the order of the pairing of the EPSP and the bAP burst induced LTP at a time interval of -10 ms. This finding is in contrast with reports at other synapses, wherein prebefore postsynaptic (causal) pairing induced LTP and vice versa. Our results reaffirm the earlier observations that the relative timing of the pre- and postsynaptic activities can lead to multiple types of plasticity profiles. The induction of timing-dependent LTD (t-LTD) was dependent on postsynaptic calcium change via NMDA receptors in the WBF neurons, while it was independent of postsynaptic calcium change, but required active L-type calcium channels in the RF neurons. Thus the mechanism of synaptic plasticity may vary within a hippocampal subfield depending on the postsynaptic neuron involved. This study also reports a novel mechanism of LTD induction, where L-type calcium channels are involved in a presynaptically induced synaptic plasticity. The findings may have strong implications in the memory consolidation process owing to the central role of the subiculum and LTD in this process.

LDPC Code Designs Based on root I Matrices

LDPC codes can be constructed by tiling permutation matrices that belong to the square root of identity type and similar algebraic structures. We investigate into the properties of such codes. We also present code structures that are amenable for efficient encoding.

Timing Recovery Algorithms and Architectures for 2-D Magnetic Recording Systems

We investigate the problem of timing recovery for 2-D magnetic recording (TDMR) channels. We develop a timing error model for TDMR channel considering the phase and frequency offsets with noise. We propose a 2-D data-aided phase-locked loop (PLL) architecture for tracking variations in the position and movement of the read head in the down-track and cross-track directions and analyze the convergence of the algorithm under non-separable timing errors. We further develop a 2-D interpolation-based timing recovery scheme that works in conjunction with the 2-D PLL. We quantify the efficiency of our proposed algorithms by simulations over a 2-D magnetic recording channel with timing errors.

An Optimizing Code Generator for a Class of Lattice-Boltzmann Computations

The Lattice-Boltzmann method (LBM), a promising new particle-based simulation technique for complex and multiscale fluid flows, has seen tremendous adoption in recent years in computational fluid dynamics. Even with a state-of-the-art LBM solver such as Palabos, a user has to still manually write the program using library-supplied primitives. We propose an automated code generator for a class of LBM computations with the objective to achieve high performance on modern architectures. Few studies have looked at time tiling for LBM codes. We exploit a key similarity between stencils and LBM to enable polyhedral optimizations and in turn time tiling for LBM. We also characterize the performance of LBM with the Roofline performance model. Experimental results for standard LBM simulations like Lid Driven Cavity, Flow Past Cylinder, and Poiseuille Flow show that our scheme consistently outperforms Palabos-on average by up to 3x while running on 16 cores of an Intel Xeon (Sandybridge). We also obtain an improvement of 2.47x on the SPEC LBM benchmark.

Timing Calculations for a General N-Level Dodecagonal Space Vector Structure Using Only Reference Phase Voltages

Multilevel inverters with dodecagonal (12-sided polygon) voltage space vector (SV) structures have advantages like extension of linear modulation range, elimination of fifth and seventh harmonics in phase voltages and currents for the full modulation range including extreme 12-step operation, reduced device voltage ratings, lesser dv/dt stresses on devices and motor phase windings resulting in lower EMI/EMC problems, and lower switching frequency-making it more suitable for high-power drive applications. This paper proposes a simple method to obtain pulsewidth modulation (PWM) timings for a dodecagonal voltage SV structure using only sampled reference voltages. In addition to this, a carrier-based method for obtaining the PWM timings for a general N-level dodecagonal structure is proposed in this paper for the first time. The algorithm outputs the triangle information and the PWM timing values which can be set as the compare values for any carrier-based hardware PWM module to obtain SV PWM like switching sequences. The proposed method eliminates the need for angle estimation, computation of modulation indices, and iterative search algorithms that are typical in multilevel dodecagonal SV systems. The proposed PWM scheme was implemented on a five-level dodecagonal SV structure. Exhaustive simulation and experimental results for steady-state and transient conditions are presented to validate the proposed method.

Correct biological timing in Arabidopsis requires multiple light-signaling pathways.

Circadian oscillators provide rhythmic temporal cues for a range of biological processes in plants and animals, enabling anticipation of the day/night cycle and enhancing fitness-associated traits. We have used engineering models to understand the control principles of a plant's response to seasonal variation. We show that the seasonal changes in the timing of circadian outputs require light regulation via feed-forward loops, combining rapid light-signaling pathways with entrained circadian oscillators. Linear time-invariant models of circadian rhythms were computed for 3,503 circadian-regulated genes and for the concentration of cytosolic-free calcium to quantify the magnitude and timing of regulation by circadian oscillators and light-signaling pathways. Bioinformatic and experimental analysis show that rapid light-induced regulation of circadian outputs is associated with seasonal rephasing of the output rhythm. We identify that external coincidence is required for rephasing of multiple output rhythms, and is therefore important in general phase control in addition to specific photoperiod-dependent processes such as flowering and hypocotyl elongation. Our findings uncover a fundamental design principle of circadian regulation, and identify the importance of rapid light-signaling pathways in temporal control.

Semi-analytic slope delay model for CMOS switch-level timing verification

A novel slope delay model for CMOS switch-level timing verification is presented. It differs from conventional methods in being semianalytic in character. The model assumes that all input waveforms are trapezoidal in overall shape, but that they vary in their slope. This simplification is quite reasonable and does not seriously affect precision, but it facilitates rapid solution. The model divides the stages in a switch-level circuit into two types. One corresponds to the logic gates, and the other corresponds to logic gates with pass transistors connected to their outputs. Semianalytic modeling for both cases is discussed.

Switch-level timing verification for CMOS circuits. A semianalytic approach

The paper describes a semianalytic slope delay model for CMOS switch-level timing verification. It is characterised by classification of the effects of the input slope, internal size and load capacitance of a logic gate on delay time, and then the use of a series of carefully chosen analytic functions to estimate delay times under different circumstances. In the field of VLSI analysis, this model achieves improvements in speed and accuracy compared with conventional approaches to transistor-level and switch-level simulation.

Hierarchical approach to timing verification in CMOS VLSI design

This paper describes a novel hierarchical approach to timing verification. Four types of relationship existing among signal paths are distinguished, based on a classification of the degree of interdependency in the circuit. In this way, irrelevant path delays can be excluded through consideration of the interaction between critical paths and others. Furthermore, under suitable conditions, bounded delay values for large hierarchical systems can be deduced using bounded delays determined for their constituent cells. Finally, we discuss the impact on design strategy of the hierarchical delay model presented in this paper.