Sistema de armazenamento de energia com base em baterias e no ondulador de tensão trifásico

Dissertação para obtenção do grau de Mestre em Engenharia Electrotécnica Ramo de Automação e Eletrotécnica Ramo de Automação e Eletrónica Industrial

MATLAB/Simulink simulation and C2000 code generation model for a grid-interactive 3-phase 4-wire inverter

This work is a MATLAB/Simulink model of a controller for a three-phase, four-wire, grid-interactive inverter. The model provides capacity for simulating the performance of power electroinic hardware, as well as code generation for an embedded controller. The implemented hardware topology is a three-leg bridge with a neutral connection to the centre-tap of the DC bus. An LQR-based current controller and MAF-based phase detector are implemented. The model is configured for code generation for a Texas Instruments TMS320F28335 Digital Signal Processor (DSP).

A five level inverter scheme with common mode volatge elimination by cascading conventional two level and three level NPC inverters for an induction motor drive

Common-mode voltage generated by the PWM inverter causes shaft voltage, bearing current and ground leakage current in induction motor drive system, resulting in an early motor failure. This paper presents a common-mode elimination scheme for a five-level inverter with reduced power circuit complexity. The proposed scheme is realised by cascading conventional two-level and conventional NPC three-level inverters in conjunction with an open-end winding three-phase induction motor drive and the common-mode voltage (CMV) elimination is achieved by using only switching states that result in zero CMV, for the entire modulation range.

Common-mode voltage eliminated three-level inverter using a three-level flying-capacitor inverter and cascaded H-bridge

This paper proposes a new 3 level common mode voltage eliminated inverter using an inverter structure formed by cascading a H-Bridge with a three-level flying capacitor inverter. The three phase space vector polygon formed by this configuration and the polygon formed by the common-mode eliminated states have been discussed. The entire system is simulated in Simulink and the results are experimentally verified. This system has an advantage that if one of devices in the H-Bridge fails, the system can still be operated as a normal 3 level inverter mode at full power. This inverter has many advantages like use of single DC-supply, making it possible for a back to back grid-tied converter application, improved reliability etc.

A Three-Level Common-Mode Voltage Eliminated Inverter With Single DC Supply Using Flying Capacitor Inverter and Cascaded H-Bridge

A three-level common-mode voltage eliminated inverter with single dc supply using flying capacitor inverter and cascaded H-bridge has been proposed in this paper. The three phase space vector polygon formed by this configuration and the polygon formed by the common-mode eliminated states have been discussed. The entire system is simulated in Simulink and the results are experimentally verified. This system has an advantage that if one of devices in the H-bridge fails, the system can still be operated as a normal three-level inverter at full power. This inverter has many other advantages like use of single dc supply, making it possible for a back-to-back grid-tied converter application, improved reliability, etc.

A 5th and 7th Order Harmonic Suppression Scheme for Open-end Winding Asymmetrical Six-phase IM Drive Using Capacitor-fed Inverter

Voltage source inverter (VSI) fed six-phase induction motor drives have high 6n +/- 1; n = odd order harmonic currents, due to absence of back emf for these currents. To suppress these harmonic currents, either bulky inductive harmonic filters or complex pulse width modulation (PWM) techniques have to be used. This paper proposes a simple harmonic elimination scheme using capacitor fed inverters, for an asymmetrical six-phase induction motor VSI fed drive. Two three phase inverters fed from a single capacitor is used on the open-end side of the motor, to suppress 6n +/- 1; n = odd order harmonics. A PWM scheme that can suppress the harmonics, as well as balance the capacitor voltage is also proposed. The capacitor fed inverters are switched so that the fundamental voltage is not affected. The proposed scheme is verified using MATLAB Simulink simulation at different speeds. The effectiveness of the scheme is demonstrated by comparing the results with those obtained by disabling the capacitor fed inverters. Experimental results are also provided to validate the functionality of the proposed controller.

A comparative study of MPPT strategies and a novel singlephase integrated buck-boost inverter for small wind energy conversion systems

This paper presents the analysis of some usual MPPT (Maximum Power Point Tracking) strategies intended for small wind energy conversion (up to 1kW) based on permanent magnet synchronous generators (PMSG), considering the stand-alone application for a novel buck-boost integrated inverter. Each MPPT method is analytically introduced and then it is simulated using MatLab/Simulink considering standard conditions of wind and also commercially available turbines and generators. The extracted power in each case is compared with the maximum available power, so the tracking factor is calculated for each method. Thus, the focus is on the application to improve the efficiency of stand-alone wind energy conversion systems (WECS) with battery chargers and AC load supplied by inverter. Therefore, for this purpose a novel single phase buck-boost integrated inverter is introduced. Finally, the main experimental results for the introduced inverter are presented. © 2011 IEEE.

A single-phase single-stage buck-boost inverter intended for low power alternative energy conversion systems: Analysis, design and experimentation

This paper presents the operational analysis of the single-phase integrated buck-boost inverter. This topology is able to convert the DC input voltage into AC voltage with a high static gain, low harmonic content and acceptable efficiency, all in one single-stage. Main functionality aspects are explained, design procedure, system modeling and control, and also component requirements are detailed. Main simulation results are included, and two prototypes were implemented and experimentally tested, where its results are compared with those corresponding to similar topologies available in literature. © 2012 IEEE.

Characteristic analysis for multisampled digital implementation of fixed-switching-frequency closed-loop modulation of voltage-source inverter

In this paper, a fixed-switching-frequency closed-loop modulation of a voltage-source inverter (VSI), upon the digital implementation of the modulation process, is analyzed and characterized. The sampling frequency of the digital processor is considered as an integer multiple of the modulation switching frequency. An expression for the determination of the modulation design parameter is developed for smooth modulation at a fixed switching frequency. The variation of the sampling frequency, switching frequency, and modulation index has been analyzed for the determination of the switching condition under closed loop. It is shown that the switching condition determined based on the continuous-time analysis of the closed-loop modulation will ensure smooth modulation upon the digital implementation of the modulation process. However, the stability properties need to be tested prior to digital implementation as they get deteriorated at smaller sampling frequencies. The closed-loop modulation index needs to be considered maximum while determining the design parameters for smooth modulation. In particular, a detailed analysis has been carried out by varying the control gain in the sliding-mode control of a two-level VSI. The proposed analysis of the closed-loop modulation of the VSI has been verified for the operation of a distribution static compensator. The theoretical results are validated experimentally on both single- and three-phase systems.

Frequency Domain Characterization Of Sliding Mode Control Of An Inverter Used In DSTATCOM Application

In this paper, the commonly used switching schemes for sliding mode control of power converters is analyzed and designed in the frequency domain. Particular application of a distribution static compensator (DSTATCOM) in voltage control mode is investigated in a power distribution system. Tsypkin's method and describing function is used to obtain the switching conditions for the two-level and three-level voltage source inverters. Magnitude conditions of carrier signals are developed for robust switching of the inverter under carrier-based modulation scheme of sliding mode control. The existence of border collision bifurcation is identified to avoid the complex switching states of the inverter. The load bus voltage of an unbalanced three-phase nonstiff radial distribution system is controlled using the proposed carrier-based design. The results are validated using PSCAD/EMTDC simulation studies and through a scaled laboratory model of DSTATCOM that is developed for experimental verification

Double star chopper cell converter for battery electric vehicles with inter-module SoC balancing and fault tolerant control

A modularized battery system with Double Star Chopper Cell (DSCC) based modular multilevel converter is proposed for a battery operated electric vehicle (EV). A design concept for the modularized battery micro-packs for DSCC is described. Multidimensional pulse width modulation (MD-PWM) with integrated inter-module SoC balancing and fault tolerant control is proposed and explained. The DSCC can be operated either as an inverter to drive the EV motor or as a synchronous rectifier connected to external three phase power supply equipment for charging the battery micro-packs. The methods of operation as inverter and synchronous rectifier with integrated inter-module SoC balancing and fault tolerant control are discussed. The proposed system operation as inverter and synchronous rectifier are verified through simulations and the results are presented.

Microprocessor Based Sinusoidal PWM Inverter by DMA Transfer

The implementation of three-phase sinusoidal pulse-width-modulated inverter control strategy using microprocessor is discussed in this paper. To save CPU time, the DMA technique is used for transferring the switching pattern from memory to the pulse amplifier and isolation circuits of individual thyristors in the inverter bridge. The method of controlling both voltage and frequency is discussed here.

Microprocessor Based Sinusoidal PWM Inverter by DMA Transfer

The implementation of three-phase sinusoidal pulse-width-modulated inverter control strategy using microprocessor is discussed in this paper. To save CPU time, the DMA technique is used for transferring the switching pattern from memory to the pulse amplifier and isolation circuits of individual thyristors in the inverter bridge. The method of controlling both voltage and frequency is discussed here.

A Five-Level Inverter Scheme for a Four-Pole Induction Motor Drive by Feeding the Identical Voltage-Profile Windings From Both Sides

This paper presents a five-level inverter scheme with four two-level inverters for a four-pole induction motor (IM) drive. In a conventional three-phase four-pole IM, there exists two identical voltage-profile winding coil groups per phase around the armature, which are connected in series and spatially apart by two pole pitches. In this paper, these two identical voltage-profile pole-pair winding coils in each phase of the IM are disconnected and fed from four two-level inverters from four sides of the windings with one-fourth dc-link voltage as compared to a conventional five-level neutral-point-clamped inverter. The scheme presented in this paper does not require any special design modification for the induction machine. For this paper, a four-pole IM drive is used, and the scheme can be easily extended to IMs with more than four poles. The proposed scheme is experimentally verified on a four-pole 5-hp IM drive.

A hybrid nine-level inverter for IM drive

This paper proposes a new hybrid nine-level inverter topology for IM drive. The nine-level structure is realized by using two three-phase two-level inverters fed by isolated DC voltage sources and six H-bridges fed by capacitors. The number of switches required in this topology is only 36 where as the conventional nine-level topologies require 48 switches. The voltages across the capacitors, feeding the H-bridges that operate at asymmetric voltages, are effectively balanced by making use of the switching state redundancies. In this topology, the requirement of DC link voltage is only half of the maximum magnitude of the voltage space vector. As the two-level inverters are powered by isolated voltage sources, the circulation of triplen harmonic current in the motor winding is prevented. The proposed drive system is capable of functioning in three-level mode in case of any switch failure in H-bridges. The performance of the proposed topology in the entire modulation range is verified by simulation study and experiment.