Size Effect and Geometrical Effect of Polycrystals and Thin Film/Substrate System in Micro-indentation Test

Micro-indentation test at scales on the order of sub-micron has shown that the measured hardness increases strongly with decreasing indent depth or indent size, which is frequently referred to as the size effect. Simultaneously, at micron or sub-micron scale, the material microstructure size also has an important influence on the measured hardness. This kind of effect, such as the crystal grain size effect, thin film thickness effect, etc., is called the geometrical effect by here. In the present research, in order to investigate the size effect and the geometrical effect, the micro-indentation experiments are carried out respectively for single crystal copper and aluminum, for polycrystal aluminum, as well as for a thin film/substrate system, Ti/Si3N4. The size effect and geometrical effect are displayed experimentally. Moreover, using strain gradient plasticity theory, the size effect and the geometrical effect are simulated. Through comparing experimental results with simulation results, length-scale parameter appearing in the strain gradient theory for different cases is predicted. Furthermore, the size effect and the geometrical effect are interpreted using the geometrically necessary dislocation concept and the discrete dislocation theory. Member Price: $0; Non-Member Price: $25.00

Microscale mechanics for metal thin film delamination along ceramic substrates

The metal thin film delamination along metal/ceramic interface in the case of large scale yielding is studied by employing the strain gradient plasticity theory and the material microscale effects are considered. Two different fracture process models are used in this study to describe the nonlinear delamination phenomena for metal thin films. A set of experiments have been done on the mechanism of copper films delaminating from silica substrates, based on which the peak interface separation stress and the micro-length scale of material, as well as the dislocation-free zone size are predicted.

Ink-jet printing of carbon nanotube thin film transistors

Ink-jet printing is an important process for placing active electronics on plastic substrates. We demonstrate ink-jet printing as a viable method for large area fabrication of carbon nanotube (CNT) thin film transistors (TFTs). We investigate different routes for producing stable CNT solutions ("inks"). These consist of dispersion methods for CNT debundling and the use of different solvents, such as N -methyl-2-pyrrolidone. The resulting printable inks are dispensed by ink-jet onto electrode bearing silicon substrates. The source to drain electrode gap is bridged by percolating networks of CNTs. Despite the presence of metallic CNTs, our devices exhibit field effect behavior, with effective mobility of ∼0.07 cm2 /V s and ON/OFF current ratio of up to 100. This result demonstrates the feasibility of ink-jet printing of nanostructured materials for TFT manufacture. © 2007 American Institute of Physics.

High performance nanocomposite thin film transistors with bilayer carbon nanotube-polythiophene active channel by ink-jet printing

Nanocomposite thin film transistors (TFTs) based on nonpercolating networks of single-walled carbon nanotubes (CNTs) and polythiophene semiconductor [poly [5, 5′ -bis(3-dodecyl-2-thienyl)- 2, 2′ -bithiophene] (PQT-12)] thin film hosts are demonstrated by ink-jet printing. A systematic study on the effect of CNT loading on the transistor performance and channel morphology is conducted. With an appropriate loading of CNTs into the active channel, ink-jet printed composite transistors show an effective hole mobility of 0.23 cm 2 V-1 s-1, which is an enhancement of more than a factor of 7 over ink-jet printed pristine PQT-12 TFTs. In addition, these devices display reasonable on/off current ratio of 105-10 6, low off currents of the order of 10 pA, and a sharp subthreshold slope (<0.8 V dec-1). The work presented here furthers our understanding of the interaction between polythiophene polymers and nonpercolating CNTs, where the CNT density in the bilayer structure substantially influences the morphology and transistor performance of polythiophene. Therefore, optimized loading of ink-jet printed CNTs is crucial to achieve device performance enhancement. High performance ink-jet printed nanocomposite TFTs can present a promising alternative to organic TFTs in printed electronic applications, including displays, sensors, radio-frequency identification (RFID) tags, and disposable electronics. © 2009 American Institute of Physics.

A comparative study of plasma-enhanced chemical vapor gate dielectrics for solution-processed polymer thin-film transistor circuit integration

This paper considers plasma-enhanced chemical vapor deposited (PECVD) silicon nitride (SiNx) and silicon oxide (SiOx) as gate dielectrics for organic thin-film transistors (OTFTs), with solution-processed poly[5, 5′ -bis(3-dodecyl-2-thienyl)-2, 2′ -bithiophene] (PQT-12) as the active semiconductor layer. We examine transistors with SiNx films of varying composition deposited at 300 °C as well as 150 °C for plastic compatibility. The transistors show over 100% (two times) improvement in field-effect mobility as the silicon content in SiNx increases, with mobility (μFE) up to 0.14 cm2 /V s and on/off current ratio (ION / IOFF) of 108. With PECVD SiOx gate dielectric, preliminary devices exhibit a μFE of 0.4 cm2 /V s and ION / IOFF of 108. PQT-12 OTFTs with PECVD SiNx and SiOx gate dielectrics on flexible plastic substrates are also presented. These results demonstrate the viability of using PECVD SiN x and SiOx as gate dielectrics for OTFT circuit integration, where the low temperature and large area deposition capabilities of PECVD films are highly amenable to integration of OTFT circuits targeted for flexible and lightweight applications. © 2008 American Institute of Physics.

Zinc oxide nanostructures and high electron mobility nanocomposite thin film transistors

This paper reports on the synthesis of zinc oxide (ZnO) nanostructures and examines the performance of nanocomposite thin-film transistors (TFTs) fabricated using ZnO dispersed in both n- and p-type polymer host matrices. The ZnO nanostructures considered here comprise nanowires and tetrapods and were synthesized using vapor phase deposition techniques involving the carbothermal reduction of solid-phase zinc-containing compounds. Measurement results of nanocomposite TFTs based on dispersion of ZnO nanorods in an n-type organic semiconductor ([6, 6]-phenyl-C61-butyric acid methyl ester) show electron field-effect mobilities in the range 0.3-0.6 cm2V-1 s-1. representing an approximate enhancement by as much as a factor of 40 from the pristine state. The on/off current ratio of the nanocomposite TFTs approach 106 at saturation with off-currents on the order of 10 pA. The results presented here, although preliminary, show a highly promising enhancement for realization of high-performance solution-processable n-type organic TFTs. © 2008 IEEE.

Formation of composite organic thin film transistors with nanotubes and nanowires

Plastic electronics is a rapidly expanding topic, much of which has been focused on organic semiconductors. However, it is also of interest to find viable ways to integrate nanomaterials, such as silicon nanowires (SiNWs) and carbon nanotubes (CNTs), into this technology. Here, we present methods of fabrication of composite devices incorporating such nanostructured materials into an organic matrix. We investigate the formation of polymer/CNT composites, for which we use the semiconducting polymer poly(3,3‴-dialkyl-quaterthiophene) (PQT). We also report a method of fabricating polymer/SiNW TFTs, whereby sparse arrays of parallel oriented SiNWs are initially prepared on silicon dioxide substrates from forests of as-grown gold-catalysed SiNWs. Subsequent ink-jet printing of PQT on these arrays produces a polymer/SiNW composite film. We also present the electrical characterization of all composite devices. © 2007 Elsevier B.V. All rights reserved.

Assessment of Microscale Test Methods of Peeling and Splitting along Surface of Thin-Film/Substrates

Peel test methods are assessed through being applied to a peeling analysis of the ductile film/ceramic substrate system. Through computing the fracture work of the system using the either beam bend model (BB model) or the general plane analysis model (GPA model), surprisingly, a big difference between both model results is found. Although the BB model can capture the plastic dissipation phenomenon for the ductile film case as the GPA model can, it is much sensitive to the choice of the peeling criterion parameters, and it overestimates the plastic bending effect unable to capture crack tip constraint plasticity. In view of the difficulty of measuring interfacial toughness using peel test method when film is the ductile material, a new test method, split test, is recommended and analyzed using the GPA model. The prediction is applied to a wedge-loaded experiment for Al-alloy double-cantilever beam in literature.

Semi-insulating layer for novel high voltage polysilicon thin film transistors

This work describes the deposition and characterisation of semi-insulating oxygen-doped silicon films for the development of high voltage polycrystalline silicon (poly-Si) circuitry on glass. The performance of a novel poly-Si High Voltage Thin Film Transistor (HVTFT) structure, incorporating a layer of semi-insulating material, has been investigated using a two dimensional device simulator. The semi-insulating layer increases the operating voltage of the HVTFT structure by linearising the potential distribution in the device offset region. A glass compatible semi-insulating layer, suitable for HVTFT applications, has been deposited by the Plasma Enhanced Chemical Vapour Deposition (PECVD) technique from silane (SiH4), nitrous oxide (N2O) and helium (He) gas mixtures. The as-deposited films are furnace annealed at 600°C which is the maximum process temperature. By varying the N2O/SiH4 ratio the conductivity of the annealed films can be accurately controlled up to a maximum of around 10-7 Ω-1cm-1. Helium dilution of the reactant gases improves both film uniformity and reproducibility. Raman analysis shows the as-deposited and annealed films to be completely amorphous. A model for the microstructure of these Semi-Insulating Amorphous Oxygen-Doped Silicon (SIAOS) films is proposed to explain the observed physical and electrical properties.

Multiscale Treatment of Thin-Film Lubrication

A multiscale technique that combines an atomistic description of the interfacial (near) region with a coarse-grained (continuum) description of the far regions of the solid substrates is proposed. The new hybrid technique, which represents an advance over a previously proposed dynamically-constrained hybrid atomistic-coarse-grained treatment (Wu et al.J. Chem. Phys., 120, 6744, 2004), is applied to a two-dimensional model tribological system comprising planar substrates sandwiching a monolayer film. Shear–stress profiles (shear stress versus strain) computed by the new hybrid technique are in excellent agreement with “exact” profiles (i.e. those computed treating the whole system at the atomic scale).

Persistent photoconductivity in Hf-In-Zn-O thin film transistors

Passivated Hf-In-Zn-O (HIZO) thin film transistors suffer from a negative threshold voltage shift under visible light stress due to persistent photoconductivity (PPC). Ionization of oxygen vacancy sites is identified as the origin of the PPC following observations of its temperature- and wavelength-dependence. This is further corroborated by the photoluminescence spectrum of the HIZO. We also show that the gate voltage can control the decay of PPC in the dark, giving rise to a memory action. © 2010 American Institute of Physics.