IMPLEMENTATION OF SIGNAL PROCESSING FUNCTIONS USING 1-BIT SYSTOLIC ARRAYS.

The use of systolic arrays of 1-bit cells to implement a range of important signal processing functions is demonstrated. Two examples, a pipelined multiplier and a pipelined bit-slice transform circuit, are given. This approach has many important implications for silicon technology, and these are outlined.

Hardware elliptic curve cryptographic processor over GF(p)

A novel hardware architecture for elliptic curve cryptography (ECC) over GF(p) is introduced. This can perform the main prime field arithmetic functions needed in these cryptosystems including modular inversion and multiplication. This is based on a new unified modular inversion algorithm that offers considerable improvement over previous ECC techniques that use Fermat's Little Theorem for this operation. The processor described uses a full-word multiplier which requires much fewer clock cycles than previous methods, while still maintaining a competitive critical path delay. The benefits of the approach have been demonstrated by utilizing these techniques to create a field-programmable gate array (FPGA) design. This can perform a 256-bit prime field scalar point multiplication in 3.86 ms, the fastest FPGA time reported to date. The ECC architecture described can also perform four different types of modular inversion, making it suitable for use in many different ECC applications. © 2006 IEEE.

Programmable high-performance IIR filter chip

The paper presents a state-of-the-art commercial demonstrator chip for infinite impulse response (IIR) filtering. The programmable IIR filter chip contains eight multiplier/accumulators that can be configured in one of five different modes to implement up to a 16th-order IIR filter. The multiply-accumulate block is based on a highly regular systolic array architecture and uses a redundant number system to overcome problems of pipelining in the feedback loop. The chip has been designed using the GEC Plessey Semiconductors CLA 78000 series gate array, operates on 16-bit two's complement data and has a clock speed of 30 MHz. Issues such as overflow detection and design for testability have also been addressed and are described.

Low-power DWT-based quasi-averaging algorithm and architecture for epileptic seizure detection

In this paper, we have developed a low-complexity algorithm for epileptic seizure detection with a high degree of accuracy. The algorithm has been designed to be feasibly implementable as battery-powered low-power implantable epileptic seizure detection system or epilepsy prosthesis. This is achieved by utilizing design optimization techniques at different levels of abstraction. Particularly, user-specific critical parameters are identified at the algorithmic level and are explicitly used along with multiplier-less implementations at the architecture level. The system has been tested on neural data obtained from in-vivo animal recordings and has been implemented in 90nm bulk-Si technology. The results show up to 90 % savings in power as compared to prevalent wavelet based seizure detection technique while achieving 97% average detection rate. Copyright 2010 ACM.

An optimal algorithm for low power multiplierless FIR filter design using chebychev criterion

In this paper, we propose a novel finite impulse response (FIR) filter design methodology that reduces the number of operations with a motivation to reduce power consumption and enhance performance. The novelty of our approach lies in the generation of filter coefficients such that they conform to a given low-power architecture, while meeting the given filter specifications. The proposed algorithm is formulated as a mixed integer linear programming problem that minimizes chebychev error and synthesizes coefficients which consist of pre-specified alphabets. The new modified coefficients can be used for low-power VLSI implementation of vector scaling operations such as FIR filtering using computation sharing multiplier (CSHM). Simulations in 0.25um technology show that CSHM FIR filter architecture can result in 55% power and 34% speed improvement compared to carry save multiplier (CSAM) based filters.

High-Speed Fully Homomorphic Encryption Over the Integers

A fully homomorphic encryption (FHE) scheme is envisioned as a key cryptographic tool in building a secure and reliable cloud computing environment, as it allows arbitrary evaluation of a ciphertext without revealing the plaintext. However, existing FHE implementations remain impractical due to very high time and resource costs. To the authors’ knowledge, this paper presents the first hardware implementation of a full encryption primitive for FHE over the integers using FPGA technology. A large-integer multiplier architecture utilising Integer-FFT multiplication is proposed, and a large-integer Barrett modular reduction module is designed incorporating the proposed multiplier. The encryption primitive used in the integer-based FHE scheme is designed employing the proposed multiplier and modular reduction modules. The designs are verified using the Xilinx Virtex-7 FPGA platform. Experimental results show that a speed improvement factor of up to 44 is achievable for the hardware implementation of the FHE encryption scheme when compared to its corresponding software implementation. Moreover, performance analysis shows further speed improvements of the integer-based FHE encryption primitives may still be possible, for example through further optimisations or by targeting an ASIC platform.

High-radix systolic modular multiplication on reconfigurable hardware

The overall aim of the work presented in this paper has been to develop Montgomery modular multiplication architectures suitable for implementation on modern reconfigurable hardware. Accordingly, novel high-radix systolic array Montgomery multiplier designs are presented, as we believe that the inherent regular structure and absence of global interconnect associated with these, make them well-suited for implementation on modern FPGAs. Unlike previous approaches, each processing element (PE) comprises both an adder and a multiplier. The inclusion of a multiplier in the PE means that the need to pre-compute or store any multiples of the operands is avoided. This also allows very high-radix implementations to be realised, further reducing the amount of clock cycles per modular multiplication, while still maintaining a competitive critical delay. For demonstrative purposes, 512-bit and 1024-bit FPGA implementations using radices of 2(8) and 2(16) are presented. The subsequent throughput rates are the fastest reported to date.

Sets of multiplicity and closable multipliers on group algebras

We undertake a detailed study of the sets of multiplicity in a second countable locally compact group G and their operator versions. We establish a symbolic calculus for normal completely bounded maps from the space B(L-2(G)) of bounded linear operators on L-2 (G) into the von Neumann algebra VN(G) of G and use it to show that a closed subset E subset of G is a set of multiplicity if and only if the set E* = {(s,t) is an element of G x G : ts(-1) is an element of E} is a set of operator multiplicity. Analogous results are established for M-1-sets and M-0-sets. We show that the property of being a set of multiplicity is preserved under various operations, including taking direct products, and establish an Inverse Image Theorem for such sets. We characterise the sets of finite width that are also sets of operator multiplicity, and show that every compact operator supported on a set of finite width can be approximated by sums of rank one operators supported on the same set. We show that, if G satisfies a mild approximation condition, pointwise multiplication by a given measurable function psi : G -> C defines a closable multiplier on the reduced C*-algebra G(r)*(G) of G if and only if Schur multiplication by the function N(psi): G x G -> C, given by N(psi)(s, t) = psi(ts(-1)), is a closable operator when viewed as a densely defined linear map on the space of compact operators on L-2(G). Similar results are obtained for multipliers on VN(C).

Effects of peer network interactions on adolescent cannabis use

Purpose
This study capitalises on three waves of longitudinal data from a cohort of 4351 secondary school pupils to examine the effects on individuals’ cannabis use uptake of both peer cannabis use and position within a peer network.

Design/methodology/approach
Both cross-sectional and individual fixed effects models are used to estimate the effect on cannabis use of nominated friends’ cannabis use, of reciprocity and transitivity of nominations across the friendship cluster, and of interactions between these nominated friends. Post hoc analyses parsed the behaviour of reciprocating and non-reciprocating friends.

Findings
Cannabis use varied depending on the stability of friendship network and the degree of reciprocity and interconnectedness within the group. Behavioural influence was strong, but interaction effects were observed between the prevalence of cannabis use among friends, the structure of the friendship group and ego’s proximity to group members. These interactions demonstrate that behavioural influence is more salient in more cohesive groups. When reciprocating and non-reciprocating friends’ mean cannabis use were separated, influence from reciprocating friends was estimated at twice the magnitude of other friends.

Originality/value
While preventing any one individual from using cannabis is likely to have a multiplier effect on classmates, the bonds and interactions between classmates will determine which classmates are affected by this multiplier and the salience of that effect.

Pilot tone reference-less phase conjugator for phase modulated retrodirective antenna applications

This letter presents a simple tracking phased locked loop (PLL) that can be used to track phase-modulated signals and provide a phase-conjugated signal for retrodirective retransmission. The configuration allows the retrodirective antenna to directly track phase-modulated signals with no requirement for a separate continuous wave (CW) pilot tone. The ability to directly track phase-modulated signals is carried out using a 4× multiplier on the tracking PLL reference signal. Practical phase conjugation results are presented for a five-element retrodirective array simultaneously sending and receiving phase-modulated (QPSK) signals. Signals with levels as low as -122 dBm can be phase-conjugated and retransmitted with 30 dBm EIRP.

Optimised Multiplication Architectures for Accelerating Fully Homomorphic Encryption

Large integer multiplication is a major performance bottleneck in fully homomorphic encryption (FHE) schemes over the integers. In this paper two optimised multiplier architectures for large integer multiplication are proposed. The first of these is a low-latency hardware architecture of an integer-FFT multiplier. Secondly, the use of low Hamming weight (LHW) parameters is applied to create a novel hardware architecture for large integer multiplication in integer-based FHE schemes. The proposed architectures are implemented, verified and compared on the Xilinx Virtex-7 FPGA platform. Finally, the proposed implementations are employed to evaluate the large multiplication in the encryption step of FHE over the integers. The analysis shows a speed improvement factor of up to 26.2 for the low-latency design compared to the corresponding original integer-based FHE software implementation. When the proposed LHW architecture is combined with the low-latency integer-FFT accelerator to evaluate a single FHE encryption operation, the performance results show that a speed improvement by a factor of approximately 130 is possible.

Estudo de Monte Carlo da electroluminescência em detectores gasosos

Uma descrição detalhada do processo de electroluminescência é um prérequisito na optimização de detectores gasosos para sistemas de imagiologia, astrofísica, física de altas energias e experiências de eventos raros. Neste trabalho, é apresentada e caracterizada uma nova e versátil plataforma de simulação da emissão de luz durante a deriva de electrões em gases nobres, desenvolvida usando os programas Magboltz e Garfield. Propriedades intrínsecas da electroluminescência em gases nobres são calculadas e apresentadas em função do campo eléctrico aplicado, nomeadamente eficiências, rendimento e flutuações estatísticas associadas. São obtidos resultados em grande concordância com dados experimentais e simulações Monte Carlo anteriores. A plataforma é usada para determinar as condições óptimas de funcionamento de detectores como o NEXT (Neutrino Experiment with a Xenon TPC) e outros baseados nas micro-estruturas GEM (Gas Electron Multiplier) e MHSP (Micro- Hole & Strip Plate).

The notion of space in urban housing markets

O mercado imobiliário tem um papel importante nas economias modernas, tanto a nível macro como a nível micro. Ao nível macro, a construção de habitação representa um sector importante e influente na economia, com efeitos multiplicadores significativos sobre a produção e o emprego. Ao nível micro, uma residência representa o activo mais valioso da maioria dos indivíduos e uma parcela muito relevante da riqueza das famílias. Para estas, o custo e a qualidade das suas habitações influencia directa e indirectamente a sua qualidade de vida. A habitação é por isso mesmo um tema, que avaliado nas suas múltiplas dimensões, se caracteriza por ser bastante complexo, mas também ao mesmo tempo desafiante. De modo a delimitar o objecto de análise do trabalho de investigação, esta tese realça os aspectos de localização e distribuição espacial das habitações urbanas. Será desenvolvido um quadro conceptual e respectiva metodologia para a compreender a estrutura espacial da habitação urbana realçando os três aspectos fundamentais da análise espacial: heterogenidade espacial, dependência espacial e escala espacial. A metodologia, aplicada à área urbana de Aveiro e Ílhavo é baseada numa análise hedónica factorial de preços e na noção não geométrica do espaço. Primeiro, é fixada uma escala territorial e são definidos submercados habitacional. Posteriormente, quer a heterogeneidade quer a dependência espaciais são estudados utilizando métodos econométricos, sem considerar qualquer padrão fixo e conhecido de interações espaciais. Em vez disso, são desenvolvidos novos métodos,tendo como base o modelo hedónico factorial, para inferir sobre os potenciais drivers de difusão espacial no valor de uma habitação. Este modelo, foi aplicado a duas diferentes escalas espaciais, para compreender as preferências dos indivíduos em Aveiro ao escolher os seus locais de residencia, e como estas afectam os preços da habitação. O trabalho empírico, utilizando duas bases de dados de habitação distintas, aplicadas ao mercado de habitação de Aveiro mostram: i) em linha com a literatura, a dificuldade de definir submercados e compreender as inter-relações entre esses mercados; ii) a utilidade de uma abordagem híbrida, combinando análise factorial com regressão; iii) a importância fundamental que o efeito escala espacial desempenha no estudo da heterogeneidade e dos spillovers e, finalmente, iv) uma metodologia inovadora para analisar spillovers sem assumir aprioristicamente uma estrutura espacial específica de difusão espacial. Esta metodologia considera a matriz de pesos espaciais (W) desconhecida e estimatima as interações espaciais dentro e entre submercados habitação.

A low-complexity self-calibrating adaptive quadrature receiver

In this paper digital part of a self-calibrating quadrature-receiver is described, containing a digital calibration-engine. The blind source-separation-based calibration-engine eliminates the RF-impairments in real-time hence improving the receiver's performance without the need for test/pilot tones, trimming or use of power-hungry discrete components. Furthermore, an efficient time-multiplexed calibration-engine architecture is proposed and implemented on an FPGA utilising a reduced-range multiplier structure. The use of reduced-range multipliers results in substantial reduction of area as well as power consumption without a compromise in performance when compared with an efficiently designed general purpose multiplier. The performance of the calibration-engine does not depend on the modulation format or the constellation size of the received signal; hence it can be easily integrated into the digital signal processing paths of any receiver.

An extensible complex fast Fourier transform processor chip for real-time spectrum analysis and measurement

This paper describes in detail the design of a CMOS custom fast Fourier transform (FFT) processor for computing a 256-point complex FFT. The FFT is well-suited for real-time spectrum analysis in instrumentation and measurement applications. The FFT butterfly processor reported here consists of one parallel-parallel multiplier and two adders. It is capable of computing one butterfly computation every 100 ns thus it can compute a 256-point complex FFT in 102.4 μs excluding data input and output processes.