894 resultados para HPC parallel computer architecture queues fault tolerance programmability ADAM


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Relatório do Trabalho Final de Mestrado para obtenção do grau de Mestre em Engenharia de Electrónica e Telecomunicações

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Many-core platforms based on Network-on-Chip (NoC [Benini and De Micheli 2002]) present an emerging technology in the real-time embedded domain. Although the idea to group the applications previously executed on separated single-core devices, and accommodate them on an individual many-core chip offers various options for power savings, cost reductions and contributes to the overall system flexibility, its implementation is a non-trivial task. In this paper we address the issue of application mapping onto a NoCbased many-core platform when considering fundamentals and trends of current many-core operating systems, specifically, we elaborate on a limited migrative application model encompassing a message-passing paradigm as a communication primitive. As the main contribution, we formulate the problem of real-time application mapping, and propose a three-stage process to efficiently solve it. Through analysis it is assured that derived solutions guarantee the fulfilment of posed time constraints regarding worst-case communication latencies, and at the same time provide an environment to perform load balancing for e.g. thermal, energy, fault tolerance or performance reasons.We also propose several constraints regarding the topological structure of the application mapping, as well as the inter- and intra-application communication patterns, which efficiently solve the issues of pessimism and/or intractability when performing the analysis.

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Trabalho Final de Mestrado para obtenção do grau de Mestre em Engenharia Mecânica

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Many-core platforms are an emerging technology in the real-time embedded domain. These devices offer various options for power savings, cost reductions and contribute to the overall system flexibility, however, issues such as unpredictability, scalability and analysis pessimism are serious challenges to their integration into the aforementioned area. The focus of this work is on many-core platforms using a limited migrative model (LMM). LMM is an approach based on the fundamental concepts of the multi-kernel paradigm, which is a promising step towards scalable and predictable many-cores. In this work, we formulate the problem of real-time application mapping on a many-core platform using LMM, and propose a three-stage method to solve it. An extended version of the existing analysis is used to assure that derived mappings (i) guarantee the fulfilment of timing constraints posed on worst-case communication delays of individual applications, and (ii) provide an environment to perform load balancing for e.g. energy/thermal management, fault tolerance and/or performance reasons.

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OCEANS, 2001. MTS/IEEE Conference and Exhibition (Volume:2 )

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The complexity of systems is considered an obstacle to the progress of the IT industry. Autonomic computing is presented as the alternative to cope with the growing complexity. It is a holistic approach, in which the systems are able to configure, heal, optimize, and protect by themselves. Web-based applications are an example of systems where the complexity is high. The number of components, their interoperability, and workload variations are factors that may lead to performance failures or unavailability scenarios. The occurrence of these scenarios affects the revenue and reputation of businesses that rely on these types of applications. In this article, we present a self-healing framework for Web-based applications (SHõWA). SHõWA is composed by several modules, which monitor the application, analyze the data to detect and pinpoint anomalies, and execute recovery actions autonomously. The monitoring is done by a small aspect-oriented programming agent. This agent does not require changes to the application source code and includes adaptive and selective algorithms to regulate the level of monitoring. The anomalies are detected and pinpointed by means of statistical correlation. The data analysis detects changes in the server response time and analyzes if those changes are correlated with the workload or are due to a performance anomaly. In the presence of per- formance anomalies, the data analysis pinpoints the anomaly. Upon the pinpointing of anomalies, SHõWA executes a recovery procedure. We also present a study about the detection and localization of anomalies, the accuracy of the data analysis, and the performance impact induced by SHõWA. Two benchmarking applications, exercised through dynamic workloads, and different types of anomaly were considered in the study. The results reveal that (1) the capacity of SHõWA to detect and pinpoint anomalies while the number of end users affected is low; (2) SHõWA was able to detect anomalies without raising any false alarm; and (3) SHõWA does not induce a significant performance overhead (throughput was affected in less than 1%, and the response time delay was no more than 2 milliseconds).

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Dissertação para obtenção do Grau de Mestre em Engenharia Informática

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Dissertação para obtenção do Grau de Mestre em Engenharia Informática

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Dissertação para obtenção do Grau de Mestre em Engenharia Informática

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Dissertação para obtenção do Grau de Mestre em Engenharia Electrotécnica e de Computadores

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Dissertação para obtenção do Grau de Mestre em Engenharia Informática

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The MAP-i doctoral program of the Universities of Minho, Aveiro and Porto

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Mobile embedded systems, wireless communication, real-time systems, real-time scheduling, communication protocols, cooperation, reliability and fault-tolerance, middleware

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L'objectiu d'aquest projecte es dissenyar i implementar en Java una interfície gràfica que permeti simular l'arquitectura VLIW. Ha d'interactuar amb un simulador ja existent, VEX, i amb l'usuari. VEX permet analitzar, desenvolupar i depurar codi escrit en C sobre un processador VLIW configurable, des dels recursos hardware fíns al comportament de la "caché". L'interfície gràfica desenvolupada es diu JavaVEX. Té el gran avantatge d'evitar la introducció de les comandes de text que necesita VEX perquè son substituïdes per elements. És una eina més intuïtiva, ràpida i eficient. JavaVEX mostra informació sobre el codi C traduït a instruccions VLIW de fins a 4 operacions. També mostra els resultats de les instrucciones VLIW simulades. JavaVEX s'ha incorporat a un LiveCD. Així es pot executar l'aplicació sobre qualsevol ordinador. La finalitat docent de JavaVEX és ser utilitzada en les pràctiques de l'assignatura Arquitectura per a Computadors 2.

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El uso intensivo y prolongado de computadores de altas prestaciones para ejecutar aplicaciones computacionalmente intensivas, sumado al elevado número de elementos que los componen, incrementan drásticamente la probabilidad de ocurrencia de fallos durante su funcionamiento. El objetivo del trabajo es resolver el problema de tolerancia a fallos para redes de interconexión de altas prestaciones, partiendo del diseño de polí­ticas de encaminamiento tolerantes a fallos. Buscamos resolver una determinada cantidad de fallos de enlaces y nodos, considerando sus factores de impacto y probabilidad de aparición. Para ello aprovechamos la redundancia de caminos de comunicación existentes, partiendo desde enfoques de encaminamiento adaptativos capaces de cumplir con las cuatro fases de la tolerancia a fallos: detección del error, contención del daño, recuperación del error, y tratamiento del fallo y continuidad del servicio. La experimentación muestra una degradación de prestaciones menor al 5%. En el futuro, se tratará la pérdida de información en tránsito.