A Comaparison Study of EM and Physical Equivalent Circuit Modeling for MIM CMOS Capacitors

In this Letter a new physical model for metal-insulatormetal CMOS capacitors is presented. In the model the parameters of the circuit are derived from the physical structural details. Physical behaviors due to metal skin effect and inductance have been considered. The model has been confirmed by 3D EM simulator and design rules proposed. The model presented is scalable with capacitor geometry, allowing designers to predict and optimize quality factor. The approach has been verified for MIM CMOS capacitors

Synthesis, Characterisation and Properties of (Ba1-xSrx) (Nd1/2Nb1/2 ) 03 Ceramics for Application as Dielectric Resonators in Microwave Circuits

The (Ba1-x Srx) (Nd1/2, Nb1/2) O3 ceramics have been prepared by the conventional ceramic route for different values of x. Addition of a small amount of CeO2(1 wt%) as a sintering aid increased the density of the samples. The structure and microstructure of the sintered samples are studied by X-ray diffraction and SEM methods. The dielectric properties of the samples are measured in the microwave frequency region as a function of composition. The dielectric constant decreases as x increases. The coefficient of thermal variation of resonant frequency decreases as the Sr content increases and goes to the negative side. The dielectric properties of (Ba1-x Srx) (Nd1/2, Nb1/2) O3 are in the range suitable for application as dielectric resonators in microwave circuits

A Faster 2D Technique for the design of Combinational Digital Circuits Using Genetic Algorithm

Combinational digital circuits can be evolved automatically using Genetic Algorithms (GA). Until recently this technique used linear chromosomes and and one dimensional crossover and mutation operators. In this paper, a new method for representing combinational digital circuits as 2 Dimensional (2D) chromosomes and suitable 2D crossover and mutation techniques has been proposed. By using this method, the convergence speed of GA can be increased significantly compared to the conventional methods. Moreover, the 2D representation and crossover operation provides the designer with better visualization of the evolved circuits. In addition to this, a technique to display automatically the evolved circuits has been developed with the help of MATLAB

An Improved Design of Combinational Digital Circuits with Multiplexers using Genetic Algorithm

This paper presents a new approach to the design of combinational digital circuits with multiplexers using Evolutionary techniques. Genetic Algorithm (GA) is used as the optimization tool. Several circuits are synthesized with this method and compared with two design techniques such as standard implementation of logic functions using multiplexers and implementation using Shannon’s decomposition technique using GA. With the proposed method complexity of the circuit and the associated delay can be reduced significantly

Large-Size AlGaN/GaN HEMT Large-Signal Electrothermal Characterization and Modeling for Wireless Digital Communications

The rapid growth in high data rate communication systems has introduced new high spectral efficient modulation techniques and standards such as LTE-A (long term evolution-advanced) for 4G (4th generation) systems. These techniques have provided a broader bandwidth but introduced high peak-to-average power ratio (PAR) problem at the high power amplifier (HPA) level of the communication system base transceiver station (BTS). To avoid spectral spreading due to high PAR, stringent requirement on linearity is needed which brings the HPA to operate at large back-off power at the expense of power efficiency. Consequently, high power devices are fundamental in HPAs for high linearity and efficiency. Recent development in wide bandgap power devices, in particular AlGaN/GaN HEMT, has offered higher power level with superior linearity-efficiency trade-off in microwaves communication. For cost-effective HPA design to production cycle, rigorous computer aided design (CAD) AlGaN/GaN HEMT models are essential to reflect real response with increasing power level and channel temperature. Therefore, large-size AlGaN/GaN HEMT large-signal electrothermal modeling procedure is proposed. The HEMT structure analysis, characterization, data processing, model extraction and model implementation phases have been covered in this thesis including trapping and self-heating dispersion accounting for nonlinear drain current collapse. The small-signal model is extracted using the 22-element modeling procedure developed in our department. The intrinsic large-signal model is deeply investigated in conjunction with linearity prediction. The accuracy of the nonlinear drain current has been enhanced through several issues such as trapping and self-heating characterization. Also, the HEMT structure thermal profile has been investigated and corresponding thermal resistance has been extracted through thermal simulation and chuck-controlled temperature pulsed I(V) and static DC measurements. Higher-order equivalent thermal model is extracted and implemented in the HEMT large-signal model to accurately estimate instantaneous channel temperature. Moreover, trapping and self-heating transients has been characterized through transient measurements. The obtained time constants are represented by equivalent sub-circuits and integrated in the nonlinear drain current implementation to account for complex communication signals dynamic prediction. The obtained verification of this table-based large-size large-signal electrothermal model implementation has illustrated high accuracy in terms of output power, gain, efficiency and nonlinearity prediction with respect to standard large-signal test signals.

Molecular Beam Epitaxial Growth of III-V Semiconductor Nanostructures on Silicon Substrates

The main focus and concerns of this PhD thesis is the growth of III-V semiconductor nanostructures (Quantum dots (QDs) and quantum dashes) on silicon substrates using molecular beam epitaxy (MBE) technique. The investigation of influence of the major growth parameters on their basic properties (density, geometry, composition, size etc.) and the systematic characterization of their structural and optical properties are the core of the research work. The monolithic integration of III-V optoelectronic devices with silicon electronic circuits could bring enormous prospect for the existing semiconductor technology. Our challenging approach is to combine the superior passive optical properties of silicon with the superior optical emission properties of III-V material by reducing the amount of III-V materials to the very limit of the active region. Different heteroepitaxial integration approaches have been investigated to overcome the materials issues between III-V and Si. However, this include the self-assembled growth of InAs and InGaAs QDs in silicon and GaAx matrices directly on flat silicon substrate, sitecontrolled growth of (GaAs/In0,15Ga0,85As/GaAs) QDs on pre-patterned Si substrate and the direct growth of GaP on Si using migration enhanced epitaxy (MEE) and MBE growth modes. An efficient ex-situ-buffered HF (BHF) and in-situ surface cleaning sequence based on atomic hydrogen (AH) cleaning at 500 °C combined with thermal oxide desorption within a temperature range of 700-900 °C has been established. The removal of oxide desorption was confirmed by semicircular streaky reflection high energy electron diffraction (RHEED) patterns indicating a 2D smooth surface construction prior to the MBE growth. The evolution of size, density and shape of the QDs are ex-situ characterized by atomic-force microscopy (AFM) and transmission electron microscopy (TEM). The InAs QDs density is strongly increased from 108 to 1011 cm-2 at V/III ratios in the range of 15-35 (beam equivalent pressure values). InAs QD formations are not observed at temperatures of 500 °C and above. Growth experiments on (111) substrates show orientation dependent QD formation behaviour. A significant shape and size transition with elongated InAs quantum dots and dashes has been observed on (111) orientation and at higher Indium-growth rate of 0.3 ML/s. The 2D strain mapping derived from high-resolution TEM of InAs QDs embedded in silicon matrix confirmed semi-coherent and fully relaxed QDs embedded in defectfree silicon matrix. The strain relaxation is released by dislocation loops exclusively localized along the InAs/Si interfaces and partial dislocations with stacking faults inside the InAs clusters. The site controlled growth of GaAs/In0,15Ga0,85As/GaAs nanostructures has been demonstrated for the first time with 1 μm spacing and very low nominal deposition thicknesses, directly on pre-patterned Si without the use of SiO2 mask. Thin planar GaP layer was successfully grown through migration enhanced epitaxy (MEE) to initiate a planar GaP wetting layer at the polar/non-polar interface, which work as a virtual GaP substrate, for the GaP-MBE subsequently growth on the GaP-MEE layer with total thickness of 50 nm. The best root mean square (RMS) roughness value was as good as 1.3 nm. However, these results are highly encouraging for the realization of III-V optical devices on silicon for potential applications.

Formal Multilevel Hierarchical Verification of Synchronous MOS Circuits

I have designed and implemented a system for the multilevel verification of synchronous MOS VLSI circuits. The system, called Silica Pithecus, accepts the schematic of an MOS circuit and a specification of the circuit's intended digital behavior. Silica Pithecus determines if the circuit meets its specification. If the circuit fails to meet its specification Silica Pithecus returns to the designer the reason for the failure. Unlike earlier verifiers which modelled primitives (e.g., transistors) as unidirectional digital devices, Silica Pithecus models primitives more realistically. Transistors are modelled as bidirectional devices of varying resistances, and nodes are modelled as capacitors. Silica Pithecus operates hierarchically, interactively, and incrementally. Major contributions of this research include a formal understanding of the relationship between different behavioral descriptions (e.g., signal, boolean, and arithmetic descriptions) of the same device, and a formalization of the relationship between the structure, behavior, and context of device. Given these formal structures my methods find sufficient conditions on the inputs of circuits which guarantee the correct operation of the circuit in the desired descriptive domain. These methods are algorithmic and complete. They also handle complex phenomena such as races and charge sharing. Informal notions such as races and hazards are shown to be derivable from the correctness conditions used by my methods.

Taming Chaotic Circuits

Control algorithms that exploit chaotic behavior can vastly improve the performance of many practical and useful systems. The program Perfect Moment is built around a collection of such techniques. It autonomously explores a dynamical system's behavior, using rules embodying theorems and definitions from nonlinear dynamics to zero in on interesting and useful parameter ranges and state-space regions. It then constructs a reference trajectory based on that information and causes the system to follow it. This program and its results are illustrated with several examples, among them the phase-locked loop, where sections of chaotic attractors are used to increase the capture range of the circuit.

Biologically Plausible Neural Circuits for Realization of Maximum Operations

Object recognition in the visual cortex is based on a hierarchical architecture, in which specialized brain regions along the ventral pathway extract object features of increasing levels of complexity, accompanied by greater invariance in stimulus size, position, and orientation. Recent theoretical studies postulate a non-linear pooling function, such as the maximum (MAX) operation could be fundamental in achieving such invariance. In this paper, we are concerned with neurally plausible mechanisms that may be involved in realizing the MAX operation. Four canonical circuits are proposed, each based on neural mechanisms that have been previously discussed in the context of cortical processing. Through simulations and mathematical analysis, we examine the relative performance and robustness of these mechanisms. We derive experimentally verifiable predictions for each circuit and discuss their respective physiological considerations.

Preliminary Characterisation of Low-Temperature Bonded Copper Interconnects for 3-D Integrated Circuits

Three dimensional (3-D) integrated circuits can be fabricated by bonding previously processed device layers using metal-metal bonds that also serve as layer-to-layer interconnects. Bonded copper interconnects test structures were created by thermocompression bonding and the bond toughness was measured using the four-point test. The effects of bonding temperature, physical bonding and failure mechanisms were investigated. The surface effects on copper surface due to pre-bond clean (with glacial acetic acid) were also looked into. A maximum average bond toughness of approximately 35 J/m² was obtained bonding temperature 300 C.

Numerical comparison between Maxwell stress method and equivalent multipole approach for calculation of the dielectrophoretic force in octupolar cell traps

This work presents detailed numerical calculations of the dielectrophoretic force in octupolar traps designed for single-cell trapping. A trap with eight planar electrodes is studied for spherical and ellipsoidal particles using an indirect implementation of the boundary element method (BEM). Multipolar approximations of orders one to three are compared with the full Maxwell stress tensor (MST) calculation of the electrical force on spherical particles. Ellipsoidal particles are also studied, but in their case only the dipolar approximation is available for comparison with the MST solution. The results show that the full MST calculation is only required in the study of non-spherical particles.

Professionals: L'experiència d'un titulat que desenvolupa la seva activitat professional dissenyant circuits electrònics

Seguint amb l’objectiu que titulats a l’Escola Politècnica Superior expliquin detalls de la seva inserció laboral i del seu perfil professional, en aquest segon número de la revista entrevistem el Sr. Albert Pijuan Vila. En aquest cas no es tracta d’un titulat recent, ja que l’Albert va finalitzar els estudis l’any 1988. Recordem que, si bé al 1988 ja disposàvem de d’actual edifici P-I de l’EPS, l’escola encara estava vinculada a la Universitat Politècnica de Catalunya. El principal interès que ens ha mogut a entrevistar l’Albert ha estat el fet de poder presentar les característiques d’un tipus de lloc de treball que pot ser adient per a alguns dels titulats actuals de l’EPS, especialment d’Enginyeria Tècnica Industrial, especialitat Electrònica Industrial i Enginyeria Tècnica en Informàtica de Sistemes. L’entrevista també vol explorar quins són els tipus de coneixements i les competències que haurien d’adquirir els estudiants per adequar-se millor a aquest tipus de sortida professional

Case based reasoning as an extension of fault dictionary methods for linear electronic analog circuits diagnosis

El test de circuits és una fase del procés de producció que cada vegada pren més importància quan es desenvolupa un nou producte. Les tècniques de test i diagnosi per a circuits digitals han estat desenvolupades i automatitzades amb èxit, mentre que aquest no és encara el cas dels circuits analògics. D'entre tots els mètodes proposats per diagnosticar circuits analògics els més utilitzats són els diccionaris de falles. En aquesta tesi se'n descriuen alguns, tot analitzant-ne els seus avantatges i inconvenients. Durant aquests últims anys, les tècniques d'Intel·ligència Artificial han esdevingut un dels camps de recerca més importants per a la diagnosi de falles. Aquesta tesi desenvolupa dues d'aquestes tècniques per tal de cobrir algunes de les mancances que presenten els diccionaris de falles. La primera proposta es basa en construir un sistema fuzzy com a eina per identificar. Els resultats obtinguts son força bons, ja que s'aconsegueix localitzar la falla en un elevat tant percent dels casos. Per altra banda, el percentatge d'encerts no és prou bo quan a més a més s'intenta esbrinar la desviació. Com que els diccionaris de falles es poden veure com una aproximació simplificada al Raonament Basat en Casos (CBR), la segona proposta fa una extensió dels diccionaris de falles cap a un sistema CBR. El propòsit no és donar una solució general del problema sinó contribuir amb una nova metodologia. Aquesta consisteix en millorar la diagnosis dels diccionaris de falles mitjançant l'addició i l'adaptació dels nous casos per tal d'esdevenir un sistema de Raonament Basat en Casos. Es descriu l'estructura de la base de casos així com les tasques d'extracció, de reutilització, de revisió i de retenció, fent èmfasi al procés d'aprenentatge. En el transcurs del text s'utilitzen diversos circuits per mostrar exemples dels mètodes de test descrits, però en particular el filtre biquadràtic és l'utilitzat per provar les metodologies plantejades, ja que és un dels benchmarks proposats en el context dels circuits analògics. Les falles considerades son paramètriques, permanents, independents i simples, encara que la metodologia pot ser fàcilment extrapolable per a la diagnosi de falles múltiples i catastròfiques. El mètode es centra en el test dels components passius, encara que també es podria extendre per a falles en els actius.