Theory of non-steady state electrical characteristics of metal-insulator-metal structures with schottky barriers and exponentially distributed impurity states

We discuss non-steady state electrical characteristics of a metal-insulator-metal structure. We consider an exponential distribution (in energy) of impurity states in addition to impurity states at a single energy level within the depletion region. We discuss thermal as well as isothermal characteristics and present an expression for the temperature of maximum current (Tm) and a method to calculate the density of exponentially distributed impurity states. We plot the theoretical curves for various sets of parameters and the variation of Tm, and Im (maximum current) with applied potential for various impurity distributions. The present model can explain the available experimental results. Finally we compare the non-steady state characteristics in three cases: (i) impurity states only at a single energy level, (ii) uniform energetic distribution of impurity states, and (iii) exponential energetic distribution of impurity states.

Shared Escovopsis parasites between leaf-cutting and non-leaf-cutting ants in the higher attine fungus-growing ant symbiosis

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

Evidence that a single bioluminescent system is shared by all known bioluminescent fungal lineages

Since the early 20th century, many researchers have attempted to determine how fungi are able to emit light. The first successful experiment was obtained using the classical luciferin-luciferase test that consists of mixing under controlled conditions hot (substrate/luciferin) and cold (enzyme/luciferase) water extracts prepared from bioluminescent fungi. Failures by other researchers to reproduce those experiments using different species of fungi lead to the hypothesis of a non-enzymatic luminescent pathway. Only recently, the involvement of a luciferase in this system was proven, thus confirming its enzymatic nature. Of the 100 000 described species in Kingdom Fungi, only 71 species are known to be luminescent and they are distributed unevenly amongst four distantly related lineages. The question we address is whether the mechanism of bioluminescence is the same in all four evolutionary lineages suggesting a single origin of luminescence in the Fungi, or whether each lineage has a unique mechanism for light emission implying independent origins. We prepared hot and cold extracts of numerous species representing the four bioluminescent fungal lineages and performed cross-reactions (luciferin x luciferase) in all possible combinations using closely related non-luminescent species as controls. All cross-reactions with extracts from luminescent species yielded positive results, independent of lineage, whereas no light was emitted in cross-reactions with extracts from non-luminescent species. These results support the hypothesis that all four lineages of luminescent fungi share the same type of luciferin and luciferase, that there is a single luminescent mechanism in the Fungi, and that fungal luciferin is not a ubiquitous molecule in fungal metabolism.

Superdiffusion in a non-Markovian random walk model with a Gaussian memory profile

Most superdiffusive Non-Markovian random walk models assume that correlations are maintained at all time scales, e. g., fractional Brownian motion, Levy walks, the Elephant walk and Alzheimer walk models. In the latter two models the random walker can always "remember" the initial times near t = 0. Assuming jump size distributions with finite variance, the question naturally arises: is superdiffusion possible if the walker is unable to recall the initial times? We give a conclusive answer to this general question, by studying a non-Markovian model in which the walker's memory of the past is weighted by a Gaussian centered at time t/2, at which time the walker had one half the present age, and with a standard deviation sigma t which grows linearly as the walker ages. For large widths we find that the model behaves similarly to the Elephant model, but for small widths this Gaussian memory profile model behaves like the Alzheimer walk model. We also report that the phenomenon of amnestically induced persistence, known to occur in the Alzheimer walk model, arises in the Gaussian memory profile model. We conclude that memory of the initial times is not a necessary condition for generating (log-periodic) superdiffusion. We show that the phenomenon of amnestically induced persistence extends to the case of a Gaussian memory profile.

Androgen responsive intronic non-coding RNAs

Abstract Background Transcription of large numbers of non-coding RNAs originating from intronic regions of human genes has been recently reported, but mechanisms governing their biosynthesis and biological functions are largely unknown. In this work, we evaluated the existence of a common mechanism of transcription regulation shared by protein-coding mRNAs and intronic RNAs by measuring the effect of androgen on the transcriptional profile of a prostate cancer cell line. Results Using a custom-built cDNA microarray enriched in intronic transcribed sequences, we found 39 intronic non-coding RNAs for which levels were significantly regulated by androgen exposure. Orientation-specific reverse transcription-PCR indicated that 10 of the 13 were transcribed in the antisense direction. These transcripts are long (0.5–5 kb), unspliced and apparently do not code for proteins. Interestingly, we found that the relative levels of androgen-regulated intronic transcripts could be correlated with the levels of the corresponding protein-coding gene (asGAS6 and asDNAJC3) or with the alternative usage of exons (asKDELR2 and asITGA6) in the corresponding protein-coding transcripts. Binding of the androgen receptor to a putative regulatory region upstream from asMYO5A, an androgen-regulated antisense intronic transcript, was confirmed by chromatin immunoprecipitation. Conclusion Altogether, these results indicate that at least a fraction of naturally transcribed intronic non-coding RNAs may be regulated by common physiological signals such as hormones, and further corroborate the notion that the intronic complement of the transcriptome play functional roles in the human gene-expression program.

Non-Markovian stochastic processes and their applications: from anomalous diffusion to time series analysis

This work provides a forward step in the study and comprehension of the relationships between stochastic processes and a certain class of integral-partial differential equation, which can be used in order to model anomalous diffusion and transport in statistical physics. In the first part, we brought the reader through the fundamental notions of probability and stochastic processes, stochastic integration and stochastic differential equations as well. In particular, within the study of H-sssi processes, we focused on fractional Brownian motion (fBm) and its discrete-time increment process, the fractional Gaussian noise (fGn), which provide examples of non-Markovian Gaussian processes. The fGn, together with stationary FARIMA processes, is widely used in the modeling and estimation of long-memory, or long-range dependence (LRD). Time series manifesting long-range dependence, are often observed in nature especially in physics, meteorology, climatology, but also in hydrology, geophysics, economy and many others. We deepely studied LRD, giving many real data examples, providing statistical analysis and introducing parametric methods of estimation. Then, we introduced the theory of fractional integrals and derivatives, which indeed turns out to be very appropriate for studying and modeling systems with long-memory properties. After having introduced the basics concepts, we provided many examples and applications. For instance, we investigated the relaxation equation with distributed order time-fractional derivatives, which describes models characterized by a strong memory component and can be used to model relaxation in complex systems, which deviates from the classical exponential Debye pattern. Then, we focused in the study of generalizations of the standard diffusion equation, by passing through the preliminary study of the fractional forward drift equation. Such generalizations have been obtained by using fractional integrals and derivatives of distributed orders. In order to find a connection between the anomalous diffusion described by these equations and the long-range dependence, we introduced and studied the generalized grey Brownian motion (ggBm), which is actually a parametric class of H-sssi processes, which have indeed marginal probability density function evolving in time according to a partial integro-differential equation of fractional type. The ggBm is of course Non-Markovian. All around the work, we have remarked many times that, starting from a master equation of a probability density function f(x,t), it is always possible to define an equivalence class of stochastic processes with the same marginal density function f(x,t). All these processes provide suitable stochastic models for the starting equation. Studying the ggBm, we just focused on a subclass made up of processes with stationary increments. The ggBm has been defined canonically in the so called grey noise space. However, we have been able to provide a characterization notwithstanding the underline probability space. We also pointed out that that the generalized grey Brownian motion is a direct generalization of a Gaussian process and in particular it generalizes Brownain motion and fractional Brownain motion as well. Finally, we introduced and analyzed a more general class of diffusion type equations related to certain non-Markovian stochastic processes. We started from the forward drift equation, which have been made non-local in time by the introduction of a suitable chosen memory kernel K(t). The resulting non-Markovian equation has been interpreted in a natural way as the evolution equation of the marginal density function of a random time process l(t). We then consider the subordinated process Y(t)=X(l(t)) where X(t) is a Markovian diffusion. The corresponding time-evolution of the marginal density function of Y(t) is governed by a non-Markovian Fokker-Planck equation which involves the same memory kernel K(t). We developed several applications and derived the exact solutions. Moreover, we considered different stochastic models for the given equations, providing path simulations.

Cooperative communication and distributed detection in wireless sensor networks

Recent progress in microelectronic and wireless communications have enabled the development of low cost, low power, multifunctional sensors, which has allowed the birth of new type of networks named wireless sensor networks (WSNs). The main features of such networks are: the nodes can be positioned randomly over a given field with a high density; each node operates both like sensor (for collection of environmental data) as well as transceiver (for transmission of information to the data retrieval); the nodes have limited energy resources. The use of wireless communications and the small size of nodes, make this type of networks suitable for a large number of applications. For example, sensor nodes can be used to monitor a high risk region, as near a volcano; in a hospital they could be used to monitor physical conditions of patients. For each of these possible application scenarios, it is necessary to guarantee a trade-off between energy consumptions and communication reliability. The thesis investigates the use of WSNs in two possible scenarios and for each of them suggests a solution that permits to solve relating problems considering the trade-off introduced. The first scenario considers a network with a high number of nodes deployed in a given geographical area without detailed planning that have to transmit data toward a coordinator node, named sink, that we assume to be located onboard an unmanned aerial vehicle (UAV). This is a practical example of reachback communication, characterized by the high density of nodes that have to transmit data reliably and efficiently towards a far receiver. It is considered that each node transmits a common shared message directly to the receiver onboard the UAV whenever it receives a broadcast message (triggered for example by the vehicle). We assume that the communication channels between the local nodes and the receiver are subject to fading and noise. The receiver onboard the UAV must be able to fuse the weak and noisy signals in a coherent way to receive the data reliably. It is proposed a cooperative diversity concept as an effective solution to the reachback problem. In particular, it is considered a spread spectrum (SS) transmission scheme in conjunction with a fusion center that can exploit cooperative diversity, without requiring stringent synchronization between nodes. The idea consists of simultaneous transmission of the common message among the nodes and a Rake reception at the fusion center. The proposed solution is mainly motivated by two goals: the necessity to have simple nodes (to this aim we move the computational complexity to the receiver onboard the UAV), and the importance to guarantee high levels of energy efficiency of the network, thus increasing the network lifetime. The proposed scheme is analyzed in order to better understand the effectiveness of the approach presented. The performance metrics considered are both the theoretical limit on the maximum amount of data that can be collected by the receiver, as well as the error probability with a given modulation scheme. Since we deal with a WSN, both of these performance are evaluated taking into consideration the energy efficiency of the network. The second scenario considers the use of a chain network for the detection of fires by using nodes that have a double function of sensors and routers. The first one is relative to the monitoring of a temperature parameter that allows to take a local binary decision of target (fire) absent/present. The second one considers that each node receives a decision made by the previous node of the chain, compares this with that deriving by the observation of the phenomenon, and transmits the final result to the next node. The chain ends at the sink node that transmits the received decision to the user. In this network the goals are to limit throughput in each sensor-to-sensor link and minimize probability of error at the last stage of the chain. This is a typical scenario of distributed detection. To obtain good performance it is necessary to define some fusion rules for each node to summarize local observations and decisions of the previous nodes, to get a final decision that it is transmitted to the next node. WSNs have been studied also under a practical point of view, describing both the main characteristics of IEEE802:15:4 standard and two commercial WSN platforms. By using a commercial WSN platform it is realized an agricultural application that has been tested in a six months on-field experimentation.

L'eredità di Aldo Rossi nella Penisola Iberica. La costruzione della città e il progetto contemporaneo

Descrizione, tema e obiettivi della ricerca La ricerca si propone lo studio delle possibili influenze che la teoria di Aldo Rossi ha avuto sulla pratica progettuale nella Penisola Iberica, intende quindi affrontare i caratteri fondamentali della teoria che sta alla base di un metodo progettuale ed in particolar modo porre l'attenzione alle nuove costruzioni quando queste si confrontano con le città storiche. Ha come oggetto principale lo studio dei documenti, saggi e scritti riguardanti il tema della costruzione all'interno delle città storiche. Dallo studio di testi selezionati di Aldo Rossi sulla città si vuole concentrare l'attenzione sull'influenza che tale teoria ha avuto nei progetti della Penisola Iberica, studiare come è stata recepita e trasmessa successivamente, attraverso gli scritti di autori spagnoli e come ha visto un suo concretizzarsi poi nei progetti di nuove costruzioni all'interno delle città storiche. Si intende restringere il campo su un periodo ed un luogo precisi, Spagna e Portogallo a partire dagli anni Settanta, tramite la lettura di un importante evento che ha ufficializzato il contatto dell'architetto italiano con la Penisola Iberica, quale il Seminario di Santiago de Compostela tenutosi nel 1976. Al Seminario parteciparono numerosi architetti che si confrontarono su di un progetto per la città di Santiago e furono invitati personaggi di fama internazionale a tenere lezioni introduttive sul tema di dibattito in merito al progetto e alla città storica. Il Seminario di Santiago si colloca in un periodo storico cruciale per la Penisola Iberica, nel 1974 cade il regime salazarista in Portogallo e nel 1975 cade il regime franchista in Spagna ed è quindi di rilevante importanza capire il legame tra l'architettura e la nuova situazione politica. Dallo studio degli interventi, dei progetti che furono prodotti durante il Seminario, della relazione tra questo evento ed il periodo storico in cui esso va contestualizzato, si intende giungere alla individuazione delle tracce della reale presenza di tale eredità. Presupposti metodologici. Percorso e strumenti di ricerca La ricerca può quindi essere articolata in distinte fasi corrispondenti per lo più ai capitoli in cui si articola la tesi: una prima fase con carattere prevalentemente storica, di ricerca del materiale per poter definire il contesto in cui si sviluppano poi le vicende oggetto della tesi; una seconda fase di impronta teorica, ossia di ricerca bibliografica del materiale e delle testimonianze che provvedono alla definizione della reale presenza di effetti scaturiti dai contatti tra Rossi e la Penisola Iberica, per andare a costruire una eredità ; una terza fase che entra nel merito della composizione attraverso lo studio e la verifica delle prime due parti, tramite l'analisi grafica applicata ad uno specifico esempio architettonico selezionato; una quarta fase dove il punto di vista viene ribaltato e si indaga l'influenza dei luoghi visitati e dei contatti intrattenuti con alcuni personaggi della Penisola Iberica sull'architettura di Rossi, ricercandone i riferimenti. La ricerca è stata condotta attraverso lo studio di alcuni eventi selezionati nel corso degli anni che si sono mostrati significativi per l'indagine, per la risonanza che hanno avuto sulla storia dell'architettura della Penisola. A questo scopo si sono utilizzati principalmente tre strumenti: lo studio dei documenti, le pubblicazioni e le riviste prodotte in Spagna, gli scritti di Aldo Rossi in merito, e la testimonianza diretta attraverso interviste di personaggi chiave. La ricerca ha prodotto un testo suddiviso per capitoli che rispetta l'organizzazione in fasi di lavoro. A seguito di determinate condizioni storiche e politiche, studiate nella ricerca a supporto della tesi espressa, nella Penisola Iberica si è verificato il diffondersi della necessità e del desiderio di guardare e prendere a riferimento l'architettura europea e in particolar modo quella italiana. Il periodo sul quale viene focalizzata l'attenzione ha inizio negli anni Sessanta, gli ultimi prima della caduta delle dittature, scenario dei primi viaggi di Aldo Rossi nella Penisola Iberica. Questi primi contatti pongono le basi per intense e significative relazioni future. Attraverso l'approfondimento e la studio dei materiali relativi all'oggetto della tesi, si è cercato di mettere in luce il contesto culturale, l'attenzione e l'interesse per l'apertura di un dibattito intorno all'architettura, non solo a livello nazionale, ma europeo. Ciò ha evidenziato il desiderio di innescare un meccanismo di discussione e scambio di idee, facendo leva sull'importanza dello sviluppo e ricerca di una base teorica comune che rende coerente i lavori prodotti nel panorama architettonico iberico, seppur ottenendo risultati che si differenziano gli uni dagli altri. E' emerso un forte interesse per il discorso teorico sull'architettura, trasmissibile e comunicabile, che diventa punto di partenza per un metodo progettuale. Ciò ha reso palese una condivisione di intenti e l'assunzione della teoria di Aldo Rossi, acquisita, diffusa e discussa, attraverso la pubblicazione dei suoi saggi, la conoscenza diretta con l'architetto e la sua architettura, conferenze, seminari, come base teorica su cui fondare il proprio sapere architettonico ed il processo metodologico progettuale da applicare di volta in volta negli interventi concreti. Si è giunti così alla definizione di determinati eventi che hanno permesso di entrare nel profondo della questione e di sondare la relazione tra Rossi e la Penisola Iberica, il materiale fornito dallo studio di tali episodi, quali il I SIAC, la diffusione della rivista "2C. Construccion de la Ciudad", la Coleccion Arquitectura y Critica di Gustavo Gili, hanno poi dato impulso per il reperimento di una rete di ulteriori riferimenti. E' stato possibile quindi individuare un gruppo di architetti spagnoli, che si identificano come allievi del maestro Rossi, impegnato per altro in quegli anni nella formazione di una Scuola e di un insegnamento, che non viene recepito tanto nelle forme, piuttosto nei contenuti. I punti su cui si fondano le connessioni tra l'analisi urbana e il progetto architettonico si centrano attorno due temi di base che riprendono la teoria esposta da Rossi nel saggio L'architettura della città : - relazione tra l'area-studio e la città nella sua globalità, - relazione tra la tipologia edificatoria e gli aspetti morfologici. La ricerca presentata ha visto nelle sue successive fasi di approfondimento, come si è detto, lo sviluppo parallelo di più tematiche. Nell'affrontare ciascuna fase è stato necessario, di volta in volta, operare una verifica delle tappe percorse precedentemente, per mantenere costante il filo del discorso col lavoro svolto e ritrovare, durante lo svolgimento stesso della ricerca, gli elementi di connessione tra i diversi episodi analizzati. Tale operazione ha messo in luce talvolta nodi della ricerca rimasti in sospeso che richiedevano un ulteriore approfondimento o talvolta solo una rivisitazione per renderne possibile un più proficuo collegamento con la rete di informazioni accumulate. La ricerca ha percorso strade diverse che corrono parallele, per quanto riguarda il periodo preso in analisi: - i testi sulla storia dell'architettura spagnola e la situazione contestuale agli anni Settanta - il materiale riguardante il I SIAC - le interviste ai partecipanti al I SIAC - le traduzioni di Gustavo Gili nella Coleccion Arquitectura y Critica - la rivista "2C. Construccion de la Ciudad" Esse hanno portato alla luce una notevole quantità di tematiche, attraverso le quali, queste strade vengono ad intrecciarsi e a coincidere, verificando l'una la veridicità dell'altra e rafforzandone il valore delle affermazioni. Esposizione sintetica dei principali contenuti esposti dalla ricerca Andiamo ora a vedere brevemente i contenuti dei singoli capitoli. Nel primo capitolo Anni Settanta. Periodo di transizione per la Penisola Iberica si è cercato di dare un contesto storico agli eventi studiati successivamente, andando ad evidenziare gli elementi chiave che permettono di rintracciare la presenza della predisposizione ad un cambiamento culturale. La fase di passaggio da una condizione di chiusura rispetto alle contaminazioni provenienti dall'esterno, che caratterizza Spagna e Portogallo negli anni Sessanta, lascia il posto ad un graduale abbandono della situazione di isolamento venutasi a creare intorno al Paese a causa del regime dittatoriale, fino a giungere all'apertura e all'interesse nei confronti degli apporti culturali esterni. E' in questo contesto che si gettano le basi per la realizzazione del I Seminario Internazionale di Architettura Contemporanea a Santiago de Compostela, del 1976, diretto da Aldo Rossi e organizzato da César Portela e Salvador Tarragó, di cui tratta il capitolo secondo. Questo è uno degli eventi rintracciati nella storia delle relazioni tra Rossi e la Penisola Iberica, attraverso il quale è stato possibile constatare la presenza di uno scambio culturale e l'importazione in Spagna delle teorie di Aldo Rossi. Organizzato all'indomani della caduta del franchismo, ne conserva una reminescenza formale. Il capitolo è organizzato in tre parti, la prima si occupa della ricostruzione dei momenti salienti del Seminario Proyecto y ciudad historica, dagli interventi di architetti di fama internazionale, quali lo stesso Aldo Rossi, Carlo Aymonino, James Stirling, Oswald Mathias Ungers e molti altri, che si confrontano sul tema delle città storiche, alle giornate seminariali dedicate all’elaborazione di un progetto per cinque aree individuate all’interno di Santiago de Compostela e quindi dell’applicazione alla pratica progettuale dell’inscindibile base teorica esposta. Segue la seconda parte dello stesso capitolo riguardante La selezione di interviste ai partecipanti al Seminario. Esso contiene la raccolta dei colloqui avuti con alcuni dei personaggi che presero parte al Seminario e attraverso le loro parole si è cercato di approfondire la materia, in particolar modo andando ad evidenziare l’ambiente culturale in cui nacque l’idea del Seminario, il ruolo avuto nella diffusione della teoria di Aldo Rossi in Spagna e la ripercussione che ebbe nella pratica costruttiva. Le diverse interviste, seppur rivolte a persone che oggi vivono in contesti distanti e che in seguito a questa esperienza collettiva hanno intrapreso strade diverse, hanno fatto emergere aspetti comuni, tale unanimità ha dato ancor più importanza al valore di testimonianza offerta. L’elemento che risulta più evidente è il lascito teorico, di molto prevalente rispetto a quello progettuale che si è andato mescolando di volta in volta con la tradizione e l’esperienza dei cosiddetti allievi di Aldo Rossi. Negli stessi anni comincia a farsi strada l’importanza del confronto e del dibattito circa i temi architettonici e nel capitolo La fortuna critica della teoria di Aldo Rossi nella Penisola Iberica è stato affrontato proprio questo rinnovato interesse per la teoria che in quegli anni si stava diffondendo. Si è portato avanti lo studio delle pubblicazioni di Gustavo Gili nella Coleccion Arquitectura y Critica che, a partire dalla fine degli anni Sessanta, pubblica e traduce in lingua spagnola i più importanti saggi di architettura, tra i quali La arquitectura de la ciudad di Aldo Rossi, nel 1971, e Comlejidad y contradiccion en arquitectura di Robert Venturi nel 1972. Entrambi fondamentali per il modo di affrontare determinate tematiche di cui sempre più in quegli anni si stava interessando la cultura architettonica iberica, diventando così ¬ testi di riferimento anche nelle scuole. Le tracce dell’influenza di Rossi sulla Penisola Iberica si sono poi ricercate nella rivista “2C. Construccion de la Ciudad” individuata come strumento di espressione di una teoria condivisa. Con la nascita nel 1972 a Barcellona di questa rivista viene portato avanti l’impegno di promuovere la Tendenza, facendo riferimento all’opera e alle idee di Rossi ed altri architetti europei, mirando inoltre al recupero di un ruolo privilegiato dell’architettura catalana. A questo proposito sono emersi due fondamentali aspetti che hanno legittimato l’indagine e lo studio di questa fonte: - la diffusione della cultura architettonica, il controllo ideologico e di informazione operato dal lavoro compiuto dalla rivista; - la documentazione circa i criteri di scelta della redazione a proposito del materiale pubblicato. E’ infatti attraverso le pubblicazioni di “2C. Construccion de la Ciudad” che è stato possibile il ritrovamento delle notizie sulla mostra Arquitectura y razionalismo. Aldo Rossi + 21 arquitectos españoles, che accomuna in un’unica esposizione le opere del maestro e di ventuno giovani allievi che hanno recepito e condiviso la teoria espressa ne “L’architettura della città”. Tale mostra viene poi riproposta nella Sezione Internazionale di Architettura della XV Triennale di Milano, la quale dedica un Padiglione col titolo Barcelona, tres epocas tres propuestas. Dalla disamina dei progetti presentati è emerso un interessante caso di confronto tra le Viviendas para gitanos di César Portela e la Casa Bay di Borgo Ticino di Aldo Rossi, di cui si è occupato l’ultimo paragrafo di questo capitolo. Nel corso degli studi è poi emerso un interessante risvolto della ricerca che, capovolgendone l’oggetto stesso, ne ha approfondito gli aspetti cercando di scavare più in profondità nell’analisi della reciproca influenza tra la cultura iberica e Aldo Rossi, questa parte, sviscerata nell’ultimo capitolo, La Penisola Iberica nel “magazzino della memoria” di Aldo Rossi, ha preso il posto di quello che inizialmente doveva presentarsi come il risvolto progettuale della tesi. Era previsto infatti, al termine dello studio dell’influenza di Aldo Rossi sulla Penisola Iberica, un capitolo che concentrava l’attenzione sulla produzione progettuale. A seguito dell’emergere di un’influenza di carattere prettamente teorica, che ha sicuramente modificato la pratica dal punto di vista delle scelte architettoniche, senza però rendersi esplicita dal punto di vista formale, si è preferito, anche per la difficoltà di individuare un solo esempio rappresentativo di quanto espresso, sostituire quest’ultima parte con lo studio dell’altra faccia della medaglia, ossia l’importanza che a sua volta ha avuto la cultura iberica nella formazione della collezione dei riferimenti di Aldo Rossi. L’articolarsi della tesi in fasi distinte, strettamente connesse tra loro da un filo conduttore, ha reso necessari successivi aggiustamenti nel percorso intrapreso, dettati dall’emergere durante la ricerca di nuovi elementi di indagine. Si è pertanto resa esplicita la ricercata eredità di Aldo Rossi, configurandosi però prevalentemente come un’influenza teorica che ha preso le sfumature del contesto e dell’esperienza personale di chi se ne è fatto ricevente, diventandone così un continuatore attraverso il proprio percorso autonomo o collettivo intrapreso in seguito. Come suggerisce José Charters Monteiro, l’eredità di Rossi può essere letta attraverso tre aspetti su cui si basa la sua lezione: la biografia, la teoria dell’architettura, l’opera. In particolar modo per quanto riguarda la Penisola Iberica si può parlare dell’individuazione di un insegnamento riferito alla seconda categoria, i suoi libri di testo, le sue partecipazioni, le traduzioni. Questo è un lascito che rende possibile la continuazione di un dibattito in merito ai temi della teoria dell’architettura, della sue finalità e delle concrete applicazioni nelle opere, che ha permesso il verificarsi di una apertura mentale che mette in relazione l’architettura con altre discipline umanistiche e scientifiche, dalla politica, alla sociologia, comprendendo l’arte, le città la morfologia, la topografia, mediate e messe in relazione proprio attraverso l’architettura.

Genomic analysis of non-splenic marginal zone lymphomas (MZL) indicates similarities between nodal and extranodal MZL and supports their derivation from memory B-cells

Three distinct categories of marginal zone lymphomas (MZLs) are currently recognized, principally based on their site of occurrence. They are thought to represent unique entities, but the relationship of one subtype with another is poorly understood. We investigated 17 non-splenic MZLs (seven nodal, 10 extranodal) by gene expression profiling to distinguish between subtypes and determine their cell of origin. Our findings suggest biological inter-relatedness of these entities despite occurrence at different locations and associations with possibly different aetiologies. Furthermore, the expression profiles of non-splenic MZL were similar to memory B cells.

Isolated Islands? Memory of the Holocaust in Formal and Non-Formal Education. The Case Study of Post-Communist Poland

Existing studies revealed several conflicts around the memory of the Holocaust in Poland: between understanding the need to teach about the Holocaust and indifference toward anti-Jewish graffiti; a conflict around the perception of Polish help to Jews; and the competing images of Polish and Jewish suffering during World War II. Those conflicts will be addressed in the paper as reflecting educational gaps in the Polish education system (lack of bad memory). This paper will look at the consciousness of young Poles, in terms of attitudes toward Jews, the Holocaust and memory of the Holocaust. The data presented are the preliminary results of the author’s longitudinal study „Attitudes of Young Poles toward the Jews and the Holocaust”. Quantitative and qualitative studies include field studies and participant observation of educational projects in Tykocin, Treblinka, Warsaw, Lublin, Bodzentyn and Kielce. The paper will present some components of the development of education about the Holocaust in Poland. There is a need to evaluate the attempt to bring back the memory of Jewish neighbours in some of the states of Central and Eastern Europe, a process with an ongoing effort to renovate monuments, destroyed cemeteries and synagogues. The number and scope of such initiatives in Poland indicate that civic institutions and individuals are intensifying their efforts to teach their fellow citizens about the Holocaust, however their impact should be assessed in detail.

Communication Middleware for Distributed Hard Real-Time Systems in Java

Distributed real-time embedded systems are becoming increasingly important to society. More demands will be made on them and greater reliance will be placed on the delivery of their services. A relevant subset of them is high-integrity or hard real-time systems, where failure can cause loss of life, environmental harm, or significant financial loss. Additionally, the evolution of communication networks and paradigms as well as the necessity of demanding processing power and fault tolerance, motivated the interconnection between electronic devices; many of the communications have the possibility of transferring data at a high speed. The concept of distributed systems emerged as systems where different parts are executed on several nodes that interact with each other via a communication network. Java’s popularity, facilities and platform independence have made it an interesting language for the real-time and embedded community. This was the motivation for the development of RTSJ (Real-Time Specification for Java), which is a language extension intended to allow the development of real-time systems. The use of Java in the development of high-integrity systems requires strict development and testing techniques. However, RTJS includes a number of language features that are forbidden in such systems. In the context of the HIJA project, the HRTJ (Hard Real-Time Java) profile was developed to define a robust subset of the language that is amenable to static analysis for high-integrity system certification. Currently, a specification under the Java community process (JSR- 302) is being developed. Its purpose is to define those capabilities needed to create safety critical applications with Java technology called Safety Critical Java (SCJ). However, neither RTSJ nor its profiles provide facilities to develop distributed realtime applications. This is an important issue, as most of the current and future systems will be distributed. The Distributed RTSJ (DRTSJ) Expert Group was created under the Java community process (JSR-50) in order to define appropriate abstractions to overcome this problem. Currently there is no formal specification. The aim of this thesis is to develop a communication middleware that is suitable for the development of distributed hard real-time systems in Java, based on the integration between the RMI (Remote Method Invocation) model and the HRTJ profile. It has been designed and implemented keeping in mind the main requirements such as the predictability and reliability in the timing behavior and the resource usage. iThe design starts with the definition of a computational model which identifies among other things: the communication model, most appropriate underlying network protocols, the analysis model, and a subset of Java for hard real-time systems. In the design, the remote references are the basic means for building distributed applications which are associated with all non-functional parameters and resources needed to implement synchronous or asynchronous remote invocations with real-time attributes. The proposed middleware separates the resource allocation from the execution itself by defining two phases and a specific threading mechanism that guarantees a suitable timing behavior. It also includes mechanisms to monitor the functional and the timing behavior. It provides independence from network protocol defining a network interface and modules. The JRMP protocol was modified to include two phases, non-functional parameters, and message size optimizations. Although serialization is one of the fundamental operations to ensure proper data transmission, current implementations are not suitable for hard real-time systems and there are no alternatives. This thesis proposes a predictable serialization that introduces a new compiler to generate optimized code according to the computational model. The proposed solution has the advantage of allowing us to schedule the communications and to adjust the memory usage at compilation time. In order to validate the design and the implementation a demanding validation process was carried out with emphasis in the functional behavior, the memory usage, the processor usage (the end-to-end response time and the response time in each functional block) and the network usage (real consumption according to the calculated consumption). The results obtained in an industrial application developed by Thales Avionics (a Flight Management System) and in exhaustive tests show that the design and the prototype are reliable for industrial applications with strict timing requirements. Los sistemas empotrados y distribuidos de tiempo real son cada vez más importantes para la sociedad. Su demanda aumenta y cada vez más dependemos de los servicios que proporcionan. Los sistemas de alta integridad constituyen un subconjunto de gran importancia. Se caracterizan por que un fallo en su funcionamiento puede causar pérdida de vidas humanas, daños en el medio ambiente o cuantiosas pérdidas económicas. La necesidad de satisfacer requisitos temporales estrictos, hace más complejo su desarrollo. Mientras que los sistemas empotrados se sigan expandiendo en nuestra sociedad, es necesario garantizar un coste de desarrollo ajustado mediante el uso técnicas adecuadas en su diseño, mantenimiento y certificación. En concreto, se requiere una tecnología flexible e independiente del hardware. La evolución de las redes y paradigmas de comunicación, así como la necesidad de mayor potencia de cómputo y de tolerancia a fallos, ha motivado la interconexión de dispositivos electrónicos. Los mecanismos de comunicación permiten la transferencia de datos con alta velocidad de transmisión. En este contexto, el concepto de sistema distribuido ha emergido como sistemas donde sus componentes se ejecutan en varios nodos en paralelo y que interactúan entre ellos mediante redes de comunicaciones. Un concepto interesante son los sistemas de tiempo real neutrales respecto a la plataforma de ejecución. Se caracterizan por la falta de conocimiento de esta plataforma durante su diseño. Esta propiedad es relevante, por que conviene que se ejecuten en la mayor variedad de arquitecturas, tienen una vida media mayor de diez anos y el lugar ˜ donde se ejecutan puede variar. El lenguaje de programación Java es una buena base para el desarrollo de este tipo de sistemas. Por este motivo se ha creado RTSJ (Real-Time Specification for Java), que es una extensión del lenguaje para permitir el desarrollo de sistemas de tiempo real. Sin embargo, RTSJ no proporciona facilidades para el desarrollo de aplicaciones distribuidas de tiempo real. Es una limitación importante dado que la mayoría de los actuales y futuros sistemas serán distribuidos. El grupo DRTSJ (DistributedRTSJ) fue creado bajo el proceso de la comunidad de Java (JSR-50) con el fin de definir las abstracciones que aborden dicha limitación, pero en la actualidad aun no existe una especificacion formal. El objetivo de esta tesis es desarrollar un middleware de comunicaciones para el desarrollo de sistemas distribuidos de tiempo real en Java, basado en la integración entre el modelo de RMI (Remote Method Invocation) y el perfil HRTJ. Ha sido diseñado e implementado teniendo en cuenta los requisitos principales, como la predecibilidad y la confiabilidad del comportamiento temporal y el uso de recursos. El diseño parte de la definición de un modelo computacional el cual identifica entre otras cosas: el modelo de comunicaciones, los protocolos de red subyacentes más adecuados, el modelo de análisis, y un subconjunto de Java para sistemas de tiempo real crítico. En el diseño, las referencias remotas son el medio básico para construcción de aplicaciones distribuidas las cuales son asociadas a todos los parámetros no funcionales y los recursos necesarios para la ejecución de invocaciones remotas síncronas o asíncronas con atributos de tiempo real. El middleware propuesto separa la asignación de recursos de la propia ejecución definiendo dos fases y un mecanismo de hebras especifico que garantiza un comportamiento temporal adecuado. Además se ha incluido mecanismos para supervisar el comportamiento funcional y temporal. Se ha buscado independencia del protocolo de red definiendo una interfaz de red y módulos específicos. También se ha modificado el protocolo JRMP para incluir diferentes fases, parámetros no funcionales y optimizaciones de los tamaños de los mensajes. Aunque la serialización es una de las operaciones fundamentales para asegurar la adecuada transmisión de datos, las actuales implementaciones no son adecuadas para sistemas críticos y no hay alternativas. Este trabajo propone una serialización predecible que ha implicado el desarrollo de un nuevo compilador para la generación de código optimizado acorde al modelo computacional. La solución propuesta tiene la ventaja que en tiempo de compilación nos permite planificar las comunicaciones y ajustar el uso de memoria. Con el objetivo de validar el diseño e implementación se ha llevado a cabo un exigente proceso de validación con énfasis en: el comportamiento funcional, el uso de memoria, el uso del procesador (tiempo de respuesta de extremo a extremo y en cada uno de los bloques funcionales) y el uso de la red (consumo real conforme al estimado). Los buenos resultados obtenidos en una aplicación industrial desarrollada por Thales Avionics (un sistema de gestión de vuelo) y en las pruebas exhaustivas han demostrado que el diseño y el prototipo son fiables para aplicaciones industriales con estrictos requisitos temporales.

Run-Time Dynamically-Adaptable FPGA-Based Architecture for High-Performance Autonomous Distributed Systems

Esta tesis doctoral se enmarca dentro del campo de los sistemas embebidos reconfigurables, redes de sensores inalámbricas para aplicaciones de altas prestaciones, y computación distribuida. El documento se centra en el estudio de alternativas de procesamiento para sistemas embebidos autónomos distribuidos de altas prestaciones (por sus siglas en inglés, High-Performance Autonomous Distributed Systems (HPADS)), así como su evolución hacia el procesamiento de alta resolución. El estudio se ha llevado a cabo tanto a nivel de plataforma como a nivel de las arquitecturas de procesamiento dentro de la plataforma con el objetivo de optimizar aspectos tan relevantes como la eficiencia energética, la capacidad de cómputo y la tolerancia a fallos del sistema. Los HPADS son sistemas realimentados, normalmente formados por elementos distribuidos conectados o no en red, con cierta capacidad de adaptación, y con inteligencia suficiente para llevar a cabo labores de prognosis y/o autoevaluación. Esta clase de sistemas suele formar parte de sistemas más complejos llamados sistemas ciber-físicos (por sus siglas en inglés, Cyber-Physical Systems (CPSs)). Los CPSs cubren un espectro enorme de aplicaciones, yendo desde aplicaciones médicas, fabricación, o aplicaciones aeroespaciales, entre otras muchas. Para el diseño de este tipo de sistemas, aspectos tales como la confiabilidad, la definición de modelos de computación, o el uso de metodologías y/o herramientas que faciliten el incremento de la escalabilidad y de la gestión de la complejidad, son fundamentales. La primera parte de esta tesis doctoral se centra en el estudio de aquellas plataformas existentes en el estado del arte que por sus características pueden ser aplicables en el campo de los CPSs, así como en la propuesta de un nuevo diseño de plataforma de altas prestaciones que se ajuste mejor a los nuevos y más exigentes requisitos de las nuevas aplicaciones. Esta primera parte incluye descripción, implementación y validación de la plataforma propuesta, así como conclusiones sobre su usabilidad y sus limitaciones. Los principales objetivos para el diseño de la plataforma propuesta se enumeran a continuación: • Estudiar la viabilidad del uso de una FPGA basada en RAM como principal procesador de la plataforma en cuanto a consumo energético y capacidad de cómputo. • Propuesta de técnicas de gestión del consumo de energía en cada etapa del perfil de trabajo de la plataforma. •Propuestas para la inclusión de reconfiguración dinámica y parcial de la FPGA (por sus siglas en inglés, Dynamic Partial Reconfiguration (DPR)) de forma que sea posible cambiar ciertas partes del sistema en tiempo de ejecución y sin necesidad de interrumpir al resto de las partes. Evaluar su aplicabilidad en el caso de HPADS. Las nuevas aplicaciones y nuevos escenarios a los que se enfrentan los CPSs, imponen nuevos requisitos en cuanto al ancho de banda necesario para el procesamiento de los datos, así como en la adquisición y comunicación de los mismos, además de un claro incremento en la complejidad de los algoritmos empleados. Para poder cumplir con estos nuevos requisitos, las plataformas están migrando desde sistemas tradicionales uni-procesador de 8 bits, a sistemas híbridos hardware-software que incluyen varios procesadores, o varios procesadores y lógica programable. Entre estas nuevas arquitecturas, las FPGAs y los sistemas en chip (por sus siglas en inglés, System on Chip (SoC)) que incluyen procesadores embebidos y lógica programable, proporcionan soluciones con muy buenos resultados en cuanto a consumo energético, precio, capacidad de cómputo y flexibilidad. Estos buenos resultados son aún mejores cuando las aplicaciones tienen altos requisitos de cómputo y cuando las condiciones de trabajo son muy susceptibles de cambiar en tiempo real. La plataforma propuesta en esta tesis doctoral se ha denominado HiReCookie. La arquitectura incluye una FPGA basada en RAM como único procesador, así como un diseño compatible con la plataforma para redes de sensores inalámbricas desarrollada en el Centro de Electrónica Industrial de la Universidad Politécnica de Madrid (CEI-UPM) conocida como Cookies. Esta FPGA, modelo Spartan-6 LX150, era, en el momento de inicio de este trabajo, la mejor opción en cuanto a consumo y cantidad de recursos integrados, cuando además, permite el uso de reconfiguración dinámica y parcial. Es importante resaltar que aunque los valores de consumo son los mínimos para esta familia de componentes, la potencia instantánea consumida sigue siendo muy alta para aquellos sistemas que han de trabajar distribuidos, de forma autónoma, y en la mayoría de los casos alimentados por baterías. Por esta razón, es necesario incluir en el diseño estrategias de ahorro energético para incrementar la usabilidad y el tiempo de vida de la plataforma. La primera estrategia implementada consiste en dividir la plataforma en distintas islas de alimentación de forma que sólo aquellos elementos que sean estrictamente necesarios permanecerán alimentados, cuando el resto puede estar completamente apagado. De esta forma es posible combinar distintos modos de operación y así optimizar enormemente el consumo de energía. El hecho de apagar la FPGA para ahora energía durante los periodos de inactividad, supone la pérdida de la configuración, puesto que la memoria de configuración es una memoria volátil. Para reducir el impacto en el consumo y en el tiempo que supone la reconfiguración total de la plataforma una vez encendida, en este trabajo, se incluye una técnica para la compresión del archivo de configuración de la FPGA, de forma que se consiga una reducción del tiempo de configuración y por ende de la energía consumida. Aunque varios de los requisitos de diseño pueden satisfacerse con el diseño de la plataforma HiReCookie, es necesario seguir optimizando diversos parámetros tales como el consumo energético, la tolerancia a fallos y la capacidad de procesamiento. Esto sólo es posible explotando todas las posibilidades ofrecidas por la arquitectura de procesamiento en la FPGA. Por lo tanto, la segunda parte de esta tesis doctoral está centrada en el diseño de una arquitectura reconfigurable denominada ARTICo3 (Arquitectura Reconfigurable para el Tratamiento Inteligente de Cómputo, Confiabilidad y Consumo de energía) para la mejora de estos parámetros por medio de un uso dinámico de recursos. ARTICo3 es una arquitectura de procesamiento para FPGAs basadas en RAM, con comunicación tipo bus, preparada para dar soporte para la gestión dinámica de los recursos internos de la FPGA en tiempo de ejecución gracias a la inclusión de reconfiguración dinámica y parcial. Gracias a esta capacidad de reconfiguración parcial, es posible adaptar los niveles de capacidad de procesamiento, energía consumida o tolerancia a fallos para responder a las demandas de la aplicación, entorno, o métricas internas del dispositivo mediante la adaptación del número de recursos asignados para cada tarea. Durante esta segunda parte de la tesis se detallan el diseño de la arquitectura, su implementación en la plataforma HiReCookie, así como en otra familia de FPGAs, y su validación por medio de diferentes pruebas y demostraciones. Los principales objetivos que se plantean la arquitectura son los siguientes: • Proponer una metodología basada en un enfoque multi-hilo, como las propuestas por CUDA (por sus siglas en inglés, Compute Unified Device Architecture) u Open CL, en la cual distintos kernels, o unidades de ejecución, se ejecuten en un numero variable de aceleradores hardware sin necesidad de cambios en el código de aplicación. • Proponer un diseño y proporcionar una arquitectura en la que las condiciones de trabajo cambien de forma dinámica dependiendo bien de parámetros externos o bien de parámetros que indiquen el estado de la plataforma. Estos cambios en el punto de trabajo de la arquitectura serán posibles gracias a la reconfiguración dinámica y parcial de aceleradores hardware en tiempo real. • Explotar las posibilidades de procesamiento concurrente, incluso en una arquitectura basada en bus, por medio de la optimización de las transacciones en ráfaga de datos hacia los aceleradores. •Aprovechar las ventajas ofrecidas por la aceleración lograda por módulos puramente hardware para conseguir una mejor eficiencia energética. • Ser capaces de cambiar los niveles de redundancia de hardware de forma dinámica según las necesidades del sistema en tiempo real y sin cambios para el código de aplicación. • Proponer una capa de abstracción entre el código de aplicación y el uso dinámico de los recursos de la FPGA. El diseño en FPGAs permite la utilización de módulos hardware específicamente creados para una aplicación concreta. De esta forma es posible obtener rendimientos mucho mayores que en el caso de las arquitecturas de propósito general. Además, algunas FPGAs permiten la reconfiguración dinámica y parcial de ciertas partes de su lógica en tiempo de ejecución, lo cual dota al diseño de una gran flexibilidad. Los fabricantes de FPGAs ofrecen arquitecturas predefinidas con la posibilidad de añadir bloques prediseñados y poder formar sistemas en chip de una forma más o menos directa. Sin embargo, la forma en la que estos módulos hardware están organizados dentro de la arquitectura interna ya sea estática o dinámicamente, o la forma en la que la información se intercambia entre ellos, influye enormemente en la capacidad de cómputo y eficiencia energética del sistema. De la misma forma, la capacidad de cargar módulos hardware bajo demanda, permite añadir bloques redundantes que permitan aumentar el nivel de tolerancia a fallos de los sistemas. Sin embargo, la complejidad ligada al diseño de bloques hardware dedicados no debe ser subestimada. Es necesario tener en cuenta que el diseño de un bloque hardware no es sólo su propio diseño, sino también el diseño de sus interfaces, y en algunos casos de los drivers software para su manejo. Además, al añadir más bloques, el espacio de diseño se hace más complejo, y su programación más difícil. Aunque la mayoría de los fabricantes ofrecen interfaces predefinidas, IPs (por sus siglas en inglés, Intelectual Property) comerciales y plantillas para ayudar al diseño de los sistemas, para ser capaces de explotar las posibilidades reales del sistema, es necesario construir arquitecturas sobre las ya establecidas para facilitar el uso del paralelismo, la redundancia, y proporcionar un entorno que soporte la gestión dinámica de los recursos. Para proporcionar este tipo de soporte, ARTICo3 trabaja con un espacio de soluciones formado por tres ejes fundamentales: computación, consumo energético y confiabilidad. De esta forma, cada punto de trabajo se obtiene como una solución de compromiso entre estos tres parámetros. Mediante el uso de la reconfiguración dinámica y parcial y una mejora en la transmisión de los datos entre la memoria principal y los aceleradores, es posible dedicar un número variable de recursos en el tiempo para cada tarea, lo que hace que los recursos internos de la FPGA sean virtualmente ilimitados. Este variación en el tiempo del número de recursos por tarea se puede usar bien para incrementar el nivel de paralelismo, y por ende de aceleración, o bien para aumentar la redundancia, y por lo tanto el nivel de tolerancia a fallos. Al mismo tiempo, usar un numero óptimo de recursos para una tarea mejora el consumo energético ya que bien es posible disminuir la potencia instantánea consumida, o bien el tiempo de procesamiento. Con el objetivo de mantener los niveles de complejidad dentro de unos límites lógicos, es importante que los cambios realizados en el hardware sean totalmente transparentes para el código de aplicación. A este respecto, se incluyen distintos niveles de transparencia: • Transparencia a la escalabilidad: los recursos usados por una misma tarea pueden ser modificados sin que el código de aplicación sufra ningún cambio. • Transparencia al rendimiento: el sistema aumentara su rendimiento cuando la carga de trabajo aumente, sin cambios en el código de aplicación. • Transparencia a la replicación: es posible usar múltiples instancias de un mismo módulo bien para añadir redundancia o bien para incrementar la capacidad de procesamiento. Todo ello sin que el código de aplicación cambie. • Transparencia a la posición: la posición física de los módulos hardware es arbitraria para su direccionamiento desde el código de aplicación. • Transparencia a los fallos: si existe un fallo en un módulo hardware, gracias a la redundancia, el código de aplicación tomará directamente el resultado correcto. • Transparencia a la concurrencia: el hecho de que una tarea sea realizada por más o menos bloques es transparente para el código que la invoca. Por lo tanto, esta tesis doctoral contribuye en dos líneas diferentes. En primer lugar, con el diseño de la plataforma HiReCookie y en segundo lugar con el diseño de la arquitectura ARTICo3. Las principales contribuciones de esta tesis se resumen a continuación. • Arquitectura de la HiReCookie incluyendo: o Compatibilidad con la plataforma Cookies para incrementar las capacidades de esta. o División de la arquitectura en distintas islas de alimentación. o Implementación de los diversos modos de bajo consumo y políticas de despertado del nodo. o Creación de un archivo de configuración de la FPGA comprimido para reducir el tiempo y el consumo de la configuración inicial. • Diseño de la arquitectura reconfigurable para FPGAs basadas en RAM ARTICo3: o Modelo de computación y modos de ejecución inspirados en el modelo de CUDA pero basados en hardware reconfigurable con un número variable de bloques de hilos por cada unidad de ejecución. o Estructura para optimizar las transacciones de datos en ráfaga proporcionando datos en cascada o en paralelo a los distinto módulos incluyendo un proceso de votado por mayoría y operaciones de reducción. o Capa de abstracción entre el procesador principal que incluye el código de aplicación y los recursos asignados para las diferentes tareas. o Arquitectura de los módulos hardware reconfigurables para mantener la escalabilidad añadiendo una la interfaz para las nuevas funcionalidades con un simple acceso a una memoria RAM interna. o Caracterización online de las tareas para proporcionar información a un módulo de gestión de recursos para mejorar la operación en términos de energía y procesamiento cuando además se opera entre distintos nieles de tolerancia a fallos. El documento está dividido en dos partes principales formando un total de cinco capítulos. En primer lugar, después de motivar la necesidad de nuevas plataformas para cubrir las nuevas aplicaciones, se detalla el diseño de la plataforma HiReCookie, sus partes, las posibilidades para bajar el consumo energético y se muestran casos de uso de la plataforma así como pruebas de validación del diseño. La segunda parte del documento describe la arquitectura reconfigurable, su implementación en varias FPGAs, y pruebas de validación en términos de capacidad de procesamiento y consumo energético, incluyendo cómo estos aspectos se ven afectados por el nivel de tolerancia a fallos elegido. Los capítulos a lo largo del documento son los siguientes: El capítulo 1 analiza los principales objetivos, motivación y aspectos teóricos necesarios para seguir el resto del documento. El capítulo 2 está centrado en el diseño de la plataforma HiReCookie y sus posibilidades para disminuir el consumo de energía. El capítulo 3 describe la arquitectura reconfigurable ARTICo3. El capítulo 4 se centra en las pruebas de validación de la arquitectura usando la plataforma HiReCookie para la mayoría de los tests. Un ejemplo de aplicación es mostrado para analizar el funcionamiento de la arquitectura. El capítulo 5 concluye esta tesis doctoral comentando las conclusiones obtenidas, las contribuciones originales del trabajo y resultados y líneas futuras. ABSTRACT This PhD Thesis is framed within the field of dynamically reconfigurable embedded systems, advanced sensor networks and distributed computing. The document is centred on the study of processing solutions for high-performance autonomous distributed systems (HPADS) as well as their evolution towards High performance Computing (HPC) systems. The approach of the study is focused on both platform and processor levels to optimise critical aspects such as computing performance, energy efficiency and fault tolerance. HPADS are considered feedback systems, normally networked and/or distributed, with real-time adaptive and predictive functionality. These systems, as part of more complex systems known as Cyber-Physical Systems (CPSs), can be applied in a wide range of fields such as military, health care, manufacturing, aerospace, etc. For the design of HPADS, high levels of dependability, the definition of suitable models of computation, and the use of methodologies and tools to support scalability and complexity management, are required. The first part of the document studies the different possibilities at platform design level in the state of the art, together with description, development and validation tests of the platform proposed in this work to cope with the previously mentioned requirements. The main objectives targeted by this platform design are the following: • Study the feasibility of using SRAM-based FPGAs as the main processor of the platform in terms of energy consumption and performance for high demanding applications. • Analyse and propose energy management techniques to reduce energy consumption in every stage of the working profile of the platform. • Provide a solution with dynamic partial and wireless remote HW reconfiguration (DPR) to be able to change certain parts of the FPGA design at run time and on demand without interrupting the rest of the system. • Demonstrate the applicability of the platform in different test-bench applications. In order to select the best approach for the platform design in terms of processing alternatives, a study of the evolution of the state-of-the-art platforms is required to analyse how different architectures cope with new more demanding applications and scenarios: security, mixed-critical systems for aerospace, multimedia applications, or military environments, among others. In all these scenarios, important changes in the required processing bandwidth or the complexity of the algorithms used are provoking the migration of the platforms from single microprocessor architectures to multiprocessing and heterogeneous solutions with more instant power consumption but higher energy efficiency. Within these solutions, FPGAs and Systems on Chip including FPGA fabric and dedicated hard processors, offer a good trade of among flexibility, processing performance, energy consumption and price, when they are used in demanding applications where working conditions are very likely to vary over time and high complex algorithms are required. The platform architecture proposed in this PhD Thesis is called HiReCookie. It includes an SRAM-based FPGA as the main and only processing unit. The FPGA selected, the Xilinx Spartan-6 LX150, was at the beginning of this work the best choice in terms of amount of resources and power. Although, the power levels are the lowest of these kind of devices, they can be still very high for distributed systems that normally work powered by batteries. For that reason, it is necessary to include different energy saving possibilities to increase the usability of the platform. In order to reduce energy consumption, the platform architecture is divided into different power islands so that only those parts of the systems that are strictly needed are powered on, while the rest of the islands can be completely switched off. This allows a combination of different low power modes to decrease energy. In addition, one of the most important handicaps of SRAM-based FPGAs is that they are not alive at power up. Therefore, recovering the system from a switch-off state requires to reload the FPGA configuration from a non-volatile memory device. For that reason, this PhD Thesis also proposes a methodology to compress the FPGA configuration file in order to reduce time and energy during the initial configuration process. Although some of the requirements for the design of HPADS are already covered by the design of the HiReCookie platform, it is necessary to continue improving energy efficiency, computing performance and fault tolerance. This is only possible by exploiting all the opportunities provided by the processing architectures configured inside the FPGA. Therefore, the second part of the thesis details the design of the so called ARTICo3 FPGA architecture to enhance the already intrinsic capabilities of the FPGA. ARTICo3 is a DPR-capable bus-based virtual architecture for multiple HW acceleration in SRAM-based FPGAs. The architecture provides support for dynamic resource management in real time. In this way, by using DPR, it will be possible to change the levels of computing performance, energy consumption and fault tolerance on demand by increasing or decreasing the amount of resources used by the different tasks. Apart from the detailed design of the architecture and its implementation in different FPGA devices, different validation tests and comparisons are also shown. The main objectives targeted by this FPGA architecture are listed as follows: • Provide a method based on a multithread approach such as those offered by CUDA (Compute Unified Device Architecture) or OpenCL kernel executions, where kernels are executed in a variable number of HW accelerators without requiring application code changes. • Provide an architecture to dynamically adapt working points according to either self-measured or external parameters in terms of energy consumption, fault tolerance and computing performance. Taking advantage of DPR capabilities, the architecture must provide support for a dynamic use of resources in real time. • Exploit concurrent processing capabilities in a standard bus-based system by optimizing data transactions to and from HW accelerators. • Measure the advantage of HW acceleration as a technique to boost performance to improve processing times and save energy by reducing active times for distributed embedded systems. • Dynamically change the levels of HW redundancy to adapt fault tolerance in real time. • Provide HW abstraction from SW application design. FPGAs give the possibility of designing specific HW blocks for every required task to optimise performance while some of them include the possibility of including DPR. Apart from the possibilities provided by manufacturers, the way these HW modules are organised, addressed and multiplexed in area and time can improve computing performance and energy consumption. At the same time, fault tolerance and security techniques can also be dynamically included using DPR. However, the inherent complexity of designing new HW modules for every application is not negligible. It does not only consist of the HW description, but also the design of drivers and interfaces with the rest of the system, while the design space is widened and more complex to define and program. Even though the tools provided by the majority of manufacturers already include predefined bus interfaces, commercial IPs, and templates to ease application prototyping, it is necessary to improve these capabilities. By adding new architectures on top of them, it is possible to take advantage of parallelization and HW redundancy while providing a framework to ease the use of dynamic resource management. ARTICo3 works within a solution space where working points change at run time in a 3D space defined by three different axes: Computation, Consumption, and Fault Tolerance. Therefore, every working point is found as a trade-off solution among these three axes. By means of DPR, different accelerators can be multiplexed so that the amount of available resources for any application is virtually unlimited. Taking advantage of DPR capabilities and a novel way of transmitting data to the reconfigurable HW accelerators, it is possible to dedicate a dynamically-changing number of resources for a given task in order to either boost computing speed or adding HW redundancy and a voting process to increase fault-tolerance levels. At the same time, using an optimised amount of resources for a given task reduces energy consumption by reducing instant power or computing time. In order to keep level complexity under certain limits, it is important that HW changes are transparent for the application code. Therefore, different levels of transparency are targeted by the system: • Scalability transparency: a task must be able to expand its resources without changing the system structure or application algorithms. • Performance transparency: the system must reconfigure itself as load changes. • Replication transparency: multiple instances of the same task are loaded to increase reliability and performance. • Location transparency: resources are accessed with no knowledge of their location by the application code. • Failure transparency: task must be completed despite a failure in some components. • Concurrency transparency: different tasks will work in a concurrent way transparent to the application code. Therefore, as it can be seen, the Thesis is contributing in two different ways. First with the design of the HiReCookie platform and, second with the design of the ARTICo3 architecture. The main contributions of this PhD Thesis are then listed below: • Architecture of the HiReCookie platform including: o Compatibility of the processing layer for high performance applications with the Cookies Wireless Sensor Network platform for fast prototyping and implementation. o A division of the architecture in power islands. o All the different low-power modes. o The creation of the partial-initial bitstream together with the wake-up policies of the node. • The design of the reconfigurable architecture for SRAM FPGAs: ARTICo3: o A model of computation and execution modes inspired in CUDA but based on reconfigurable HW with a dynamic number of thread blocks per kernel. o A structure to optimise burst data transactions providing coalesced or parallel data to HW accelerators, parallel voting process and reduction operation. o The abstraction provided to the host processor with respect to the operation of the kernels in terms of the number of replicas, modes of operation, location in the reconfigurable area and addressing. o The architecture of the modules representing the thread blocks to make the system scalable by adding functional units only adding an access to a BRAM port. o The online characterization of the kernels to provide information to a scheduler or resource manager in terms of energy consumption and processing time when changing among different fault-tolerance levels, as well as if a kernel is expected to work in the memory-bounded or computing-bounded areas. The document of the Thesis is divided into two main parts with a total of five chapters. First, after motivating the need for new platforms to cover new more demanding applications, the design of the HiReCookie platform, its parts and several partial tests are detailed. The design of the platform alone does not cover all the needs of these applications. Therefore, the second part describes the architecture inside the FPGA, called ARTICo3, proposed in this PhD Thesis. The architecture and its implementation are tested in terms of energy consumption and computing performance showing different possibilities to improve fault tolerance and how this impact in energy and time of processing. Chapter 1 shows the main goals of this PhD Thesis and the technology background required to follow the rest of the document. Chapter 2 shows all the details about the design of the FPGA-based platform HiReCookie. Chapter 3 describes the ARTICo3 architecture. Chapter 4 is focused on the validation tests of the ARTICo3 architecture. An application for proof of concept is explained where typical kernels related to image processing and encryption algorithms are used. Further experimental analyses are performed using these kernels. Chapter 5 concludes the document analysing conclusions, comments about the contributions of the work, and some possible future lines for the work.