Education and self-regulation of learning for gifted pupils: Systemic design and development.

Gifted pupils differ from their age-mates with respect to development potential, actual competencies, self-regulatory capabilities, and learning styles in one or more domains of competence. The question is how to design and develop education that fits and further supports such characteristics and competencies of gifted pupils. Analysis of various types of educational interventions for gifted pupils reflects positive cognitive or intellectual effects and differentiated social comparison or group-related effects on these pupils. Systemic preventive combination of such interventions could make these more effective and sustainable. The systemic design is characterised by three conditional dimensions: differentiation of learning materials and procedures, integration by and use of ICT support, and strategies to improve development and learning. The relationships to diagnostic, instructional, managerial, and systemic learning aspects are expressed in guidelines to develop or transform education. The guidelines imply the facilitation of learning arrangements that provide flexible self-regulation for gifted pupils. A three-year pilot in Dutch nursery and primary school is conducted to develop and implement the design in collaboration with teachers. The results constitute prototypes of structured competence domains and supportive software. These support the screening of entry characteristics of all four-year old pupils and assignment of adequate play and learning processes and activities throughout the school career. Gifted and other pupils are supported to work at their actual achievement or competency levels since their start in nursery school, in self-regulated learning arrangements either in or out of class. Each pupil can choose other pupils to collaborate with in small groups, at self-chosen tasks or activities, while being coached by the teacher. Formative evaluation of the school development process shows that the systemic prevention guidelines seem to improve learning and social progress of gifted pupils, including their self-regulation. Further development and implementation steps are discussed.

The Design and Implementation of a SD Card File System

SD card (Secure Digital Memory Card) is widely used in portable storage medium. Currently, latest researches on SD card, are mainly SD card controller based on FPGA (Field Programmable Gate Array). Most of them are relying on API interface (Application Programming Interface), AHB bus (Advanced High performance Bus), etc. They are dedicated to the realization of ultra high speed communication between SD card and upper systems. Studies about SD card controller, really play a vital role in the field of high speed cameras and other sub-areas of expertise. This design of FPGA-based file systems and SD2.0 IP (Intellectual Property core) does not only exhibit a nice transmission rate, but also achieve the systematic management of files, while retaining a strong portability and practicality. The file system design and implementation on a SD card covers the main three IP innovation points. First, the combination and integration of file system and SD card controller, makes the overall system highly integrated and practical. The popular SD2.0 protocol is implemented for communication channels. Pure digital logic design based on VHDL (Very-High-Speed Integrated Circuit Hardware Description Language), integrates the SD card controller in hardware layer and the FAT32 file system for the entire system. Secondly, the document management system mechanism makes document processing more convenient and easy. Especially for small files in batch processing, it can ease the pressure of upper system to frequently access and process them, thereby enhancing the overall efficiency of systems. Finally, digital design ensures the superior performance. For transmission security, CRC (Cyclic Redundancy Check) algorithm is for data transmission protection. Design of each module is platform-independent of macro cells, and keeps a better portability. Custom integrated instructions and interfaces may facilitate easily to use. Finally, the actual test went through multi-platform method, Xilinx and Altera FPGA developing platforms. The timing simulation and debugging of each module was covered. Finally, Test results show that the designed FPGA-based file system IP on SD card can support SD card, TF card and Micro SD with 2.0 protocols, and the successful implementation of systematic management for stored files, and supports SD bus mode. Data read and write rates in Kingston class10 card is approximately 24.27MB/s and 16.94MB/s.

Phobos: The design and implementation of embedded software for a low cost radar warning receiver

This portfolio thesis describes work undertaken by the author under the Engineering Doctorate program of the Institute for System Level Integration. It was carried out in conjunction with the sponsor company Teledyne Defence Limited. A radar warning receiver is a device used to detect and identify the emissions of radars. They were originally developed during the Second World War and are found today on a variety of military platforms as part of the platform’s defensive systems. Teledyne Defence has designed and built components and electronic subsystems for the defence industry since the 1970s. This thesis documents part of the work carried out to create Phobos, Teledyne Defence’s first complete radar warning receiver. Phobos was designed to be the first low cost radar warning receiver. This was made possible by the reuse of existing Teledyne Defence products, commercial off the shelf hardware and advanced UK government algorithms. The challenges of this integration are described and discussed, with detail given of the software architecture and the development of the embedded application. Performance of the embedded system as a whole is described and qualified within the context of a low cost system.

The Road to Bali: ERIA Perspectives on the WTO Ministerial and Asian Integration

The World Trade Organization’s (WTO) forthcoming Ninth Ministerial Conference in Bali comes at a critical juncture for the multilateral trade body, long mired in the Doha Round stalemate. Beyond offering a critical first test at consensus-building and institutional renewal, the Bali Ministerial affords a unique opportunity to gauge contrasting perceptions across ASEAN and East Asian countries of the continued relevance of the WTO to trade and economic governance within the region and beyond. Resulting from the collaborative efforts of the Economic Research Institute for ASEAN and East Asia (ERIA), the Universitas Pelita Harapan (UPH) and the World Trade Institute at the University of Bern (WTI), this policy research initiative offers comparative scholarship on some of the key questions arising from the forthcoming WTO Ministerial gathering from an East Asian perspective. Specifically, it explores what scholars in the region expect the Bali Ministerial to produce by way of tangible outcomes and whether the Ministerial will restore the momentum needed to bring the Doha Round to a successful conclusion. Contributors also investigate how relevant the WTO remains to the multiple processes of deepening economic integration in ASEAN and East Asia (e.g. AEC, TPP, RCEP) and, importantly, what lessons in rule-design and market opening WTO Members could usefully draw from the ongoing march towards the establishment of an ASEAN Economic Community.

Guidelines on building design and operation to minimize air quality impacts from major roads in transit oriented development

Poor air quality has a huge detrimental effect, both economic and on the quality of life, in Australia. Transit oriented design (TOD), which aims to minimise urban sprawl and lower dependency on vehicles, leads to an increasing number of buildings close to transport corridors. This project aims at providing guidelines that are appropriate to include within City Plan to inform future planning along road corridors, and provide recommendations on when mitigation measures should be utilised.