Test and evaluation system for multi-protocol sampled value protection schemes

Proposed transmission smart grids will use a digital platform for the automation of substations operating at voltage levels of 110 kV and above. The IEC 61850 series of standards, released in parts over the last ten years, provide a specification for substation communications networks and systems. These standards, along with IEEE Std 1588-2008 Precision Time Protocol version 2 (PTPv2) for precision timing, are recommended by the both IEC Smart Grid Strategy Group and the NIST Framework and Roadmap for Smart Grid Interoperability Standards for substation automation. IEC 61850-8-1 and IEC 61850-9-2 provide an inter-operable solution to support multi-vendor digital process bus solutions, allowing for the removal of potentially lethal voltages and damaging currents from substation control rooms, a reduction in the amount of cabling required in substations, and facilitates the adoption of non-conventional instrument transformers (NCITs). IEC 61850, PTPv2 and Ethernet are three complementary protocol families that together define the future of sampled value digital process connections for smart substation automation. This paper describes a specific test and evaluation system that uses real time simulation, protection relays, PTPv2 time clocks and artificial network impairment that is being used to investigate technical impediments to the adoption of SV process bus systems by transmission utilities. Knowing the limits of a digital process bus, especially when sampled values and NCITs are included, will enable utilities to make informed decisions regarding the adoption of this technology.

Busway platform bus capacity analysis

Bus Rapid Transit (BRT), because of its operational flexibility and simplicity, is rapidly gaining popularity with urban designers and transit planners. Earlier BRTs were bus shared lane or bus only lane, which share the roadway with general and other forms of traffic. In recent time, more sophisticated designs of BRT have emerged, such as busway, which has separate carriageway for buses and provides very high physical separation of buses from general traffic. Line capacities of a busway are predominately dependent on bus capacity of its stations. Despite new developments in BRT designs, the methodology of capacity analysis is still based on traditional principles of kerbside bus stop on bus only lane operations. Consequently, the tradition methodology lacks accounting for various dimensions of busway station operation, such as passenger crowd, passenger walking and bus lost time along the long busway station platform. This research has developed a purpose made bus capacity analysis methodology for busway station analysis. Extensive observations of kerbside bus stops and busway stations in Brisbane, Australia were made and differences in their operation were studied. A large scale data collection was conducted using the video recording technique at the Mater Hill Busway Station on the South East Busway in Brisbane. This research identified new parameters concerning busway station operation, and through intricate analysis identified the elements and processes which influence the bus dwell time at a busway station platform. A new variable, Bus lost time, was defined and its quantitative descriptions were established. Based on these finding and analysis, a busway station platform bus capacity methodology was developed, comprising of new models for busway station lost time, busway station dwell time, busway station loading area bus capacity, and busway station platform bus capacity. The new methodology not only accounts for passenger boarding and alighting, but also covers platform crowd and bus lost time in station platform bus capacity estimation. The applicability of this methodology was shown through demonstrative examples. Additionally, these examples illustrated the significance of the bus lost time variable in determining station capacities.

Multicast traffic filtering for sampled value process bus networks

Ethernet is a key component of the standards used for digital process buses in transmission substations, namely IEC 61850 and IEEE Std 1588-2008 (PTPv2). These standards use multicast Ethernet frames that can be processed by more than one device. This presents some significant engineering challenges when implementing a sampled value process bus due to the large amount of network traffic. A system of network traffic segregation using a combination of Virtual LAN (VLAN) and multicast address filtering using managed Ethernet switches is presented. This includes VLAN prioritisation of traffic classes such as the IEC 61850 protocols GOOSE, MMS and sampled values (SV), and other protocols like PTPv2. Multicast address filtering is used to limit SV/GOOSE traffic to defined subsets of subscribers. A method to map substation plant reference designations to multicast address ranges is proposed that enables engineers to determine the type of traffic and location of the source by inspecting the destination address. This method and the proposed filtering strategy simplifies future changes to the prioritisation of network traffic, and is applicable to both process bus and station bus applications.

Direct evaluation of IEC 61850-9-2 process bus network performance

This letter presents a technique to assess the overall network performance of sampled value process buses based on IEC 61850-9-2 using measurements from a single location in the network. The method is based upon the use of Ethernet cards with externally synchronized time stamping, and characteristics of the process bus protocol. The application and utility of the method is demonstrated by measuring latency introduced by Ethernet switches. Network latency can be measured from a single set of captures, rather than comparing source and destination captures. Absolute latency measures will greatly assist the design testing, commissioning and maintenance of these critical data networks.

Performance analysis of PTP components for IEC 61850 process bus applications

New substation automation applications, such as sampled value process buses and synchrophasors, require sampling accuracy of 1 µs or better. The Precision Time Protocol (PTP), IEEE Std 1588, achieves this level of performance and integrates well into Ethernet based substation networks. This paper takes a systematic approach to the performance evaluation of commercially available PTP devices (grandmaster, slave, transparent and boundary clocks) from a variety of manufacturers. The ``error budget'' is set by the performance requirements of each application. The ``expenditure'' of this error budget by each component is valuable information for a system designer. The component information is used to design a synchronization system that meets the overall functional requirements. The quantitative performance data presented shows that this testing is effective and informative. Results from testing PTP performance in the presence of sampled value process bus traffic demonstrate the benefit of a ``bottom up'' component testing approach combined with ``top down'' system verification tests. A test method that uses a precision Ethernet capture card, rather than dedicated PTP test sets, to determine the Correction Field Error of transparent clocks is presented. This test is particularly relevant for highly loaded Ethernet networks with stringent timing requirements. The methods presented can be used for development purposes by manufacturers, or by system integrators for acceptance testing. A sampled value process bus was used as the test application for the systematic approach described in this paper. The test approach was applied, components were selected, and the system performance verified to meet the application's requirements. Systematic testing, as presented in this paper, is applicable to a range of industries that use, rather than develop, PTP for time transfer.

Performance analysis of IEC 61850 sampled value process bus networks

Process bus networks are the next stage in the evolution of substation design, bringing digital technology to the high voltage switchyard. Benefits of process buses include facilitating the use of Non-Conventional Instrument Transformers, improved disturbance recording and phasor measurement and the removal of costly, and potentially hazardous, copper cabling from substation switchyards and control rooms. This paper examines the role a process bus plays in an IEC 61850 based Substation Automation System. Measurements taken from a process bus substation are used to develop an understanding of the network characteristics of "whole of substation" process buses. The concept of "coherent transmission" is presented and the impact of this on Ethernet switches is examined. Experiments based on substation observations are used to investigate in detail the behavior of Ethernet switches with sampled value traffic. Test methods that can be used to assess the adequacy of a network are proposed, and examples of the application and interpretation of these tests are provided. Once sampled value frames are queued by an Ethernet switch the additional delay incurred by subsequent switches is minimal, and this allows their use in switchyards to further reduce communications cabling, without significantly impacting operation. The performance and reliability of a process bus network operating with close to the theoretical maximum number of digital sampling units (merging units or electronic instrument transformers) was investigated with networking equipment from several vendors, and has been demonstrated to be acceptable.

Network interactions and performance of a multi-function IEC 61850 process bus

New substation technology, such as non-conventional instrument transformers,and a need to reduce design and construction costs, are driving the adoption of Ethernet based digital process bus networks for high voltage substations. Protection and control applications can share a process bus, making more efficient use of the network infrastructure. This paper classifies and defines performance requirements for the protocols used in a process bus on the basis of application. These include GOOSE, SNMP and IEC 61850-9-2 sampled values. A method, based on the Multiple Spanning Tree Protocol (MSTP) and virtual local area networks, is presented that separates management and monitoring traffic from the rest of the process bus. A quantitative investigation of the interaction between various protocols used in a process bus is described. These tests also validate the effectiveness of the MSTP based traffic segregation method. While this paper focusses on a substation automation network, the results are applicable to other real-time industrial networks that implement multiple protocols. High volume sampled value data and time-critical circuit breaker tripping commands do not interact on a full duplex switched Ethernet network, even under very high network load conditions. This enables an efficient digital network to replace a large number of conventional analog connections between control rooms and high voltage switchyards.

Australia leads with process bus

Powerlink Queensland has undertaken an aggressive program of research, development and implementation of IEC 61850-based system solutions. The intent is to move towards an IEC 61850 process bus using a two-step approach.

Common DC link in residential LV network to improve the penetration level of Small-Scale Embedded Generators

This paper presents a new approach for network upgrading to improve the penetration level of Small Scale Generators in residential feeders. In this paper, it is proposed that a common DC link can be added to LV network to alleviate the negative impact of increased export power on AC lines, allowing customers to inject their surplus power with no restrictions to the common DC link. In addition, it is shown that the proposed approach can be a pathway from current AC network to future DC network.

Saturated core high-temperature superconducting fault current limiters as an alternative to conventional series reactors in a distribution grid

Series reactors are used in distribution grids to reduce the short-circuit fault level. Some of the disadvantages of the application of these devices are the voltage drop produced across the reactor and the steep front rise of the transient recovery voltage (TRV), which generally exceeds the rating of the associated circuit breaker. Simulations were performed to compare the characteristics of a saturated core High-Temperature Superconducting Fault Current Limiter (HTS FCL) and a series reactor. The design of the HTS FCL was optimized using the evolutionary algorithm. The resulting Pareto frontier curve of optimum solution is presented in this paper. The results show that the steady-state impedance of an HTS FCL is significantly lower than that of a series reactor for the same level of fault current limiting. Tests performed on a prototype 11 kV HTS FCL confirm the theoretical results. The respective transient recovery voltages (TRV) of the HTS FCL and an air core reactor of comparable fault current limiting capability are also determined. The results show that the saturated core HTS FCL has a significantly lower effect on the rate of rise of the circuit breaker TRV as compared to the air core reactor. The simulations results are validated with shortcircuit test results.

Assessment of real-time networks and timing for process bus applications

Widespread adoption by electricity utilities of Non-Conventional Instrument Transformers, such as optical or capacitive transducers, has been limited due to the lack of a standardised interface and multi-vendor interoperability. Low power analogue interfaces are being replaced by IEC 61850 9 2 and IEC 61869 9 digital interfaces that use Ethernet networks for communication. These ‘process bus’ connections achieve significant cost savings by simplifying connections between switchyard and control rooms; however the in-service performance when these standards are employed is largely unknown. The performance of real-time Ethernet networks and time synchronisation was assessed using a scale model of a substation automation system. The test bed was constructed from commercially available timing and protection equipment supplied by a range of vendors. Test protocols have been developed to thoroughly evaluate the performance of Ethernet networks and network based time synchronisation. The suitability of IEEE Std 1588 Precision Time Protocol (PTP) as a synchronising system for sampled values was tested in the steady state and under transient conditions. Similarly, the performance of hardened Ethernet switches designed for substation use was assessed under a range of network operating conditions. This paper presents test methods that use a precision Ethernet capture card to accurately measure PTP and network performance. These methods can be used for product selection and to assess ongoing system performance as substations age. Key findings on the behaviour of multi-function process bus networks are presented. System level tests were performed using a Real Time Digital Simulator and transformer protection relay with sampled value and Generic Object Oriented Substation Events (GOOSE) capability. These include the interactions between sampled values, PTP and GOOSE messages. Our research has demonstrated that several protocols can be used on a shared process bus, even with very high network loads. This should provide confidence that this technology is suitable for transmission substations.

Benefits and issues for bus travel time estimation and prediction

Bus travel time estimation and prediction are two important modelling approaches which could facilitate transit users in using and transit providers in managing the public transport network. Bus travel time estimation could assist transit operators in understanding and improving the reliability of their systems and attracting more public transport users. On the other hand, bus travel time prediction is an important component of a traveller information system which could reduce the anxiety and stress for the travellers. This paper provides an insight into the characteristic of bus in traffic and the factors that influence bus travel time. A critical overview of the state-of-the-art in bus travel time estimation and prediction is provided and the needs for research in this important area are highlighted. The possibility of using Vehicle Identification Data (VID) for studying the relationship between bus and cars travel time is also explored.

Bus and car travel time on urban networks : integrating Bluetooth and bus vehicle identification data

Travel time in an important transport performance indicator. Different modes of transport (buses and cars) have different mechanical and operational characteristics, resulting in significantly different travel behaviours and complexities in multimodal travel time estimation on urban networks. This paper explores the relationship between bus and car travel time on urban networks by utilising the empirical Bluetooth and Bus Vehicle Identification data from Brisbane. The technologies and issues behind the two datasets are studied. After cleaning the data to remove outliers, the relationship between not-in-service bus and car travel time and the relationship between in-service bus and car travel time are discussed. The travel time estimation models reveal that the not-in-service bus travel time are similar to the car travel time and the in-service bus travel time could be used to estimate car travel time during off-peak hours

A microscopic simulation model to estimate Bus Rapid Transit (BRT) station service capacity with mixed stopping and non-stopping bus operation

Bus Rapid Transit (BRT) station is the interface between passenger and service. The station is crucial to line operation as it is typically the only location where buses can pass each other. Congestion may occur here when buses maneuvering into and out of the platform lane interfere with bus flow, or when a queue of buses forms upstream of the platform lane blocking the passing lane. However, some systems include operation where express buses pass the critical station, resulting in a proportion of non stopping buses. It is important to understand the operation of the critical busway station under this type of operation, as it affects busway line capacity. This study uses micro simulation to treat the BRT station operation and to analyze the relationship between station Limit state bus capacity (B_ls), Total Bus Capacity (B_ttl). First, the simulation model is developed for Limit state scenario and then a mathematical model is defined, calibrated for a specified range of controlled scenarios of mean and coefficient of variation of dwell time. Thereafter, the proposed B_ls model is extended to consider non stopping buses and B_ttlmodel is defined. The proposed models provides better understanding to the BRT line capacity and is useful for transit authorities for designing better BRT operation.