Phased-Mission Analysis for Evaluating the Effectiveness of Aerospace Computing-Systems

Effectiveness evaluation of aerospace fault-tolerant computing systems used in a phased-mission environment is rather tricky and difficult because of the interaction of its several degraded performance levels with the multiple objectives of the mission and the use environment. Part I uses an approach based on multiobjective phased-mission analysis to evaluate the effectiveness of a distributed avionics architecture used in a transport aircraft. Part II views the computing system as a multistate s-coherent structure. Lower bounds on the probabilities of accomplishing various levels of performance are evaluated.

Topological Quantum Computation - An Analysis of an Anyon Model Based on Quantum Double Symmetries

There exists various suggestions for building a functional and a fault-tolerant large-scale quantum computer. Topological quantum computation is a more exotic suggestion, which makes use of the properties of quasiparticles manifest only in certain two-dimensional systems. These so called anyons exhibit topological degrees of freedom, which, in principle, can be used to execute quantum computation with intrinsic fault-tolerance. This feature is the main incentive to study topological quantum computation. The objective of this thesis is to provide an accessible introduction to the theory. In this thesis one has considered the theory of anyons arising in two-dimensional quantum mechanical systems, which are described by gauge theories based on so called quantum double symmetries. The quasiparticles are shown to exhibit interactions and carry quantum numbers, which are both of topological nature. Particularly, it is found that the addition of the quantum numbers is not unique, but that the fusion of the quasiparticles is described by a non-trivial fusion algebra. It is discussed how this property can be used to encode quantum information in a manner which is intrinsically protected from decoherence and how one could, in principle, perform quantum computation by braiding the quasiparticles. As an example of the presented general discussion, the particle spectrum and the fusion algebra of an anyon model based on the gauge group S_3 are explicitly derived. The fusion algebra is found to branch into multiple proper subalgebras and the simplest one of them is chosen as a model for an illustrative demonstration. The different steps of a topological quantum computation are outlined and the computational power of the model is assessed. It turns out that the chosen model is not universal for quantum computation. However, because the objective was a demonstration of the theory with explicit calculations, none of the other more complicated fusion subalgebras were considered. Studying their applicability for quantum computation could be a topic of further research.

A distributed services based conference planner application using software agents, grid services and web services

This demonstration highlights the applications of our research work i.e. second generation (Scalable Fault Tolerant Agent Grooming Environment - SAGE) Multi Agent System, Integration of Software Agents and Grid Computing and Autonomous Agent Architecture in the Agent Platform. It is a conference planner application that uses collaborative effort of services deployed geographically wide in different technologies i.e. Software Agents, Grid computing and Web services to perform useful tasks as required. Copyright 2005 ACM.

An efficient and light-weight multi-tasking model to achieve Intra-Agent concurrency for SAGE

Multi-agent systems implicate a high degree of concurrency at both the Inter- and Intra-Agent levels. Scalable, fault tolerant, Agent Grooming Environment (SAGE), the second generation, FIPA compliant MAS requires a built in mechanism to achieve both the Inter- and Intra-Agent concurrency. This paper dilates upon an attempt to provide a reliable, efficient and light-weight solution to provide intra-agent concurrency with-in the internal agent architecture of SAGE. It addresses the issues related to using the JAVA threading model to provide this level of concurrency to the agent and provides an alternative approach that is based on an eventdriven, concurrent and user-scalable multi-tasking model for the agent's internal model. The findings of this paper show that our proposed approach is suitable for providing an efficient and lightweight concurrent task model for SA GE and considerably outweighs the performance of multithreaded tasking model based on JAVA in terms of throughput and efficiency. This has been illustrated using the practical implementation and evaluation of both models. © 2004 IEEE.

A hybrid agent architecture for modeling autonomous agents in SAGE

This paper highlights the Hybrid agent construction model being developed that allows the description and development of autonomous agents in SAGE (Scalable, fault Tolerant Agent Grooming Environment) - a second generation FIPA-Compliant Multi-Agent system. We aim to provide the programmer with a generic and well defined agent architecture enabling the development of sophisticated agents on SAGE, possessing the desired properties of autonomous agents - reactivity, pro-activity, social ability and knowledge based reasoning. © Springer-Verlag Berlin Heidelberg 2005.

FREP: A Soft-Error Resilient Pipelined RISC Architecture

Soft error has become one of the major areas of attention with the device scaling and large scale integration. Lot of variants for superscalar architecture were proposed with focus on program re-execution, thread re-execution and instruction re-execution. In this paper we proposed a fault tolerant micro-architecture of pipelined RISC. The proposed architecture, Floating Resources Extended pipeline (FREP), re-executes the instructions using extended pipeline stages. The instructions are re-executed by hybrid architecture with a suitable combination of space and time redundancy.

Energy-efficient redundant execution for chip multiprocessors

Relentless CMOS scaling coupled with lower design tolerances is making ICs increasingly susceptible to wear-out related permanent faults and transient faults, necessitating on-chip fault tolerance in future chip microprocessors (CMPs). In this paper, we describe a power-efficient architecture for redundant execution on chip multiprocessors (CMPs) which when coupled with our per-core dynamic voltage and frequency scaling (DVFS) algorithm significantly reduces the energy overhead of redundant execution without sacrificing performance. Our evaluation shows that this architecture has a performance overhead of only 0.3% and consumes only 1.48 times the energy of a non-fault-tolerant baseline.

A Hybrid Five-Level Inverter With Common-Mode Voltage Elimination Having Single Voltage Source for IM Drive Applications

A new hybrid five-level inverter topology with common-mode voltage (CMV) elimination for induction motor drive is proposed in this paper. This topology has only one dc source, and different voltage levels are generated by using this voltage source along with floating capacitors charged to asymmetrical voltage levels. The pulsewidth modulation (PWM) scheme employed in this topology balances the capacitor voltages at the required levels at any power factor and modulation index while eliminating the CMV. This inverter has good fault-tolerant capability as it can be operated in three-or two-level mode with CMV elimination, in case of any failure in the H-bridges. More voltage levels with CMV elimination can be realized from this topology but only in a limited range of modulation index and power factor. Extensive simulation is done to validate the PWM technique for CMV elimination and balancing of the capacitor voltages. The experimental verification of the proposed inverter-fed induction motor is carried out in the linear modulation and overmodulation regions. The steady-state and transient operations of the drive are verified. The dynamics of the capacitor voltage balancing is also tested. The experimental results demonstrate that the proposed topology can be considered for industrial drive applications.

On the secret key capacity of the harary graph PIN model

A pairwise independent network (PIN) model consists of pairwise secret keys (SKs) distributed among m terminals. The goal is to generate, through public communication among the terminals, a group SK that is information-theoretically secure from an eavesdropper. In this paper, we study the Harary graph PIN model, which has useful fault-tolerant properties. We derive the exact SK capacity for a regular Harary graph PIN model. Lower and upper bounds on the fault-tolerant SK capacity of the Harary graph PIN model are also derived.

Failure detectors and communication efficiency in the crash and general omisión failure models

122 p.

Lattice quantum codes and exotic topological phases of matter

This thesis addresses whether it is possible to build a robust memory device for quantum information. Many schemes for fault-tolerant quantum information processing have been developed so far, one of which, called topological quantum computation, makes use of degrees of freedom that are inherently insensitive to local errors. However, this scheme is not so reliable against thermal errors. Other fault-tolerant schemes achieve better reliability through active error correction, but incur a substantial overhead cost. Thus, it is of practical importance and theoretical interest to design and assess fault-tolerant schemes that work well at finite temperature without active error correction.

In this thesis, a three-dimensional gapped lattice spin model is found which demonstrates for the first time that a reliable quantum memory at finite temperature is possible, at least to some extent. When quantum information is encoded into a highly entangled ground state of this model and subjected to thermal errors, the errors remain easily correctable for a long time without any active intervention, because a macroscopic energy barrier keeps the errors well localized. As a result, stored quantum information can be retrieved faithfully for a memory time which grows exponentially with the square of the inverse temperature. In contrast, for previously known types of topological quantum storage in three or fewer spatial dimensions the memory time scales exponentially with the inverse temperature, rather than its square.

This spin model exhibits a previously unexpected topological quantum order, in which ground states are locally indistinguishable, pointlike excitations are immobile, and the immobility is not affected by small perturbations of the Hamiltonian. The degeneracy of the ground state, though also insensitive to perturbations, is a complicated number-theoretic function of the system size, and the system bifurcates into multiple noninteracting copies of itself under real-space renormalization group transformations. The degeneracy, the excitations, and the renormalization group flow can be analyzed using a framework that exploits the spin model's symmetry and some associated free resolutions of modules over polynomial algebras.

Quantum error correction with biased noise

Quantum computing offers powerful new techniques for speeding up the calculation of many classically intractable problems. Quantum algorithms can allow for the efficient simulation of physical systems, with applications to basic research, chemical modeling, and drug discovery; other algorithms have important implications for cryptography and internet security.

At the same time, building a quantum computer is a daunting task, requiring the coherent manipulation of systems with many quantum degrees of freedom while preventing environmental noise from interacting too strongly with the system. Fortunately, we know that, under reasonable assumptions, we can use the techniques of quantum error correction and fault tolerance to achieve an arbitrary reduction in the noise level.

In this thesis, we look at how additional information about the structure of noise, or "noise bias," can improve or alter the performance of techniques in quantum error correction and fault tolerance. In Chapter 2, we explore the possibility of designing certain quantum gates to be extremely robust with respect to errors in their operation. This naturally leads to structured noise where certain gates can be implemented in a protected manner, allowing the user to focus their protection on the noisier unprotected operations.

In Chapter 3, we examine how to tailor error-correcting codes and fault-tolerant quantum circuits in the presence of dephasing biased noise, where dephasing errors are far more common than bit-flip errors. By using an appropriately asymmetric code, we demonstrate the ability to improve the amount of error reduction and decrease the physical resources required for error correction.

In Chapter 4, we analyze a variety of protocols for distilling magic states, which enable universal quantum computation, in the presence of faulty Clifford operations. Here again there is a hierarchy of noise levels, with a fixed error rate for faulty gates, and a second rate for errors in the distilled states which decreases as the states are distilled to better quality. The interplay of of these different rates sets limits on the achievable distillation and how quickly states converge to that limit.

Uma infraestrutura para monitoramento de sistemas cientes do contexto.

Aplicações ubíquas e pervasivas são cientes do contexto dos recursos utilizados no que diz respeito à disponibilidade e qualidade. Esta classe de aplicações pode se beneficiar de mecanismos para descobrir recursos que atendam aos requisitos não-funcionais desejados, e mecanismos para monitorar a qualidade destes recursos. Neste trabalho é proposta uma arquitetura para dois serviços que deveriam ser incluídos na infra-estrutura de suporte a ser utilizada pelas aplicações mencionadas: um Serviço de Contexto, que provê acesso a informações de contexto, e um Serviço de Descoberta, que permite a descoberta dinâmica de recursos, levando em conta restrições de contexto a serem satisfeitas. Estes serviços se apóiam em Agentes de Recursos, que efetivamente monitoram os recursos e sensores. Uma implementação de referência foi desenvolvida, oferecendo os serviços mencionados na forma de Serviços Web e implementando os Agentes de Recursos empregando um padrão de projeto simples. Para avaliar os serviços estes foram utilizados como infra-estrutura para o desenvolvimento de um sistema tolerante a falhas e uma aplicação de assistência domiciliar remota (tele-saúde). O desempenho dos serviços também foi avaliado.

The design algorithm of an associative memory neural network

A design algorithm of an associative memory neural network is proposed. The benefit of this design algorithm is to make the designed associative memory model can implement the hoped situation. On the one hand, the designed model has realized the nonlinear association of infinite value pattern from n dimension space to m dimension space. The result has improved the ones of some old associative memory neural network. On the other hand, the memory samples are in the centers of the fault-tolerant. In average significance the radius of the memory sample fault-tolerant field is maximum.