Design of nanoparticle systems with antimicrobial properties

Infektiöse Komplikationen im Zusammenhang mit Implantaten stellen einen Großteil aller Krankenhausinfektionen dar und treiben die Gesundheitskosten signifikant in die Höhe. Die bakterielle Kolonisation von Implantatoberflächen zieht schwerwiegende medizinische Konsequenzen nach sich, die unter Umständen tödlich verlaufen können. Trotz umfassender Forschungsaktivitäten auf dem Gebiet der antibakteriellen Oberflächenbeschichtungen ist das Spektrum an wirksamen Substanzen aufgrund der Anpassungsfähigkeit und Ausbildung von Resistenzen verschiedener Mikroorganismen eingeschränkt. Die Erforschung und Entwicklung neuer antibakterieller Materialien ist daher von fundamentaler Bedeutung.rnIn der vorliegenden Arbeit wurden auf der Basis von Polymernanopartikeln und anorganischen/polymeren Verbundmaterialien verschiedene Systeme als Alternative zu bestehenden antibakteriellen Oberflächenbeschichtungen entwickelt. Polymerpartikel finden Anwendung in vielen verschiedenen Bereichen, da sowohl Größe als auch Zusammensetzung und Morphologie vielseitig gestaltet werden können. Mit Hilfe der Miniemulsionstechnik lassen sich u. A. funktionelle Polymernanopartikel im Größenbereich von 50-500 nm herstellen. Diese wurde im ersten System angewendet, um PEGylierte Poly(styrol)nanopartikel zu synthetisieren, deren anti-adhesives Potential in Bezug auf P. aeruginosa evaluiert wurde. Im zweiten System wurden sog. kontakt-aktive kolloide Dispersionen entwickelt, welche bakteriostatische Eigenschaften gegenüber S. aureus zeigten. In Analogie zum ersten System, wurden Poly(styrol)nanopartikel in Copolymerisation in Miniemulsion mit quaternären Ammoniumgruppen funktionalisiert. Als Costabilisator diente das zuvor quaternisierte, oberflächenaktive Monomer (2-Dimethylamino)ethylmethacrylat (qDMAEMA). Die Optimierung der antibakteriellen Eigenschaften wurde im nachfolgenden System realisiert. Hierbei wurde das oberflächenaktive Monomer qDMAEMA zu einem oberflächenaktiven Polyelektrolyt polymerisiert, welcher unter Anwendung von kombinierter Miniemulsions- und Lösemittelverdampfungstechnik, in entsprechende Polyelektrolytnanopartikel umgesetzt wurde. Infolge seiner oberflächenaktiven Eigenschaften, ließen sich aus dem Polyelektrolyt stabile Partikeldispersionen ohne Zusatz weiterer Tenside ausbilden. Die selektive Toxizität der Polyelektrolytnanopartikel gegenüber S. aureus im Unterschied zu Körperzellen, untermauert ihr vielversprechendes Potential als bakterizides, kontakt-aktives Reagenz. rnAufgrund ihrer antibakteriellen Eigenschaften wurden ZnO Nanopartikel ausgewählt und in verschiedene Freisetzungssysteme integriert. Hochdefinierte eckige ZnO Nanokristalle mit einem mittleren Durchmesser von 23 nm wurden durch thermische Zersetzung des Precursormaterials synthetisiert. Durch die nachfolgende Einkapselung in Poly(L-laktid) Latexpartikel wurden neue, antibakterielle und UV-responsive Hybridnanopartikel entwickelt. Durch die photokatalytische Aktivierung von ZnO mittels UV-Strahlung wurde der Abbau der ZnO/PLLA Hybridnanopartikel signifikant von mehreren Monaten auf mehrere Wochen verkürzt. Die Photoaktivierung von ZnO eröffnet somit die Möglichkeit einer gesteuerten Freisetzung von ZnO. Im nachfolgenden System wurden dünne Verbundfilme aus Poly(N-isopropylacrylamid)-Hydrogelschichten mit eingebetteten ZnO Nanopartikeln hergestellt, die als bakterizide Oberflächenbeschichtungen gegen E. coli zum Einsatz kamen. Mit minimalem Gehalt an ZnO zeigten die Filme eine vergleichbare antibakterielle Aktivität zu Silber-basierten Beschichtungen. Hierbei lässt sich der Gehalt an ZnO relativ einfach über die Filmdicke einstellen. Weiterhin erwiesen sich die Filme mit bakteriziden Konzentrationen an ZnO als nichtzytotoxisch gegenüber Körperzellen. Zusammenfassend wurden mehrere vielversprechende antibakterielle Prototypen entwickelt, die als potentielle Implantatbeschichtungen auf die jeweilige Anwendung weiterhin zugeschnitten und optimiert werden können.

Physiologic cold shock of Moraxella catarrhalis affects the expression of genes involved in the iron acquisition, serum resistance and immune evasion

Background Moraxella catarrhalis, a major nasopharyngeal pathogen of the human respiratory tract, is exposed to rapid downshifts of environmental temperature when humans breathe cold air. It was previously shown that the prevalence of pharyngeal colonization and respiratory tract infections caused by M. catarrhalis are greatest in winter. The aim of this study was to investigate how M. catarrhalis uses the physiologic exposure to cold air to upregulate pivotal survival systems in the pharynx that may contribute to M. catarrhalis virulence. Results A 26°C cold shock induces the expression of genes involved in transferrin and lactoferrin acquisition, and enhances binding of these proteins on the surface of M. catarrhalis. Exposure of M. catarrhalis to 26°C upregulates the expression of UspA2, a major outer membrane protein involved in serum resistance, leading to improved binding of vitronectin which neutralizes the lethal effect of human complement. In contrast, cold shock decreases the expression of Hemagglutinin, a major adhesin, which mediates B cell response, and reduces immunoglobulin D-binding on the surface of M. catarrhalis. Conclusion Cold shock of M. catarrhalis induces the expression of genes involved in iron acquisition, serum resistance and immune evasion. Thus, cold shock at a physiologically relevant temperature of 26°C induces in M. catarrhalis a complex of adaptive mechanisms that enables the bacterium to target their host cellular receptors or soluble effectors and may contribute to enhanced growth, colonization and virulence.

Antimicrobial resistance of Escherichia coli and Enterococcus faecalis in housed laying-hen flocks in Europe

The aim of this study was to determine the potential association between housing type and multiple drug resistance (MDR) in Escherichia coli and Enterococcus faecalis isolates recovered from 283 laying-hen flocks. In each flock, a cloacal swab from four hens was collected and produced 1102 E. coli and 792 E. faecalis isolates. Broth microdilution was used to test susceptibility to antimicrobials. Country and housing type interacted differently with the MDR levels of both species. In the E. coli model, housing in a raised-floor system was associated with an increased risk of MDR compared to the conventional battery system [ odds ratio (OR) 2.12, 95% confidence interval (CI) 1.13-3.97)]. In the E. faecalis model the MDR levels were lower in free-range systems than in conventional battery cages (OR 0.51, 95% CI 0.27-0.94). In Belgium, ceftiofur-resistant E. coli isolates were more numerous than in the other countries.

Artemisinin, an endoperoxide antimalarial, disrupts the hemoglobin catabolism and heme detoxification systems in malarial parasite

Endoperoxide antimalarials based on the ancient Chinese drug Qinghaosu (artemisinin) are currently our major hope in the fight against drug-resistant malaria. Rational drug design based on artemisinin and its analogues is slow as the mechanism of action of these antimalarials is not clear. Here we report that these drugs, at least in part, exert their effect by interfering with the plasmodial hemoglobin catabolic pathway and inhibition of heme polymerization. In an in vitro experiment we observed inhibition of digestive vacuole proteolytic activity of malarial parasite by artemisinin. These observations were further confirmed by ex vivo experiments showing accumulation of hemoglobin in the parasites treated with artemisinin, suggesting inhibition of hemoglobin degradation. We found artemisinin to be a potent inhibitor of heme polymerization activity mediated by Plasmodium yoelii lysates as well as Plasmodium falciparum histidine-rich protein II. Interaction of artemisinin with the purified malarial hemozoin in vitro resulted in the concentration-dependent breakdown of the malaria pigment. Our results presented here may explain the selective and rapid toxicity of these drugs on mature, hemozoin-containing, stages of malarial parasite. Since artemisinin and its analogues appear to have similar molecular targets as chloroquine despite having different structures, they can potentially bypass the quinoline resistance machinery of the malarial parasite, which causes sublethal accumulation of these drugs in resistant strains.

Understanding acquired resistance to Lapatinib in breast cancer cells

Signaling through epidermal growth factor receptor (EGFR/ErbB) family members plays a very important role in regulating proliferation, development, and malignant transformation of mammary epithelial cells. ErbB family members are often over-expressed in human breast carcinomas. Lapatinib is an ErbB1 and ErbB2 tyrosine kinase inhibitor that has been shown to have anti-proliferative effects in breast and lung cancer cells. Cells treated with Lapatinib undergo G1 phase arrest, followed by apoptosis. Lapatinib has been approved for clinical use, though patients have developed resistance to the drug, as seen previously with other EGFR inhibitors. Moreover, the therapeutic efficacy varies significantly within the patient population, and the mechanism of drug sensitivity is not fully understood. Expression levels of ErbB2 are used as a prognostic marker for Lapatinib response; however, even among breast tumor cell lines that express similar levels of ErbB2 there is marked difference in their proliferative responses to Lapatinib. To understand the mechanisms of acquired resistance, we established a cell line SkBr3-R that is resistant to Lapatinib, from a Lapatinib-sensitive breast tumor cell line, SkBr3. We have characterized the cell lines and demonstrated that Lapatinib resistance in our system is not facilitated by receptor-level activity or by previously known mutations in the ErbB receptors. Significant changes were observed in cell proliferation, cell migration, cell cycle and cell death between the Lapatinib resistant SkBr3-R and sensitive SkBr3 cell lines. Recent studies have suggested STAT3 is upregulated in Lapatinib resistant tumors in association with ErbB signaling. We investigated the role that STAT3 may play in Lapatinib resistance and discovered higher STAT3 activity in these resistant cells. In addition, transcriptional profiling indicated higher expression of STAT3 target genes, as well as of other genes that promote survival. The gene array data also revealed cell cycle regulators and cell adhesion/junction component genes as possible mediator of Lapatinib resistance. Altogether, this study has identified several possible mechanisms of Lapatinib resistance.

Biological diversity of prokaryotic type IV secretion systems.

Type IV secretion systems (T4SS) translocate DNA and protein substrates across prokaryotic cell envelopes generally by a mechanism requiring direct contact with a target cell. Three types of T4SS have been described: (i) conjugation systems, operationally defined as machines that translocate DNA substrates intercellularly by a contact-dependent process; (ii) effector translocator systems, functioning to deliver proteins or other macromolecules to eukaryotic target cells; and (iii) DNA release/uptake systems, which translocate DNA to or from the extracellular milieu. Studies of a few paradigmatic systems, notably the conjugation systems of plasmids F, R388, RP4, and pKM101 and the Agrobacterium tumefaciens VirB/VirD4 system, have supplied important insights into the structure, function, and mechanism of action of type IV secretion machines. Information on these systems is updated, with emphasis on recent exciting structural advances. An underappreciated feature of T4SS, most notably of the conjugation subfamily, is that they are widely distributed among many species of gram-negative and -positive bacteria, wall-less bacteria, and the Archaea. Conjugation-mediated lateral gene transfer has shaped the genomes of most if not all prokaryotes over evolutionary time and also contributed in the short term to the dissemination of antibiotic resistance and other virulence traits among medically important pathogens. How have these machines adapted to function across envelopes of distantly related microorganisms? A survey of T4SS functioning in phylogenetically diverse species highlights the biological complexity of these translocation systems and identifies common mechanistic themes as well as novel adaptations for specialized purposes relating to the modulation of the donor-target cell interaction.

Biological diversity of prokaryotic type IV secretion systems.

Type IV secretion systems (T4SS) translocate DNA and protein substrates across prokaryotic cell envelopes generally by a mechanism requiring direct contact with a target cell. Three types of T4SS have been described: (i) conjugation systems, operationally defined as machines that translocate DNA substrates intercellularly by a contact-dependent process; (ii) effector translocator systems, functioning to deliver proteins or other macromolecules to eukaryotic target cells; and (iii) DNA release/uptake systems, which translocate DNA to or from the extracellular milieu. Studies of a few paradigmatic systems, notably the conjugation systems of plasmids F, R388, RP4, and pKM101 and the Agrobacterium tumefaciens VirB/VirD4 system, have supplied important insights into the structure, function, and mechanism of action of type IV secretion machines. Information on these systems is updated, with emphasis on recent exciting structural advances. An underappreciated feature of T4SS, most notably of the conjugation subfamily, is that they are widely distributed among many species of gram-negative and -positive bacteria, wall-less bacteria, and the Archaea. Conjugation-mediated lateral gene transfer has shaped the genomes of most if not all prokaryotes over evolutionary time and also contributed in the short term to the dissemination of antibiotic resistance and other virulence traits among medically important pathogens. How have these machines adapted to function across envelopes of distantly related microorganisms? A survey of T4SS functioning in phylogenetically diverse species highlights the biological complexity of these translocation systems and identifies common mechanistic themes as well as novel adaptations for specialized purposes relating to the modulation of the donor-target cell interaction.

Signal signature of aboveground-induced resistance upon belowground herbivory in maize

Plants activate local and systemic defence mechanisms upon exposure to stress. This innate immune response is partially regulated by plant hormones, and involves the accumulation of defensive metabolites. Although local defence reactions to herbivores are well studied, less is known about the impact of root herbivory on shoot defence. Here, we examined the effects of belowground infestation by the western corn rootworm Diabrotica virgifera virgifera on aboveground resistance in maize. Belowground herbivory by D. v. virgifera induced aboveground resistance against the generalist herbivore Spodoptera littoralis, and the necrotrophic pathogen Setosphaeria turcica. Furthermore, D. v. virgifera increased shoot levels of 2,4-dihydroxy-7-methoxy-1,4-benzoxazin-3-one (DIMBOA), and primed the induction of chlorogenic acid upon subsequent infestation by S. littoralis. To gain insight into the signalling network behind this below- and aboveground defence interaction, we compiled a set of 32 defence-related genes, which can be used as transcriptional marker systems to detect activities of different hormone-response pathways. Belowground attack by D. v. virgifera triggered an ABA-inducible transcription pattern in the shoot. The quantification of defence hormones showed a local increase in the production of oxylipins after root and shoot infestation by D. v. virgifera and S. littoralis, respectively. On the other hand, ABA accumulated locally and systemically upon belowground attack by D. v. virgifera. Furthermore, D. v. virgifera reduced the aboveground water content, whereas the removal of similar quantities of root biomass had no effect. Our study shows that root herbivory by D. v. virgifera specifically alters the aboveground defence status of a maize, and suggests that ABA plays a role in the signalling network mediating this interaction.

The relationship of mutations in alpha- and beta-tubulin to microtubule assembly and anti-mitotic drug resistance

The mechanisms responsible for anti-cancer drug (including Taxol) treatment failure have not been identified. In cell culture model systems, many β-tubulin, but very few α-tubulin, mutations have been associated with resistance to Taxol. To test what, if any, mutations in α-tubulin can cause resistance, we transfected a randomly mutagenized α-tubulin cDNA into Chinese hamster ovary (CHO) cells and isolated drug resistant cell lines. A total of 12 mutations were identified in this way and all of them were confirmed to confer Taxol resistance. Furthermore, all cells expressing mutant α-tubulin had less microtubule polymer. Some cells also had abnormal nuclei and enlarged cell bodies. The data indicate that α-tubulin mutations confer Taxol resistance by disrupting microtubule assembly, a mechanism consistent with a large number of previously described β-tubulin mutations. ^ Because α- and β-tubulin are almost identical in their three dimensional structure, we hypothesized that mutations discovered in one subunit, when introduced into the other, would produce similar effects on microtubule assembly and drug resistance. 9 α- and 2 β-tubulin mutations were tested. The results were complex. Some mutations produced similar changes in microtubule assembly and drug resistance irrespective of the subunit in which they were introduced, but others produced opposite effects. Still one mutation produced resistance when present in one subunit, yet had no effect when present on the other; and one mutation that produced Taxol resistance when present in α-tubulin, resulted in assembly-defective tubulin when it was present in β-tubulin. The results suggest that in most cases, the same amino acid modification in α- and β-tubulin affects the microtubule structure and assembly in a similar way. ^ Finally, we tested whether three β-tubulin mutations found in patient tumors could confer resistance to Taxol by recreating the mutations in a β-tubulin cDNA and transfecting it into CHO cells. We found that all three mutations conferred Taxol resistance, but to different extents. Again, microtubule assembly in the transfectants was disrupted, suggesting that mutations in β-tubulin are a potential problem in cancer therapeutics. ^

Análisis comparativo de procedimientos para la medición de las gemas y evaluación de su influencia en la determinación de las propiedades mecánicas de la madera de Pinus sylvestris L. de gran escuadría. Comparison of wanes measurement systems to evaluate their influence on the mechanical properties of large cross section timber of Pinus sylvestris L.

Las gemas se evalúan mediante la norma de clasificación visual (UNE 56544), pero su aplicación en estructuras existentes y grandes escuadrías resulta poco eficaz y conduce a estimaciones demasiado conservadoras. Este trabajo analiza la influencia de las gemas comparando la resistencia de piezas con gemas y piezas correctamente escuadradas. Se han analizado 218 piezas de pino silvestre con dimensiones nominales 150 x 200 x 4.200 mm, de las que 102 presentaban una gema completa a lo largo de toda su longitud y el resto estaban correctamente escuadradas. En las piezas con gema se ha medido la altura de la sección cada 30 cm (altura en cada cara y altura máxima). Para determinar la resistencia se han ensayado todas las piezas de acuerdo a la norma EN 408. Se ha comparado la resistencia obtenida para las piezas con gema, diferenciando si la gema se encuentra en el borde comprimido o en el borde traccionado, con las piezas escuadradas. Puede concluirse que la presencia de gemas disminuye la resistencia excepto si la gema se encuentra en el borde traccionado, en cuyo caso los resultados obtenidos han sido similares a los de las piezas escuadradas. The wanes on structural timber are evaluated according to the visual grading standard (UNE 56544), but its application on existing structures and large cross sections is ineffective and leads to conservative estimations. This paper analyzes the influence of the wanes by comparing the resistance of pieces with wanes and square pieces. 218 pieces of Scotch pine with nominal dimensions 150 x 200 x 4200 mm have been analyzed, 102 of them had a complete wane along its length and the rest were properly squared. The height of the cross section was measured every 30 cm (the height on each side and the maximum height) for the pieces with wane. The bending strength of all the pieces was obtained according to the EN 408 standard. The bending strength of the pieces with wane has been compared with the strength of the squared pieces, taking into account if the wane is positioned on the compressed edge or on the tensioned edge. It can be concluded that the bending strength of the pieces with wanes is lower than the one of squared pieces, except if the wanes are on the tensioned edge of the beam.

Testing of fluorescent DC lamps for Solar Home Systems

With the advent of the Universal Technical Standard for Solar Home Systems, procedures to test the compliance of SHS fluorescent lamps with the standard have been developed. Definition of the laboratory testing procedures is a necessary step in any lamp quality assurance procedure. Particular attention has been paid to test simplicity and to affordability, in order to facilitate local application of the testing procedures, for example by the organisations which carry out electrification programmes. The set of test procedures has been applied to a representative collection of 42 lamps from many different countries, directly acquired in the current photovoltaic rural electrification market. Tests apply to: lamp resistance under normal operating conditions; lamp reliability under extreme conditions; under abnormal conditions; and lamp luminosity. Results are discussed and some recommendations for updating the relevant standard are given. The selected technical standard, together with the proposed testing procedures, form the basis of a complete quality assurance tool that can be applied locally in normal electrical laboratories. Full testing of a lamp requires less than one month, which is very reasonable on the context of quality assurance programmes

LED bulb lamps technical specification and testing procedure for solar home systems.

With the consolidation of the new solid state lighting LEOs devices, te5t1n9 the compliance 01 lamps based on this technology lor Solar Home Systems (SHS) have been analyzed. The definition of the laboratory procedures to be used with final products 15 a necessary step in arder to be able to assure the quality of the lamps prior to be installed [1]. As well as with CFL technology. particular attention has been given to simplicity and technical affordability in arder to facilitate the implementation of the test with basie and simple laboratory too15 even on the same SHS electrification program locations. The block of test procedures has been applied to a set of 14 low-cost lamps. They apply to lamp resistance, reliability and performance under normal, extreme and abnormal operating conditions as a simple but complete quality meter tool 01 any LEO bulb.

Side-Channel Attack Protection Techniques in FPGA Systems using Enhanced Dual-Rail Solutions

Esta tesis doctoral se centra principalmente en técnicas de ataque y contramedidas relacionadas con ataques de canal lateral (SCA por sus siglas en inglés), que han sido propuestas dentro del campo de investigación académica desde hace 17 años. Las investigaciones relacionadas han experimentado un notable crecimiento en las últimas décadas, mientras que los diseños enfocados en la protección sólida y eficaz contra dichos ataques aún se mantienen como un tema de investigación abierto, en el que se necesitan iniciativas más confiables para la protección de la información persona de empresa y de datos nacionales. El primer uso documentado de codificación secreta se remonta a alrededor de 1700 B.C., cuando los jeroglíficos del antiguo Egipto eran descritos en las inscripciones. La seguridad de la información siempre ha supuesto un factor clave en la transmisión de datos relacionados con inteligencia diplomática o militar. Debido a la evolución rápida de las técnicas modernas de comunicación, soluciones de cifrado se incorporaron por primera vez para garantizar la seguridad, integridad y confidencialidad de los contextos de transmisión a través de cables sin seguridad o medios inalámbricos. Debido a las restricciones de potencia de cálculo antes de la era del ordenador, la técnica de cifrado simple era un método más que suficiente para ocultar la información. Sin embargo, algunas vulnerabilidades algorítmicas pueden ser explotadas para restaurar la regla de codificación sin mucho esfuerzo. Esto ha motivado nuevas investigaciones en el área de la criptografía, con el fin de proteger el sistema de información ante sofisticados algoritmos. Con la invención de los ordenadores se ha acelerado en gran medida la implementación de criptografía segura, que ofrece resistencia eficiente encaminada a obtener mayores capacidades de computación altamente reforzadas. Igualmente, sofisticados cripto-análisis han impulsado las tecnologías de computación. Hoy en día, el mundo de la información ha estado involucrado con el campo de la criptografía, enfocada a proteger cualquier campo a través de diversas soluciones de cifrado. Estos enfoques se han fortalecido debido a la unificación optimizada de teorías matemáticas modernas y prácticas eficaces de hardware, siendo posible su implementación en varias plataformas (microprocesador, ASIC, FPGA, etc.). Las necesidades y requisitos de seguridad en la industria son las principales métricas de conducción en el diseño electrónico, con el objetivo de promover la fabricación de productos de gran alcance sin sacrificar la seguridad de los clientes. Sin embargo, una vulnerabilidad en la implementación práctica encontrada por el Prof. Paul Kocher, et al en 1996 implica que un circuito digital es inherentemente vulnerable a un ataque no convencional, lo cual fue nombrado posteriormente como ataque de canal lateral, debido a su fuente de análisis. Sin embargo, algunas críticas sobre los algoritmos criptográficos teóricamente seguros surgieron casi inmediatamente después de este descubrimiento. En este sentido, los circuitos digitales consisten típicamente en un gran número de celdas lógicas fundamentales (como MOS - Metal Oxide Semiconductor), construido sobre un sustrato de silicio durante la fabricación. La lógica de los circuitos se realiza en función de las innumerables conmutaciones de estas células. Este mecanismo provoca inevitablemente cierta emanación física especial que puede ser medida y correlacionada con el comportamiento interno del circuito. SCA se puede utilizar para revelar datos confidenciales (por ejemplo, la criptografía de claves), analizar la arquitectura lógica, el tiempo e incluso inyectar fallos malintencionados a los circuitos que se implementan en sistemas embebidos, como FPGAs, ASICs, o tarjetas inteligentes. Mediante el uso de la comparación de correlación entre la cantidad de fuga estimada y las fugas medidas de forma real, información confidencial puede ser reconstruida en mucho menos tiempo y computación. Para ser precisos, SCA básicamente cubre una amplia gama de tipos de ataques, como los análisis de consumo de energía y radiación ElectroMagnética (EM). Ambos se basan en análisis estadístico y, por lo tanto, requieren numerosas muestras. Los algoritmos de cifrado no están intrínsecamente preparados para ser resistentes ante SCA. Es por ello que se hace necesario durante la implementación de circuitos integrar medidas que permitan camuflar las fugas a través de "canales laterales". Las medidas contra SCA están evolucionando junto con el desarrollo de nuevas técnicas de ataque, así como la continua mejora de los dispositivos electrónicos. Las características físicas requieren contramedidas sobre la capa física, que generalmente se pueden clasificar en soluciones intrínsecas y extrínsecas. Contramedidas extrínsecas se ejecutan para confundir la fuente de ataque mediante la integración de ruido o mala alineación de la actividad interna. Comparativamente, las contramedidas intrínsecas están integradas en el propio algoritmo, para modificar la aplicación con el fin de minimizar las fugas medibles, o incluso hacer que dichas fugas no puedan ser medibles. Ocultación y Enmascaramiento son dos técnicas típicas incluidas en esta categoría. Concretamente, el enmascaramiento se aplica a nivel algorítmico, para alterar los datos intermedios sensibles con una máscara de manera reversible. A diferencia del enmascaramiento lineal, las operaciones no lineales que ampliamente existen en criptografías modernas son difíciles de enmascarar. Dicho método de ocultación, que ha sido verificado como una solución efectiva, comprende principalmente la codificación en doble carril, que está ideado especialmente para aplanar o eliminar la fuga dependiente de dato en potencia o en EM. En esta tesis doctoral, además de la descripción de las metodologías de ataque, se han dedicado grandes esfuerzos sobre la estructura del prototipo de la lógica propuesta, con el fin de realizar investigaciones enfocadas a la seguridad sobre contramedidas de arquitectura a nivel lógico. Una característica de SCA reside en el formato de las fuentes de fugas. Un típico ataque de canal lateral se refiere al análisis basado en la potencia, donde la capacidad fundamental del transistor MOS y otras capacidades parásitas son las fuentes esenciales de fugas. Por lo tanto, una lógica robusta resistente a SCA debe eliminar o mitigar las fugas de estas micro-unidades, como las puertas lógicas básicas, los puertos I/O y las rutas. Las herramientas EDA proporcionadas por los vendedores manipulan la lógica desde un nivel más alto, en lugar de realizarlo desde el nivel de puerta, donde las fugas de canal lateral se manifiestan. Por lo tanto, las implementaciones clásicas apenas satisfacen estas necesidades e inevitablemente atrofian el prototipo. Por todo ello, la implementación de un esquema de diseño personalizado y flexible ha de ser tomado en cuenta. En esta tesis se presenta el diseño y la implementación de una lógica innovadora para contrarrestar SCA, en la que se abordan 3 aspectos fundamentales: I. Se basa en ocultar la estrategia sobre el circuito en doble carril a nivel de puerta para obtener dinámicamente el equilibrio de las fugas en las capas inferiores; II. Esta lógica explota las características de la arquitectura de las FPGAs, para reducir al mínimo el gasto de recursos en la implementación; III. Se apoya en un conjunto de herramientas asistentes personalizadas, incorporadas al flujo genérico de diseño sobre FPGAs, con el fin de manipular los circuitos de forma automática. El kit de herramientas de diseño automático es compatible con la lógica de doble carril propuesta, para facilitar la aplicación práctica sobre la familia de FPGA del fabricante Xilinx. En este sentido, la metodología y las herramientas son flexibles para ser extendido a una amplia gama de aplicaciones en las que se desean obtener restricciones mucho más rígidas y sofisticadas a nivel de puerta o rutado. En esta tesis se realiza un gran esfuerzo para facilitar el proceso de implementación y reparación de lógica de doble carril genérica. La viabilidad de las soluciones propuestas es validada mediante la selección de algoritmos criptográficos ampliamente utilizados, y su evaluación exhaustiva en comparación con soluciones anteriores. Todas las propuestas están respaldadas eficazmente a través de ataques experimentales con el fin de validar las ventajas de seguridad del sistema. El presente trabajo de investigación tiene la intención de cerrar la brecha entre las barreras de implementación y la aplicación efectiva de lógica de doble carril. En esencia, a lo largo de esta tesis se describirá un conjunto de herramientas de implementación para FPGAs que se han desarrollado para trabajar junto con el flujo de diseño genérico de las mismas, con el fin de lograr crear de forma innovadora la lógica de doble carril. Un nuevo enfoque en el ámbito de la seguridad en el cifrado se propone para obtener personalización, automatización y flexibilidad en el prototipo de circuito de bajo nivel con granularidad fina. Las principales contribuciones del presente trabajo de investigación se resumen brevemente a continuación: Lógica de Precharge Absorbed-DPL logic: El uso de la conversión de netlist para reservar LUTs libres para ejecutar la señal de precharge y Ex en una lógica DPL. Posicionamiento entrelazado Row-crossed con pares idénticos de rutado en redes de doble carril, lo que ayuda a aumentar la resistencia frente a la medición EM selectiva y mitigar los impactos de las variaciones de proceso. Ejecución personalizada y herramientas de conversión automática para la generación de redes idénticas para la lógica de doble carril propuesta. (a) Para detectar y reparar conflictos en las conexiones; (b) Detectar y reparar las rutas asimétricas. (c) Para ser utilizado en otras lógicas donde se requiere un control estricto de las interconexiones en aplicaciones basadas en Xilinx. Plataforma CPA de pruebas personalizadas para el análisis de EM y potencia, incluyendo la construcción de dicha plataforma, el método de medición y análisis de los ataques. Análisis de tiempos para cuantificar los niveles de seguridad. División de Seguridad en la conversión parcial de un sistema de cifrado complejo para reducir los costes de la protección. Prueba de concepto de un sistema de calefacción auto-adaptativo para mitigar los impactos eléctricos debido a la variación del proceso de silicio de manera dinámica. La presente tesis doctoral se encuentra organizada tal y como se detalla a continuación: En el capítulo 1 se abordan los fundamentos de los ataques de canal lateral, que abarca desde conceptos básicos de teoría de modelos de análisis, además de la implementación de la plataforma y la ejecución de los ataques. En el capítulo 2 se incluyen las estrategias de resistencia SCA contra los ataques de potencia diferencial y de EM. Además de ello, en este capítulo se propone una lógica en doble carril compacta y segura como contribución de gran relevancia, así como también se presentará la transformación lógica basada en un diseño a nivel de puerta. Por otra parte, en el Capítulo 3 se abordan los desafíos relacionados con la implementación de lógica en doble carril genérica. Así mismo, se describirá un flujo de diseño personalizado para resolver los problemas de aplicación junto con una herramienta de desarrollo automático de aplicaciones propuesta, para mitigar las barreras de diseño y facilitar los procesos. En el capítulo 4 se describe de forma detallada la elaboración e implementación de las herramientas propuestas. Por otra parte, la verificación y validaciones de seguridad de la lógica propuesta, así como un sofisticado experimento de verificación de la seguridad del rutado, se describen en el capítulo 5. Por último, un resumen de las conclusiones de la tesis y las perspectivas como líneas futuras se incluyen en el capítulo 6. Con el fin de profundizar en el contenido de la tesis doctoral, cada capítulo se describe de forma más detallada a continuación: En el capítulo 1 se introduce plataforma de implementación hardware además las teorías básicas de ataque de canal lateral, y contiene principalmente: (a) La arquitectura genérica y las características de la FPGA a utilizar, en particular la Xilinx Virtex-5; (b) El algoritmo de cifrado seleccionado (un módulo comercial Advanced Encryption Standard (AES)); (c) Los elementos esenciales de los métodos de canal lateral, que permiten revelar las fugas de disipación correlacionadas con los comportamientos internos; y el método para recuperar esta relación entre las fluctuaciones físicas en los rastros de canal lateral y los datos internos procesados; (d) Las configuraciones de las plataformas de pruebas de potencia / EM abarcadas dentro de la presente tesis. El contenido de esta tesis se amplia y profundiza a partir del capítulo 2, en el cual se abordan varios aspectos claves. En primer lugar, el principio de protección de la compensación dinámica de la lógica genérica de precarga de doble carril (Dual-rail Precharge Logic-DPL) se explica mediante la descripción de los elementos compensados a nivel de puerta. En segundo lugar, la lógica PA-DPL es propuesta como aportación original, detallando el protocolo de la lógica y un caso de aplicación. En tercer lugar, dos flujos de diseño personalizados se muestran para realizar la conversión de doble carril. Junto con ello, se aclaran las definiciones técnicas relacionadas con la manipulación por encima de la netlist a nivel de LUT. Finalmente, una breve discusión sobre el proceso global se aborda en la parte final del capítulo. El Capítulo 3 estudia los principales retos durante la implementación de DPLs en FPGAs. El nivel de seguridad de las soluciones de resistencia a SCA encontradas en el estado del arte se ha degenerado debido a las barreras de implantación a través de herramientas EDA convencionales. En el escenario de la arquitectura FPGA estudiada, se discuten los problemas de los formatos de doble carril, impactos parásitos, sesgo tecnológico y la viabilidad de implementación. De acuerdo con estas elaboraciones, se plantean dos problemas: Cómo implementar la lógica propuesta sin penalizar los niveles de seguridad, y cómo manipular un gran número de celdas y automatizar el proceso. El PA-DPL propuesto en el capítulo 2 se valida con una serie de iniciativas, desde características estructurales como doble carril entrelazado o redes de rutado clonadas, hasta los métodos de aplicación tales como las herramientas de personalización y automatización de EDA. Por otra parte, un sistema de calefacción auto-adaptativo es representado y aplicado a una lógica de doble núcleo, con el fin de ajustar alternativamente la temperatura local para equilibrar los impactos negativos de la variación del proceso durante la operación en tiempo real. El capítulo 4 se centra en los detalles de la implementación del kit de herramientas. Desarrollado sobre una API third-party, el kit de herramientas personalizado es capaz de manipular los elementos de la lógica de circuito post P&R ncd (una versión binaria ilegible del xdl) convertido al formato XDL Xilinx. El mecanismo y razón de ser del conjunto de instrumentos propuestos son cuidadosamente descritos, que cubre la detección de enrutamiento y los enfoques para la reparación. El conjunto de herramientas desarrollado tiene como objetivo lograr redes de enrutamiento estrictamente idénticos para la lógica de doble carril, tanto para posicionamiento separado como para el entrelazado. Este capítulo particularmente especifica las bases técnicas para apoyar las implementaciones en los dispositivos de Xilinx y su flexibilidad para ser utilizado sobre otras aplicaciones. El capítulo 5 se enfoca en la aplicación de los casos de estudio para la validación de los grados de seguridad de la lógica propuesta. Se discuten los problemas técnicos detallados durante la ejecución y algunas nuevas técnicas de implementación. (a) Se discute el impacto en el proceso de posicionamiento de la lógica utilizando el kit de herramientas propuesto. Diferentes esquemas de implementación, tomando en cuenta la optimización global en seguridad y coste, se verifican con los experimentos con el fin de encontrar los planes de posicionamiento y reparación optimizados; (b) las validaciones de seguridad se realizan con los métodos de correlación y análisis de tiempo; (c) Una táctica asintótica se aplica a un núcleo AES sobre BCDL estructurado para validar de forma sofisticada el impacto de enrutamiento sobre métricas de seguridad; (d) Los resultados preliminares utilizando el sistema de calefacción auto-adaptativa sobre la variación del proceso son mostrados; (e) Se introduce una aplicación práctica de las herramientas para un diseño de cifrado completa. Capítulo 6 incluye el resumen general del trabajo presentado dentro de esta tesis doctoral. Por último, una breve perspectiva del trabajo futuro se expone, lo que puede ampliar el potencial de utilización de las contribuciones de esta tesis a un alcance más allá de los dominios de la criptografía en FPGAs. ABSTRACT This PhD thesis mainly concentrates on countermeasure techniques related to the Side Channel Attack (SCA), which has been put forward to academic exploitations since 17 years ago. The related research has seen a remarkable growth in the past decades, while the design of solid and efficient protection still curiously remain as an open research topic where more reliable initiatives are required for personal information privacy, enterprise and national data protections. The earliest documented usage of secret code can be traced back to around 1700 B.C., when the hieroglyphs in ancient Egypt are scribed in inscriptions. Information security always gained serious attention from diplomatic or military intelligence transmission. Due to the rapid evolvement of modern communication technique, crypto solution was first incorporated by electronic signal to ensure the confidentiality, integrity, availability, authenticity and non-repudiation of the transmitted contexts over unsecure cable or wireless channels. Restricted to the computation power before computer era, simple encryption tricks were practically sufficient to conceal information. However, algorithmic vulnerabilities can be excavated to restore the encoding rules with affordable efforts. This fact motivated the development of modern cryptography, aiming at guarding information system by complex and advanced algorithms. The appearance of computers has greatly pushed forward the invention of robust cryptographies, which efficiently offers resistance relying on highly strengthened computing capabilities. Likewise, advanced cryptanalysis has greatly driven the computing technologies in turn. Nowadays, the information world has been involved into a crypto world, protecting any fields by pervasive crypto solutions. These approaches are strong because of the optimized mergence between modern mathematical theories and effective hardware practices, being capable of implement crypto theories into various platforms (microprocessor, ASIC, FPGA, etc). Security needs from industries are actually the major driving metrics in electronic design, aiming at promoting the construction of systems with high performance without sacrificing security. Yet a vulnerability in practical implementation found by Prof. Paul Kocher, et al in 1996 implies that modern digital circuits are inherently vulnerable to an unconventional attack approach, which was named as side-channel attack since then from its analysis source. Critical suspicions to theoretically sound modern crypto algorithms surfaced almost immediately after this discovery. To be specifically, digital circuits typically consist of a great number of essential logic elements (as MOS - Metal Oxide Semiconductor), built upon a silicon substrate during the fabrication. Circuit logic is realized relying on the countless switch actions of these cells. This mechanism inevitably results in featured physical emanation that can be properly measured and correlated with internal circuit behaviors. SCAs can be used to reveal the confidential data (e.g. crypto-key), analyze the logic architecture, timing and even inject malicious faults to the circuits that are implemented in hardware system, like FPGA, ASIC, smart Card. Using various comparison solutions between the predicted leakage quantity and the measured leakage, secrets can be reconstructed at much less expense of time and computation. To be precisely, SCA basically encloses a wide range of attack types, typically as the analyses of power consumption or electromagnetic (EM) radiation. Both of them rely on statistical analyses, and hence require a number of samples. The crypto algorithms are not intrinsically fortified with SCA-resistance. Because of the severity, much attention has to be taken into the implementation so as to assemble countermeasures to camouflage the leakages via "side channels". Countermeasures against SCA are evolving along with the development of attack techniques. The physical characteristics requires countermeasures over physical layer, which can be generally classified into intrinsic and extrinsic vectors. Extrinsic countermeasures are executed to confuse the attacker by integrating noise, misalignment to the intra activities. Comparatively, intrinsic countermeasures are built into the algorithm itself, to modify the implementation for minimizing the measurable leakage, or making them not sensitive any more. Hiding and Masking are two typical techniques in this category. Concretely, masking applies to the algorithmic level, to alter the sensitive intermediate values with a mask in reversible ways. Unlike the linear masking, non-linear operations that widely exist in modern cryptographies are difficult to be masked. Approved to be an effective counter solution, hiding method mainly mentions dual-rail logic, which is specially devised for flattening or removing the data-dependent leakage in power or EM signatures. In this thesis, apart from the context describing the attack methodologies, efforts have also been dedicated to logic prototype, to mount extensive security investigations to countermeasures on logic-level. A characteristic of SCA resides on the format of leak sources. Typical side-channel attack concerns the power based analysis, where the fundamental capacitance from MOS transistors and other parasitic capacitances are the essential leak sources. Hence, a robust SCA-resistant logic must eliminate or mitigate the leakages from these micro units, such as basic logic gates, I/O ports and routings. The vendor provided EDA tools manipulate the logic from a higher behavioral-level, rather than the lower gate-level where side-channel leakage is generated. So, the classical implementations barely satisfy these needs and inevitably stunt the prototype. In this case, a customized and flexible design scheme is appealing to be devised. This thesis profiles an innovative logic style to counter SCA, which mainly addresses three major aspects: I. The proposed logic is based on the hiding strategy over gate-level dual-rail style to dynamically overbalance side-channel leakage from lower circuit layer; II. This logic exploits architectural features of modern FPGAs, to minimize the implementation expenses; III. It is supported by a set of assistant custom tools, incorporated by the generic FPGA design flow, to have circuit manipulations in an automatic manner. The automatic design toolkit supports the proposed dual-rail logic, facilitating the practical implementation on Xilinx FPGA families. While the methodologies and the tools are flexible to be expanded to a wide range of applications where rigid and sophisticated gate- or routing- constraints are desired. In this thesis a great effort is done to streamline the implementation workflow of generic dual-rail logic. The feasibility of the proposed solutions is validated by selected and widely used crypto algorithm, for thorough and fair evaluation w.r.t. prior solutions. All the proposals are effectively verified by security experiments. The presented research work attempts to solve the implementation troubles. The essence that will be formalized along this thesis is that a customized execution toolkit for modern FPGA systems is developed to work together with the generic FPGA design flow for creating innovative dual-rail logic. A method in crypto security area is constructed to obtain customization, automation and flexibility in low-level circuit prototype with fine-granularity in intractable routings. Main contributions of the presented work are summarized next: Precharge Absorbed-DPL logic: Using the netlist conversion to reserve free LUT inputs to execute the Precharge and Ex signal in a dual-rail logic style. A row-crossed interleaved placement method with identical routing pairs in dual-rail networks, which helps to increase the resistance against selective EM measurement and mitigate the impacts from process variations. Customized execution and automatic transformation tools for producing identical networks for the proposed dual-rail logic. (a) To detect and repair the conflict nets; (b) To detect and repair the asymmetric nets. (c) To be used in other logics where strict network control is required in Xilinx scenario. Customized correlation analysis testbed for EM and power attacks, including the platform construction, measurement method and attack analysis. A timing analysis based method for quantifying the security grades. A methodology of security partitions of complex crypto systems for reducing the protection cost. A proof-of-concept self-adaptive heating system to mitigate electrical impacts over process variations in dynamic dual-rail compensation manner. The thesis chapters are organized as follows: Chapter 1 discusses the side-channel attack fundamentals, which covers from theoretic basics to analysis models, and further to platform setup and attack execution. Chapter 2 centers to SCA-resistant strategies against generic power and EM attacks. In this chapter, a major contribution, a compact and secure dual-rail logic style, will be originally proposed. The logic transformation based on bottom-layer design will be presented. Chapter 3 is scheduled to elaborate the implementation challenges of generic dual-rail styles. A customized design flow to solve the implementation problems will be described along with a self-developed automatic implementation toolkit, for mitigating the design barriers and facilitating the processes. Chapter 4 will originally elaborate the tool specifics and construction details. The implementation case studies and security validations for the proposed logic style, as well as a sophisticated routing verification experiment, will be described in Chapter 5. Finally, a summary of thesis conclusions and perspectives for future work are included in Chapter 5. To better exhibit the thesis contents, each chapter is further described next: Chapter 1 provides the introduction of hardware implementation testbed and side-channel attack fundamentals, and mainly contains: (a) The FPGA generic architecture and device features, particularly of Virtex-5 FPGA; (b) The selected crypto algorithm - a commercially and extensively used Advanced Encryption Standard (AES) module - is detailed; (c) The essentials of Side-Channel methods are profiled. It reveals the correlated dissipation leakage to the internal behaviors, and the method to recover this relationship between the physical fluctuations in side-channel traces and the intra processed data; (d) The setups of the power/EM testing platforms enclosed inside the thesis work are given. The content of this thesis is expanded and deepened from chapter 2, which is divided into several aspects. First, the protection principle of dynamic compensation of the generic dual-rail precharge logic is explained by describing the compensated gate-level elements. Second, the novel DPL is originally proposed by detailing the logic protocol and an implementation case study. Third, a couple of custom workflows are shown next for realizing the rail conversion. Meanwhile, the technical definitions that are about to be manipulated above LUT-level netlist are clarified. A brief discussion about the batched process is given in the final part. Chapter 3 studies the implementation challenges of DPLs in FPGAs. The security level of state-of-the-art SCA-resistant solutions are decreased due to the implementation barriers using conventional EDA tools. In the studied FPGA scenario, problems are discussed from dual-rail format, parasitic impact, technological bias and implementation feasibility. According to these elaborations, two problems arise: How to implement the proposed logic without crippling the security level; and How to manipulate a large number of cells and automate the transformation. The proposed PA-DPL in chapter 2 is legalized with a series of initiatives, from structures to implementation methods. Furthermore, a self-adaptive heating system is depicted and implemented to a dual-core logic, assumed to alternatively adjust local temperature for balancing the negative impacts from silicon technological biases on real-time. Chapter 4 centers to the toolkit system. Built upon a third-party Application Program Interface (API) library, the customized toolkit is able to manipulate the logic elements from post P&R circuit (an unreadable binary version of the xdl one) converted to Xilinx xdl format. The mechanism and rationale of the proposed toolkit are carefully convoyed, covering the routing detection and repairing approaches. The developed toolkit aims to achieve very strictly identical routing networks for dual-rail logic both for separate and interleaved placement. This chapter particularly specifies the technical essentials to support the implementations in Xilinx devices and the flexibility to be expanded to other applications. Chapter 5 focuses on the implementation of the case studies for validating the security grades of the proposed logic style from the proposed toolkit. Comprehensive implementation techniques are discussed. (a) The placement impacts using the proposed toolkit are discussed. Different execution schemes, considering the global optimization in security and cost, are verified with experiments so as to find the optimized placement and repair schemes; (b) Security validations are realized with correlation, timing methods; (c) A systematic method is applied to a BCDL structured module to validate the routing impact over security metric; (d) The preliminary results using the self-adaptive heating system over process variation is given; (e) A practical implementation of the proposed toolkit to a large design is introduced. Chapter 6 includes the general summary of the complete work presented inside this thesis. Finally, a brief perspective for the future work is drawn which might expand the potential utilization of the thesis contributions to a wider range of implementation domains beyond cryptography on FPGAs.

Energy Storage Systems for Electric Vehicles: Performance Comparison based on a Simple Equivalent Circuit and Experimental Tests

The decision to select the most suitable type of energy storage system for an electric vehicle is always difficult, since many conditionings must be taken into account. Sometimes, this study can be made by means of complex mathematical models which represent the behavior of a battery, ultracapacitor or some other devices. However, these models are usually too dependent on parameters that are not easily available, which usually results in nonrealistic results. Besides, the more accurate the model, the more specific it needs to be, which becomes an issue when comparing systems of different nature. This paper proposes a practical methodology to compare different energy storage technologies. This is done by means of a linear approach of an equivalent circuit based on laboratory tests. Via these tests, the internal resistance and the self-discharge rate are evaluated, making it possible to compare different energy storage systems regardless their technology. Rather simple testing equipment is sufficient to give a comparative idea of the differences between each system, concerning issues such as efficiency, heating and self-discharge, when operating under a certain scenario. The proposed methodology is applied to four energy storage systems of different nature for the sake of illustration.

Effect of strain and magnetic field on the critical current and electric resistance of the joints between HTS coated conductors

Engineering of devices and systems such as magnets, fault current limiters or cables, based on High Temperature Superconducting wires requires a deep characterization of the possible degradation of their properties by handling at room temperature as well as during the service life thus establishing the limits for building up functional devices and systems. In the present work we report our study regarding the mechanical behavior of spliced joints between commercial HTS coated conductors based on YBCO at room temperature and service temperature, 77 K. Tensile tests under axial stress and the evolution of the critical current and the electric resistance of the joints have been measured. The complete strain contour for the tape and the joint has been obtained by using Digital Image Correlation. Also, tensile tests under external magnetic field have been performed and the effect of the applied field on the critical current and the electric resistance of the joints has been studied. Finally, a preliminary numerical study by means of Finite Element Method (FEM) of the mechanical behavior of the joints between commercial HTS is presented.