995 resultados para SI SUBSTRATE
Resumo:
The present work aims to assess Laser-Induced Plasma Spectrometry (LIPS) as a tool for the characterization of photovoltaic materials. Despite being a well-established technique with applications to many scientific and industrial fields, so far LIPS is little known to the photovoltaic scientific community. The technique allows the rapid characterization of layered samples without sample preparation, in open atmosphere and in real time. In this paper, we assess LIPS ability for the determination of elements that are difficult to analyze by other broadly used techniques, or for producing analytical information from very low-concentration elements. The results of the LIPS characterization of two different samples are presented: 1) a 90 nm, Al-doped ZnO layer deposited on a Si substrate by RF sputtering and 2) a Te-doped GaInP layer grown on GaAs by Metalorganic Vapor Phase Epitaxy. For both cases, the depth profile of the constituent and dopant elements is reported along with details of the experimental setup and the optimization of key parameters. It is remarkable that the longest time of analysis was ∼10 s, what, in conjunction with the other characteristics mentioned, makes of LIPS an appealing technique for rapid screening or quality control whether at the lab or at the production line.
Resumo:
We have fabricated titanium and vanadium supersaturated silicon layers on top of a silicon substrate by means of ion implantation and pulsed laser melting processes. This procedure has proven to be suitable to fabricate an intermediate band (IB) material, i.e. a semiconductor material with a band of allowed states within the bandgap. Sheet resistance and Hall mobility measurements as a function of the temperature show an unusual behavior that has been well explained in the framework of the IB material theory, supposing that we are dealing with a junction formed by the IB material top layer and the n-Si substrate. Using an analytical model that fits with accuracy the experimental sheet resistance and mobility curves, we have obtained the values of the exponential factor for the thermically activated junction resistance of the bilayer, showing important differences as a function of the implanted element. These results could allow us to engineer the IB properties selecting the implanted element depending on the required properties for a specific application.
Resumo:
In the framework of the third generation of photovoltaic devices, the intermediate band solar cell is one of the possible candidates to reach higher efficiencies with a lower processing cost. In this work, we introduce a novel processing method based on a double ion implantation and, subsequently, a pulsed laser melting (PLM) process to obtain thicker layers of Ti supersaturated Si. We perform ab initio theoretical calculations of Si impurified with Ti showing that Ti in Si is a good candidate to theoretically form an intermediate band material in the Ti supersaturated Si. From time-of-flight secondary ion mass spectroscopy measurements, we confirm that we have obtained a Ti implanted and PLM thicker layer of 135 nm. Transmission electron microscopy reveals a single crystalline structure whilst the electrical characterization confirms the transport properties of an intermediate band material/Si substrate junction. High subbandgap absorption has been measured, obtaining an approximate value of 104 cm−1 in the photons energy range from 1.1 to 0.6 eV.
Resumo:
Los transistores de alta movilidad electrónica basados en GaN han sido objeto de una extensa investigación ya que tanto el GaN como sus aleaciones presentan unas excelentes propiedades eléctricas (alta movilidad, elevada concentración de portadores y campo eléctrico crítico alto). Aunque recientemente se han incluido en algunas aplicaciones comerciales, su expansión en el mercado está condicionada a la mejora de varios asuntos relacionados con su rendimiento y habilidad. Durante esta tesis se han abordado algunos de estos aspectos relevantes; por ejemplo, la fabricación de enhancement mode HEMTs, su funcionamiento a alta temperatura, el auto calentamiento y el atrapamiento de carga. Los HEMTs normalmente apagado o enhancement mode han atraído la atención de la comunidad científica dedicada al desarrollo de circuitos amplificadores y conmutadores de potencia, ya que su utilización disminuiría significativamente el consumo de potencia; además de requerir solamente una tensión de alimentación negativa, y reducir la complejidad del circuito y su coste. Durante esta tesis se han evaluado varias técnicas utilizadas para la fabricación de estos dispositivos: el ataque húmedo para conseguir el gate-recess en heterostructuras de InAl(Ga)N/GaN; y tratamientos basados en flúor (plasma CF4 e implantación de F) de la zona debajo de la puerta. Se han llevado a cabo ataques húmedos en heteroestructuras de InAl(Ga)N crecidas sobre sustratos de Si, SiC y zafiro. El ataque completo de la barrera se consiguió únicamente en las muestras con sustrato de Si. Por lo tanto, se puede deducir que la velocidad de ataque depende de la densidad de dislocaciones presentes en la estructura, ya que el Si presenta un peor ajuste del parámetro de red con el GaN. En relación a los tratamientos basados en flúor, se ha comprobado que es necesario realizar un recocido térmico después de la fabricación de la puerta para recuperar la heteroestructura de los daños causados durante dichos tratamientos. Además, el estudio de la evolución de la tensión umbral con el tiempo de recocido ha demostrado que en los HEMTs tratados con plasma ésta tiende a valores más negativos al aumentar el tiempo de recocido. Por el contrario, la tensión umbral de los HEMTs implantados se desplaza hacia valores más positivos, lo cual se atribuye a la introducción de iones de flúor a niveles más profundos de la heterostructura. Los transistores fabricados con plasma presentaron mejor funcionamiento en DC a temperatura ambiente que los implantados. Su estudio a alta temperatura ha revelado una reducción del funcionamiento de todos los dispositivos con la temperatura. Los valores iniciales de corriente de drenador y de transconductancia medidos a temperatura ambiente se recuperaron después del ciclo térmico, por lo que se deduce que dichos efectos térmicos son reversibles. Se han estudiado varios aspectos relacionados con el funcionamiento de los HEMTs a diferentes temperaturas. En primer lugar, se han evaluado las prestaciones de dispositivos de AlGaN/GaN sobre sustrato de Si con diferentes caps: GaN, in situ SiN e in situ SiN/GaN, desde 25 K hasta 550 K. Los transistores con in situ SiN presentaron los valores más altos de corriente drenador, transconductancia, y los valores más bajos de resistencia-ON, así como las mejores características en corte. Además, se ha confirmado que dichos dispositivos presentan gran robustez frente al estrés térmico. En segundo lugar, se ha estudiado el funcionamiento de transistores de InAlN/GaN con diferentes diseños y geometrías. Dichos dispositivos presentaron una reducción casi lineal de los parámetros en DC en el rango de temperaturas de 25°C hasta 225°C. Esto se debe principalmente a la dependencia térmica de la movilidad electrónica, y también a la reducción de la drift velocity con la temperatura. Además, los transistores con mayores longitudes de puerta mostraron una mayor reducción de su funcionamiento, lo cual se atribuye a que la drift velocity disminuye más considerablemente con la temperatura cuando el campo eléctrico es pequeño. De manera similar, al aumentar la distancia entre la puerta y el drenador, el funcionamiento del HEMT presentó una mayor reducción con la temperatura. Por lo tanto, se puede deducir que la degradación del funcionamiento de los HEMTs causada por el aumento de la temperatura depende tanto de la longitud de la puerta como de la distancia entre la puerta y el drenador. Por otra parte, la alta densidad de potencia generada en la región activa de estos transistores conlleva el auto calentamiento de los mismos por efecto Joule, lo cual puede degradar su funcionamiento y Habilidad. Durante esta tesis se ha desarrollado un simple método para la determinación de la temperatura del canal basado en medidas eléctricas. La aplicación de dicha técnica junto con la realización de simulaciones electrotérmicas han posibilitado el estudio de varios aspectos relacionados con el autocalentamiento. Por ejemplo, se han evaluado sus efectos en dispositivos sobre Si, SiC, y zafiro. Los transistores sobre SiC han mostrado menores efectos gracias a la mayor conductividad térmica del SiC, lo cual confirma el papel clave que desempeña el sustrato en el autocalentamiento. Se ha observado que la geometría del dispositivo tiene cierta influencia en dichos efectos, destacando que la distribución del calor generado en la zona del canal depende de la distancia entre la puerta y el drenador. Además, se ha demostrado que la temperatura ambiente tiene un considerable impacto en el autocalentamiento, lo que se atribuye principalmente a la dependencia térmica de la conductividad térmica de las capas y sustrato que forman la heterostructura. Por último, se han realizado numerosas medidas en pulsado para estudiar el atrapamiento de carga en HEMTs sobre sustratos de SiC con barreras de AlGaN y de InAlN. Los resultados obtenidos en los transistores con barrera de AlGaN han presentado una disminución de la corriente de drenador y de la transconductancia sin mostrar un cambio en la tensión umbral. Por lo tanto, se puede deducir que la posible localización de las trampas es la región de acceso entre la puerta y el drenador. Por el contrario, la reducción de la corriente de drenador observada en los dispositivos con barrera de InAlN llevaba asociado un cambio significativo en la tensión umbral, lo que implica la existencia de trampas situadas en la zona debajo de la puerta. Además, el significativo aumento del valor de la resistencia-ON y la degradación de la transconductancia revelan la presencia de trampas en la zona de acceso entre la puerta y el drenador. La evaluación de los efectos del atrapamiento de carga en dispositivos con diferentes geometrías ha demostrado que dichos efectos son menos notables en aquellos transistores con mayor longitud de puerta o mayor distancia entre puerta y drenador. Esta dependencia con la geometría se puede explicar considerando que la longitud y densidad de trampas de la puerta virtual son independientes de las dimensiones del dispositivo. Finalmente se puede deducir que para conseguir el diseño óptimo durante la fase de diseño no sólo hay que tener en cuenta la aplicación final sino también la influencia que tiene la geometría en los diferentes aspectos estudiados (funcionamiento a alta temperatura, autocalentamiento, y atrapamiento de carga). ABSTRACT GaN-based high electron mobility transistors have been under extensive research due to the excellent electrical properties of GaN and its related alloys (high carrier concentration, high mobility, and high critical electric field). Although these devices have been recently included in commercial applications, some performance and reliability issues need to be addressed for their expansion in the market. Some of these relevant aspects have been studied during this thesis; for instance, the fabrication of enhancement mode HEMTs, the device performance at high temperature, the self-heating and the charge trapping. Enhancement mode HEMTs have become more attractive mainly because their use leads to a significant reduction of the power consumption during the stand-by state. Moreover, they enable the fabrication of simpler power amplifier circuits and high-power switches because they allow the elimination of negativepolarity voltage supply, reducing significantly the circuit complexity and system cost. In this thesis, different techniques for the fabrication of these devices have been assessed: wet-etching for achieving the gate-recess in InAl(Ga)N/GaN devices and two different fluorine-based treatments (CF4 plasma and F implantation). Regarding the wet-etching, experiments have been carried out in InAl(Ga)N/GaN grown on different substrates: Si, sapphire, and SiC. The total recess of the barrier was achieved after 3 min of etching in devices grown on Si substrate. This suggests that the etch rate can critically depend on the dislocations present in the structure, since the Si exhibits the highest mismatch to GaN. Concerning the fluorine-based treatments, a post-gate thermal annealing was required to recover the damages caused to the structure during the fluorine-treatments. The study of the threshold voltage as a function of this annealing time has revealed that in the case of the plasma-treated devices it become more negative with the time increase. On the contrary, the threshold voltage of implanted HEMTs showed a positive shift when the annealing time was increased, which is attributed to the deep F implantation profile. Plasma-treated HEMTs have exhibited better DC performance at room temperature than the implanted devices. Their study at high temperature has revealed that their performance decreases with temperature. The initial performance measured at room temperature was recovered after the thermal cycle regardless of the fluorine treatment; therefore, the thermal effects were reversible. Thermal issues related to the device performance at different temperature have been addressed. Firstly, AlGaN/GaN HEMTs grown on Si substrate with different cap layers: GaN, in situ SiN, or in situ SiN/GaN, have been assessed from 25 K to 550 K. In situ SiN cap layer has been demonstrated to improve the device performance since HEMTs with this cap layer have exhibited the highest drain current and transconductance values, the lowest on-resistance, as well as the best off-state characteristics. Moreover, the evaluation of thermal stress impact on the device performance has confirmed the robustness of devices with in situ cap. Secondly, the high temperature performance of InAlN/GaN HEMTs with different layouts and geometries have been assessed. The devices under study have exhibited an almost linear reduction of the main DC parameters operating in a temperature range from room temperature to 225°C. This was mainly due to the thermal dependence of the electron mobility, and secondly to the drift velocity decrease with temperature. Moreover, HEMTs with large gate length values have exhibited a great reduction of the device performance. This was attributed to the greater decrease of the drift velocity for low electric fields. Similarly, the increase of the gate-to-drain distance led to a greater reduction of drain current and transconductance values. Therefore, this thermal performance degradation has been found to be dependent on both the gate length and the gate-to-drain distance. It was observed that the very high power density in the active region of these transistors leads to Joule self-heating, resulting in an increase of the device temperature, which can degrade the device performance and reliability. A simple electrical method have been developed during this work to determine the channel temperature. Furthermore, the application of this technique together with the performance of electro-thermal simulations have enabled the evaluation of different aspects related to the self-heating. For instance, the influence of the substrate have been confirmed by the study of devices grown on Si, SiC, and Sapphire. HEMTs grown on SiC substrate have been confirmed to exhibit the lowest self-heating effects thanks to its highest thermal conductivity. In addition to this, the distribution of the generated heat in the channel has been demonstrated to be dependent on the gate-to-drain distance. Besides the substrate and the geometry of the device, the ambient temperature has also been found to be relevant for the self-heating effects, mainly due to the temperature-dependent thermal conductivity of the layers and the substrate. Trapping effects have been evaluated by means of pulsed measurements in AlGaN and InAIN barrier devices. AlGaN barrier HEMTs have exhibited a de crease in drain current and transconductance without measurable threshold voltage change, suggesting the location of the traps in the gate-to-drain access region. On the contrary, InAIN barrier devices have showed a drain current associated with a positive shift of threshold voltage, which indicated that the traps were possibly located under the gate region. Moreover, a significant increase of the ON-resistance as well as a transconductance reduction were observed, revealing the presence of traps on the gate-drain access region. On the other hand, the assessment of devices with different geometries have demonstrated that the trapping effects are more noticeable in devices with either short gate length or the gate-to-drain distance. This can be attributed to the fact that the length and the trap density of the virtual gate are independent on the device geometry. Finally, it can be deduced that besides the final application requirements, the influence of the device geometry on the performance at high temperature, on the self-heating, as well as on the trapping effects need to be taken into account during the device design stage to achieve the optimal layout.
Resumo:
Synthesis and functionalization of large-area graphene and its structural, electrical and electrochemical properties has been investigated. First, the graphene films, grown by thermal chemical vapor deposition (CVD), contain three to five atomic layers of graphene, as confirmed by Raman spectroscopy and high-resolution transmission electron microscopy. Furthermore, the graphene film is treated with CF4 reactive-ion plasma to dope fluorine ions into graphene lattice as confirmed by X-ray photoelectron spectroscopy (XPS) and UV-photoemission spectroscopy (UPS). Electrochemical characterization reveals that the catalytic activity of graphene for iodine reduction enhanced with increasing plasma treatment time, which is attributed to increase in catalytic sites of graphene for charge transfer. The fluorinated graphene is characterized as a counter-electrode (CE) in a dye-sensitized solar cell (DSSC) which shows ~ 2.56% photon to electron conversion efficiency with ~11 mAcm−2 current density. Second, the large scale graphene film is covalently functionalized with HNO3 for high efficiency electro-catalytic electrode for DSSC. The XPS and UPS confirm the covalent attachment of C-OH, C(O)OH and NO3- moieties with carbon atoms through sp2-sp3 hybridization and Fermi level shift of graphene occurs under different doping concentrations, respectively. Finally, CoS-implanted graphene (G-CoS) film was prepared using CVD followed by SILAR method. The G-CoS electro-catalytic electrodes are characterized in a DSSC CE and is found to be highly electro-catalytic towards iodine reduction with low charge transfer resistance (Rct ~5.05 Ωcm 2) and high exchange current density (J0~2.50 mAcm -2). The improved performance compared to the pristine graphene is attributed to the increased number of active catalytic sites of G-CoS and highly conducting path of graphene. We also studied the synthesis and characterization of graphene-carbon nanotube (CNT) hybrid film consisting of graphene supported by vertical CNTs on a Si substrate. The hybrid film is inverted and transferred to flexible substrates for its application in flexible electronics, demonstrating a distinguishable variation of electrical conductivity for both tension and compression. Furthermore, both turn-on field and total emission current was found to depend strongly on the bending radius of the film and were found to vary in ranges of 0.8 - 3.1 V/μm and 4.2 - 0.4 mA, respectively.
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This thesis is devoted to the development, synthesis, properties, and applications of nano materials for critical technologies, including three areas: (1) Microbial contamination of drinking water is a serious problem of global significance. About 51% of the waterborne disease outbreaks in the United States can be attributed to contaminated ground water. Development of metal oxide nanoparticles, as viricidal materials is of technological and fundamental scientific importance. Nanoparticles with high surface areas and ultra small particle sizes have dramatically enhanced efficiency and capacity of virus inactivation, which cannot be achieved by their bulk counterparts. A series of metal oxide nanoparticles, such as iron oxide nanoparticles, zinc oxide nanoparticles and iron oxide-silver nanoparticles, coated on fiber substrates was developed in this research for evaluation of their viricidal activity. We also carried out XRD, TEM, SEM, XPS, surface area measurements, and zeta potential of these nanoparticles. MS2 virus inactivation experiments showed that these metal oxide nanoparticle coated fibers were extremely powerful viricidal materials. Results from this research suggest that zinc oxide nanoparticles with diameter of 3.5 nm, showing an isoelectric point (IEP) at 9.0, were well dispersed on fiberglass. These fibers offer an increase in capacity by orders of magnitude over all other materials. Compared to iron oxide nanoparticles, zinc oxide nanoparticles didn’t show an improvement in inactivation kinetics but inactivation capacities did increase by two orders of magnitude to 99.99%. Furthermore, zinc oxide nanoparticles have higher affinity to viruses than the iron oxide nanoparticles in presence of competing ions. The advantages of zinc oxide depend on high surface charge density, small nanoparticle sizes and capabilities of generating reactive oxygen species. The research at its present stage of development appears to offer the best avenue to remove viruses from water. Without additional chemicals and energy input, this system can be implemented by both points of use (POU) and large-scale use water treatment technology, which will have a significant impact on the water purification industry. (2) A new family of aliphatic polyester lubricants has been developed for use in micro-electromechanical systems (MEMS), specifically for hard disk drives that operate at high spindle speeds (>15000rpm). Our program was initiated to address current problems with spin-off of the perfluoroether (PFPE) lubricants. The new polyester lubricant appears to alleviate spin-off problems and at the same time improves the chemical and thermal stability. This new system provides a low cost alternative to PFPE along with improved adhesion to the substrates. In addition, it displays a much lower viscosity, which may be of importance to stiction related problems. The synthetic route is readily scalable in case additional interest emerges in other areas including small motors. (3) The demand for increased signal transmission speed and device density for the next generation of multilevel integrated circuits has placed stringent demands on materials performance. Currently, integration of the ultra low-k materials in dual Damascene processing requires chemical mechanical polishing (CMP) to planarize the copper. Unfortunately, none of the commercially proposed dielectric candidates display the desired mechanical and thermal properties for successful CMP. A new polydiacetylene thermosetting polymer (DEB-TEB), which displays a low dielectric constant (low-k) of 2.7, was recently developed. This novel material appears to offer the only avenue for designing an ultra low k dielectric (1.85k), which can still display the desired modulus (7.7Gpa) and hardness (2.0Gpa) sufficient to withstand the process of CMP. We focused on further characterization of the thermal properties of spin-on poly (DEB-TEB) ultra-thin film. These include the coefficient of thermal expansion (CTE), biaxial thermal stress, and thermal conductivity. Thus the CTE is 2.0*10-5K-1 in the perpendicular direction and 8.0*10-6 K-1 in the planar direction. The low CTE provides a better match to the Si substrate which minimizes interfacial stress and greatly enhances the reliability of the microprocessors. Initial experiments with oxygen plasma etching suggest a high probability of success for achieving vertical profiles.
Resumo:
Silicon photoanodes protected by atomic layer deposited (ALD) TiO2 show promise as components of water splitting devices that may enable the large-scale production of solar fuels and chemicals. Minimizing the resistance of the oxide corrosion protection layer is essential for fabricating efficient devices with good fill factor. Recent literature reports have shown that the interfacial SiO2 layer, interposed between the protective ALD-TiO2 and the Si anode, acts as a tunnel oxide that limits hole conduction from the photoabsorbing substrate to the surface oxygen evolution catalyst. Herein, we report a significant reduction of bilayer resistance, achieved by forming stable, ultrathin (<1.3 nm) SiO2 layers, allowing fabrication of water splitting photoanodes with hole conductances near the maximum achievable with the given catalyst and Si substrate. Three methods for controlling the SiO2 interlayer thickness on the Si(100) surface for ALD-TiO2 protected anodes were employed: (1) TiO2 deposition directly on an HF-etched Si(100) surface, (2) TiO2 deposition after SiO2 atomic layer deposition on an HF-etched Si(100) surface, and (3) oxygen scavenging, post-TiO2 deposition to decompose the SiO2 layer using a Ti overlayer. Each of these methods provides a progressively superior means of reliably thinning the interfacial SiO2 layer, enabling the fabrication of efficient and stable water oxidation silicon anodes.
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A simple, effective, and innovative approach based on ion-assisted self-organization is proposed to synthesize size-selected Si quantum dots (QDs) on SiC substrates at low substrate temperatures. Using hybrid numerical simulations, the formation of Si QDs through a self-organization approach is investigated by taking into account two distinct cases of Si QD formation using the ionization energy approximation theory, which considers ionized in-fluxes containing Si3+ and Si1+ ions in the presence of a microscopic nonuniform electric field induced by a variable surface bias. The results show that the highest percentage of the surface coverage by 1 and 2 nm size-selected QDs was achieved using a bias of -20 V and ions in the lowest charge state, namely, Si1+ ions in a low substrate temperature range (227-327 °C). As low substrate temperatures (≤500 °C) are desirable from a technological point of view, because (i) low-temperature deposition techniques are compatible with current thin-film Si-based solar cell fabrication and (ii) high processing temperatures can frequently cause damage to other components in electronic devices and destroy the tandem structure of Si QD-based third-generation solar cells, our results are highly relevant to the development of the third-generation all-Si tandem photovoltaic solar cells.
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The registry of bismuth dimers, integral components of the bismuth nanoline on Si(001), is examined. In contrast to the currently accepted view, the bismuth dimers are found to be in registry with the two-dimensional lattice created by the silicon dimers. The consequences of this finding are briefly explored.
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An attempt has been made to study the film-substrate interface by using a sensitive, non- conventional tool. Because of the prospective use of gate oxide in MOSFET devices, we have chosen to study alumina films grown on silicon. Film-substrate interface of alumina grown by MOCVD on Si(100) was studied systematically using spectroscopic ellipsometry in the range 1.5-5.0 eV, supported by cross-sectional SEM, and SIMS. The (ε1,ε2) versus energy data obtained for films grown at 600°C, 700°C, and 750°C were modeled to fit a substrate/interface/film “sandwich”. The experimental results reveal (as may be expected) that the nature of the substrate -film interface depends strongly on the growth temperature. The simulated (ε1,ε2) patterns are in excellent agreement with observed ellipsometric data. The MOCVD precursors results the presence of carbon in the films. Theoretical simulation was able to account for the ellipsometry data by invoking the presence of “free” carbon in the alumina films.
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Phase pure wurtzite GaN films were grown on Si (100) substrates by introducing a silicon nitride layer followed by low temperature GaN growth as buffer layers. GaN films grown directly on Si (100) were found to be phase mixtured, containing both cubic (beta) and hexagonal (alpha) modifications. The x-ray diffraction (XRD), scanning electron microscopy (SEM), photoluminescence (PL) spectroscopy studies reveal that the significant enhancement in the structural as well as in the optical properties of GaN films grown with silicon nitride buffer layer grown at 800 degrees C when compared to the samples grown in the absence of silicon nitride buffer layer and with silicon nitride buffer layer grown at 600 degrees C. Core-level photoelectron spectroscopy of Si(x)N(y) layers reveals the sources for superior qualities of GaN epilayers grown with the high temperature substrate nitridation process. The discussion has been carried out on the typical inverted rectification behavior exhibited by n-GaN/p-Si heterojunctions. Considerable modulation in the transport mechanism was observed with the nitridation conditions. The heterojunction fabricated with the sample of substrate nitridation at high temperature exhibited superior rectifying nature with reduced trap concentrations. Lowest ideality factors (similar to 1.5) were observed in the heterojunctions grown with high temperature substrate nitridation which is attributed to the recombination tunneling at the space charge region transport mechanism at lower voltages and at higher voltages space charge limited current conduction is the dominating transport mechanism. Whereas, thermally generated carrier tunneling and recombination tunneling are the dominating transport mechanisms in the heterojunctions grown without substrate nitridation and low temperature substrate nitridation, respectively. (C) 2011 American Institute of Physics. [doi:10.1063/1.3658867]
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We report, strong ultraviolet (UV) emission from ZnO nanoparticle thin film obtained by a green synthesis, where the film is formed by the microwave irradiation of the alcohol solution of the precursor. The deposition is carried out in non-aqueous medium without the use of any surfactant, and the film formation is quick (5 min). The film is uniform comprising of mono-disperse nanoparticles having a narrow size distribution (15-22 nm), and that cover over an entire area (625 mm(2)) of the substrate. The growth rate is comparatively high (30-70 nm/min). It is possible to tune the morphology of the films and the UV emission by varying the process parameters. The growth mechanism is discussed precisely and schematic of the growth process is provided.
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This research article describes the large scale fabrication of ZnO nanorods of various shapes on Si(100) substrate, by using metalorganic precursor of Zn in solutions with microwave as the source of energy. This is a low temperature, environmental friendly and rapid thin film deposition process, where ZnO nanorods (1-3 mu m length) were grown only in 1-5 min of microwave irradiation. All as-synthesized nanorods are of single crystalline grown along the < 0001 > crystallographic direction. The coated nanorods were found to be highly dense having a thickness of similar to 1-3 mu m over the entire area 20 mm x 20 mm of the substrate. The ZnO thin film comprising of nanorods exhibits good adhesion with the substrate. A possible mechanism for the initial nucleation and growth of ZnO is discussed. A cross over from a strong visible light emission to an enhanced UV emission is observed, when the nature of the surfactants are varied from polymeric to ionic and nonionic. The position of the chromaticity coordinates in yellow region of the color space gives an impression of white light generation from these coatings by exciting with a blue laser.
Resumo:
This report focuses on the structural and optical properties of the GaN films grown on p-Si (100) substrates along with photovoltaic characteristics of GaN/p-Si heterojunctions fabricated with substrate nitridation and in absence of substrate nitridation. The high resolution X-ray diffraction (HRXRD), atomic force microscopy (AFM), Raman and photoluminescence (PL) spectroscopic studies reveal that the significant enhancement in the structural as well as in the optical properties of GaN epifilms grown with silicon nitride buffer layer when compared with the sample grown without silicon nitride buffer layer. The low temperature PL shows a free excitonic (FX) emission peak at 3.51 eV at the temperature of 5 K with a very narrow line width of 35 meV. Temperature dependent PL spectra follow the Varshni equation well and peak energy blue shifts by similar to 63 meV from 300 to 5 K. Raman data confirms the strain free nature and reasonably good crystallinity of the films. The GaN/p-Si heterojunctions fabricated without substrate nitridation show a superior photovoltaic performance compared to the devices fabricated in presence of substrate nitridation. The discussions have been carried out on the junction properties. Such single junction devices exhibit a promising fill factor and conversion efficiency of 23.36 and 0.12 %, respectively, under concentrated AM1.5 illumination.