MADAP, a flexible clustering tool for the interpretation of one-dimensional genome annotation data.

A recurring task in the analysis of mass genome annotation data from high-throughput technologies is the identification of peaks or clusters in a noisy signal profile. Examples of such applications are the definition of promoters on the basis of transcription start site profiles, the mapping of transcription factor binding sites based on ChIP-chip data and the identification of quantitative trait loci (QTL) from whole genome SNP profiles. Input to such an analysis is a set of genome coordinates associated with counts or intensities. The output consists of a discrete number of peaks with respective volumes, extensions and center positions. We have developed for this purpose a flexible one-dimensional clustering tool, called MADAP, which we make available as a web server and as standalone program. A set of parameters enables the user to customize the procedure to a specific problem. The web server, which returns results in textual and graphical form, is useful for small to medium-scale applications, as well as for evaluation and parameter tuning in view of large-scale applications, requiring a local installation. The program written in C++ can be freely downloaded from ftp://ftp.epd.unil.ch/pub/software/unix/madap. The MADAP web server can be accessed at http://www.isrec.isb-sib.ch/madap/.

Rapid fluidic exchange microsystem for recording of fast ion channel kinetics in Xenopus oocytes.

We present a new lab-on-a-chip system for electrophysiological measurements on Xenopus oocytes. Xenopus oocytes are widely used host cells in the field of pharmacological studies and drug development. We developed a novel non-invasive technique using immobilized non-devitellinized cells that replaces the traditional "two-electrode voltage-clamp" (TEVC) method. In particular, rapid fluidic exchange was implemented on-chip to allow recording of fast kinetic events of exogenous ion channels expressed in the cell membrane. Reducing fluidic exchange times of extracellular reagent solutions is a great challenge with these large millimetre-sized cells. Fluidic switching is obtained by shifting the laminar flow interface in a perfusion channel under the cell by means of integrated poly-dimethylsiloxane (PDMS) microvalves. Reagent solution exchange times down to 20 ms have been achieved. An on-chip purging system allows to perform complex pharmacological protocols, making the system suitable for screening of ion channel ligand libraries. The performance of the integrated rapid fluidic exchange system was demonstrated by investigating the self-inhibition of human epithelial sodium channels (ENaC). Our results show that the response time of this ion channel to a specific reactant is about an order of magnitude faster than could be estimated with the traditional TEVC technique.

Voltage fluctuations in IC power supply distribution

The supply voltage decrease and powerconsumption increase of modern ICs made the requirements for low voltage fluctuation caused by packaging and on-chip parasitic impedances more difficult to achieve. Most of the research works on the area assume that all the nodes of the chip are fed at thesame voltage, in such a way that the main cause of disturbance or fluctuation is the parasitic impedance of packaging. In the paper an approach to analyze the effect of high and fast current demands on the on-chip power supply network. First an approach to model the entire network by considering a homogeneous conductive foil is presented. The modification of the timing parameters of flipflops caused by spatial voltage drops through the IC surface are also investigated.

Oikosulkumoottorin roottorivaurioiden tunnistaminen staattorivirran avulla

Diplomityössä esitellään menetelmiä sauvarikon toteamiseksi. Työn tarkoituksena on tutkia roottorivaurioita staattorivirran avulla. Työ jaetaan karkeasti kolmeen osa-alueeseen: oikosulkumoottorin vikoihin, roottorivaurioiden tunnistamiseen ja signaalinkäsittelymenetelmiin, jonka avulla havaitaan sauvarikko. Oikosulkumoottorin vikoja ovat staattorikäämien vauriot ja roottorivauriot. Roottorikäämien vaurioita ovat roottori sauvojen murtuminen sekä roottorisauvan irtoaminen oikosulkujenkaan päästä. Roottorivaurioiden tunnistamismenetelmiä ovat parametrin arviointi ja virtaspektrianalyysi. Työn alkuosassa esitellään oikosulkumoottorien rakenne ja toiminta. Esitellään moottoriin kohdistuvia vikoja ja etsitään ratkaisumenetelmiä roottorivaurioiden tunnistamisessa. Lopuksi tutkitaan, kuinka staattorimittaustietojen perusteella saadut tulokset voidaan käsitellä FFT -algoritmilla ja kuinka FFT -algoritmi voidaan toteuttaa sulautettuna Sharc -prosessorin avulla. Työssä käytetään ADSP 21062 EZ -LAB kehitysympäristöä, jonka avulla voidaan ajaa ohjelmia RAM-sirusta, joka on vuorovaikutuksessa SHARC -laudassa oleviin laitteisiin.

Predictors and consequences of adherence to the treatment of pediatric patients with attention-deficit/hyperactivity disorder in Central Europe and East Asia.

PURPOSE: To assess baseline predictors and consequences of medication non-adherence in the treatment of pediatric patients with attention-deficit/hyperactivity disorder (ADHD) from Central Europe and East Asia. PATIENTS AND METHODS: Data for this post-hoc analysis were taken from a 1-year prospective, observational study that included a total of 1,068 newly-diagnosed pediatric patients with ADHD symptoms from Central Europe and East Asia. Medication adherence during the week prior to each visit was assessed by treating physicians using a 5-point Likert scale, and then dichotomized into either adherent or non-adherent. Clinical severity was measured by the Clinical Global Impressions-ADHD-Severity (CGI-ADHD) scale and the Child Symptom Inventory-4 (CSI-4) Checklist. Health-Related Quality of Life (HRQoL) was measured using the Child Health and Illness Profile-Child Edition (CHIP-CE). Regression analyses were used to assess baseline predictors of overall adherence during follow-up, and the impact of time-varying adherence on subsequent outcomes: response (defined as a decrease of at least 1 point in CGI), changes in CGI-ADHD, CSI-4, and the five dimensions of CHIP-CE. RESULTS: Of the 860 patients analyzed, 64.5% (71.6% in Central Europe and 55.5% in East Asia) were rated as adherent and 35.5% as non-adherent during follow-up. Being from East Asia was found to be a strong predictor of non-adherence. In East Asia, a family history of ADHD and parental emotional distress were associated with non-adherence, while having no other children living at home was associated with non-adherence in Central Europe as well as in the overall sample. Non-adherence was associated with poorer response and less improvement on CGI-ADHD and CSI-4, but not on CHIP-CE. CONCLUSION: Non-adherence to medication is common in the treatment of ADHD, particularly in East Asia. Non-adherence was associated with poorer response and less improvement in clinical severity. A limitation of this study is that medication adherence was assessed by the treating clinician using a single item question.

Exploration and Design of Power-Efficient Networked Many-Core Systems

Multiprocessing is a promising solution to meet the requirements of near future applications. To get full benefit from parallel processing, a manycore system needs efficient, on-chip communication architecture. Networkon- Chip (NoC) is a general purpose communication concept that offers highthroughput, reduced power consumption, and keeps complexity in check by a regular composition of basic building blocks. This thesis presents power efficient communication approaches for networked many-core systems. We address a range of issues being important for designing power-efficient manycore systems at two different levels: the network-level and the router-level. From the network-level point of view, exploiting state-of-the-art concepts such as Globally Asynchronous Locally Synchronous (GALS), Voltage/ Frequency Island (VFI), and 3D Networks-on-Chip approaches may be a solution to the excessive power consumption demanded by today’s and future many-core systems. To this end, a low-cost 3D NoC architecture, based on high-speed GALS-based vertical channels, is proposed to mitigate high peak temperatures, power densities, and area footprints of vertical interconnects in 3D ICs. To further exploit the beneficial feature of a negligible inter-layer distance of 3D ICs, we propose a novel hybridization scheme for inter-layer communication. In addition, an efficient adaptive routing algorithm is presented which enables congestion-aware and reliable communication for the hybridized NoC architecture. An integrated monitoring and management platform on top of this architecture is also developed in order to implement more scalable power optimization techniques. From the router-level perspective, four design styles for implementing power-efficient reconfigurable interfaces in VFI-based NoC systems are proposed. To enhance the utilization of virtual channel buffers and to manage their power consumption, a partial virtual channel sharing method for NoC routers is devised and implemented. Extensive experiments with synthetic and real benchmarks show significant power savings and mitigated hotspots with similar performance compared to latest NoC architectures. The thesis concludes that careful codesigned elements from different network levels enable considerable power savings for many-core systems.

Adaptive Routing Approaches for Networked Many-Core Systems

Through advances in technology, System-on-Chip design is moving towards integrating tens to hundreds of intellectual property blocks into a single chip. In such a many-core system, on-chip communication becomes a performance bottleneck for high performance designs. Network-on-Chip (NoC) has emerged as a viable solution for the communication challenges in highly complex chips. The NoC architecture paradigm, based on a modular packet-switched mechanism, can address many of the on-chip communication challenges such as wiring complexity, communication latency, and bandwidth. Furthermore, the combined benefits of 3D IC and NoC schemes provide the possibility of designing a high performance system in a limited chip area. The major advantages of 3D NoCs are the considerable reductions in average latency and power consumption. There are several factors degrading the performance of NoCs. In this thesis, we investigate three main performance-limiting factors: network congestion, faults, and the lack of efficient multicast support. We address these issues by the means of routing algorithms. Congestion of data packets may lead to increased network latency and power consumption. Thus, we propose three different approaches for alleviating such congestion in the network. The first approach is based on measuring the congestion information in different regions of the network, distributing the information over the network, and utilizing this information when making a routing decision. The second approach employs a learning method to dynamically find the less congested routes according to the underlying traffic. The third approach is based on a fuzzy-logic technique to perform better routing decisions when traffic information of different routes is available. Faults affect performance significantly, as then packets should take longer paths in order to be routed around the faults, which in turn increases congestion around the faulty regions. We propose four methods to tolerate faults at the link and switch level by using only the shortest paths as long as such path exists. The unique characteristic among these methods is the toleration of faults while also maintaining the performance of NoCs. To the best of our knowledge, these algorithms are the first approaches to bypassing faults prior to reaching them while avoiding unnecessary misrouting of packets. Current implementations of multicast communication result in a significant performance loss for unicast traffic. This is due to the fact that the routing rules of multicast packets limit the adaptivity of unicast packets. We present an approach in which both unicast and multicast packets can be efficiently routed within the network. While suggesting a more efficient multicast support, the proposed approach does not affect the performance of unicast routing at all. In addition, in order to reduce the overall path length of multicast packets, we present several partitioning methods along with their analytical models for latency measurement. This approach is discussed in the context of 3D mesh networks.

Reusable formal architectures for networked systems

Today's networked systems are becoming increasingly complex and diverse. The current simulation and runtime verification techniques do not provide support for developing such systems efficiently; moreover, the reliability of the simulated/verified systems is not thoroughly ensured. To address these challenges, the use of formal techniques to reason about network system development is growing, while at the same time, the mathematical background necessary for using formal techniques is a barrier for network designers to efficiently employ them. Thus, these techniques are not vastly used for developing networked systems. The objective of this thesis is to propose formal approaches for the development of reliable networked systems, by taking efficiency into account. With respect to reliability, we propose the architectural development of correct-by-construction networked system models. With respect to efficiency, we propose reusable network architectures as well as network development. At the core of our development methodology, we employ the abstraction and refinement techniques for the development and analysis of networked systems. We evaluate our proposal by employing the proposed architectures to a pervasive class of dynamic networks, i.e., wireless sensor network architectures as well as to a pervasive class of static networks, i.e., network-on-chip architectures. The ultimate goal of our research is to put forward the idea of building libraries of pre-proved rules for the efficient modelling, development, and analysis of networked systems. We take into account both qualitative and quantitative analysis of networks via varied formal tool support, using a theorem prover the Rodin platform and a statistical model checker the SMC-Uppaal.

Thermal-Aware Networked Many-Core Systems

Advancements in IC processing technology has led to the innovation and growth happening in the consumer electronics sector and the evolution of the IT infrastructure supporting this exponential growth. One of the most difficult obstacles to this growth is the removal of large amount of heatgenerated by the processing and communicating nodes on the system. The scaling down of technology and the increase in power density is posing a direct and consequential effect on the rise in temperature. This has resulted in the increase in cooling budgets, and affects both the life-time reliability and performance of the system. Hence, reducing on-chip temperatures has become a major design concern for modern microprocessors. This dissertation addresses the thermal challenges at different levels for both 2D planer and 3D stacked systems. It proposes a self-timed thermal monitoring strategy based on the liberal use of on-chip thermal sensors. This makes use of noise variation tolerant and leakage current based thermal sensing for monitoring purposes. In order to study thermal management issues from early design stages, accurate thermal modeling and analysis at design time is essential. In this regard, spatial temperature profile of the global Cu nanowire for on-chip interconnects has been analyzed. It presents a 3D thermal model of a multicore system in order to investigate the effects of hotspots and the placement of silicon die layers, on the thermal performance of a modern ip-chip package. For a 3D stacked system, the primary design goal is to maximise the performance within the given power and thermal envelopes. Hence, a thermally efficient routing strategy for 3D NoC-Bus hybrid architectures has been proposed to mitigate on-chip temperatures by herding most of the switching activity to the die which is closer to heat sink. Finally, an exploration of various thermal-aware placement approaches for both the 2D and 3D stacked systems has been presented. Various thermal models have been developed and thermal control metrics have been extracted. An efficient thermal-aware application mapping algorithm for a 2D NoC has been presented. It has been shown that the proposed mapping algorithm reduces the effective area reeling under high temperatures when compared to the state of the art.

Virtual Runtime Application Partitions for Resource Management in Massively Parallel Architectures

This thesis presents a novel design paradigm, called Virtual Runtime Application Partitions (VRAP), to judiciously utilize the on-chip resources. As the dark silicon era approaches, where the power considerations will allow only a fraction chip to be powered on, judicious resource management will become a key consideration in future designs. Most of the works on resource management treat only the physical components (i.e. computation, communication, and memory blocks) as resources and manipulate the component to application mapping to optimize various parameters (e.g. energy efficiency). To further enhance the optimization potential, in addition to the physical resources we propose to manipulate abstract resources (i.e. voltage/frequency operating point, the fault-tolerance strength, the degree of parallelism, and the configuration architecture). The proposed framework (i.e. VRAP) encapsulates methods, algorithms, and hardware blocks to provide each application with the abstract resources tailored to its needs. To test the efficacy of this concept, we have developed three distinct self adaptive environments: (i) Private Operating Environment (POE), (ii) Private Reliability Environment (PRE), and (iii) Private Configuration Environment (PCE) that collectively ensure that each application meets its deadlines using minimal platform resources. In this work several novel architectural enhancements, algorithms and policies are presented to realize the virtual runtime application partitions efficiently. Considering the future design trends, we have chosen Coarse Grained Reconfigurable Architectures (CGRAs) and Network on Chips (NoCs) to test the feasibility of our approach. Specifically, we have chosen Dynamically Reconfigurable Resource Array (DRRA) and McNoC as the representative CGRA and NoC platforms. The proposed techniques are compared and evaluated using a variety of quantitative experiments. Synthesis and simulation results demonstrate VRAP significantly enhances the energy and power efficiency compared to state of the art.

Agent-based management systems for many-core platforms : rigorous design and efficient implementation

Due to various advantages such as flexibility, scalability and updatability, software intensive systems are increasingly embedded in everyday life. The constantly growing number of functions executed by these systems requires a high level of performance from the underlying platform. The main approach to incrementing performance has been the increase of operating frequency of a chip. However, this has led to the problem of power dissipation, which has shifted the focus of research to parallel and distributed computing. Parallel many-core platforms can provide the required level of computational power along with low power consumption. On the one hand, this enables parallel execution of highly intensive applications. With their computational power, these platforms are likely to be used in various application domains: from home use electronics (e.g., video processing) to complex critical control systems. On the other hand, the utilization of the resources has to be efficient in terms of performance and power consumption. However, the high level of on-chip integration results in the increase of the probability of various faults and creation of hotspots leading to thermal problems. Additionally, radiation, which is frequent in space but becomes an issue also at the ground level, can cause transient faults. This can eventually induce a faulty execution of applications. Therefore, it is crucial to develop methods that enable efficient as well as resilient execution of applications. The main objective of the thesis is to propose an approach to design agentbased systems for many-core platforms in a rigorous manner. When designing such a system, we explore and integrate various dynamic reconfiguration mechanisms into agents functionality. The use of these mechanisms enhances resilience of the underlying platform whilst maintaining performance at an acceptable level. The design of the system proceeds according to a formal refinement approach which allows us to ensure correct behaviour of the system with respect to postulated properties. To enable analysis of the proposed system in terms of area overhead as well as performance, we explore an approach, where the developed rigorous models are transformed into a high-level implementation language. Specifically, we investigate methods for deriving fault-free implementations from these models into, e.g., a hardware description language, namely VHDL.

Identification in silico d’éléments de réponse de récepteurs nucléaires impliqués dans le cancer du sein

La croissance de deux tiers des tumeurs mammaires dépend des œstrogènes. Le réseau de gènes responsable de propager les signaux prolifératifs des œstrogènes est encore mal connu. Des micropuces d’ADN de cellules de carcinome mammaire MCF7 traitées à l’œstradiol (E2) avec ou sans l’inhibiteur de synthèse protéique cycloheximide (CHX) ont permis d’identifier de nombreux gènes cibles primaires et secondaires. La séquence des promoteurs des gènes cibles a été criblée à l’aide d’une banque de 300 matrices modélisant les sites reconnus par divers facteurs de transcription. Les éléments de réponse aux œstrogènes (ERE) sont enrichis dans les promoteurs des gènes primaires. Les sites E2F sont enrichis dans les promoteurs des gènes cible secondaires. Un enrichissement similaire a été observé avec les régions liées par ERα et E2F1 en ChIP-on-chip pour chacune des catégories de gènes. La croissance des cellules de carcinome mammaire est inhibée par des traitements à l’acide rétinoïque (RA). L’analyse de micropuces d’ADN de MCF7 traitées avec RA a permis d’identifier de nombreux gènes cibles potentiels. Un enrichissement d’éléments de réponse à l’acide rétinoïque (RARE) est observable dans les promoteurs de ces gènes après avoir exclus les RARE se trouvant à l’intérieur d’éléments transposables. Des RARE présents dans des éléments transposables spécifiques aux primates sont aussi fixés in vivo dans les promoteurs de cibles connues de RA : BTG2, CASP9 et GPRC5A. Certains gènes cibles de RA dans les MCF7 sont aussi des cibles de E2, suggérant que le contrôle que ces molécules exercent sur la prolifération est en partie attribuable à des effets opposés sur un ensemble commun de gènes.

The role of the peptidyl prolyl isomerase Rrd1 in the transcriptional stress response

La régulation de la transcription est un processus complexe qui a évolué pendant des millions d’années permettant ainsi aux cellules de s’adapter aux changements environnementaux. Notre laboratoire étudie le rôle de la rapamycine, un agent immunosuppresseur et anticancéreux, qui mime la carence nutritionelle. Afin de comprendre les mécanismes impliqués dans la réponse a la rapamycine, nous recherchons des mutants de la levure Saccaromyces cerevisiae qui ont un phenotype altérée envers cette drogue. Nous avons identifié le gène RRD1, qui encode une peptidyl prolyl isomérase et dont la mutation rend les levures très résistantes à la rapamycine et il semble que se soit associé à une réponse transcriptionelle alterée. Mon projet de recherche de doctorat est d’identifier le rôle de Rrd1 dans la réponse à la rapamycine. Tout d’abord nous avons trouvé que Rrd1 interagit avec l’ARN polymérase II (RNAPII), plus spécifiquement avec son domaine C-terminal. En réponse à la rapamycine, Rrd1 induit un changement dans la conformation du domaine C-terminal in vivo permettant la régulation de l’association de RNAPII avec certains gènes. Des analyses in vitro ont également montré que cette action est directe et probablement liée à l’activité isomérase de Rrd1 suggérant un rôle pour Rrd1 dans la régulation de la transcription. Nous avons utilisé la technologie de ChIP sur micropuce pour localiser Rrd1 sur la majorité des gènes transcrits par RNAPII et montre que Rrd1 agit en tant que facteur d’élongation de RNAPII. Pour finir, des résultats suggèrent que Rrd1 n’est pas seulement impliqué dans la réponse à la rapamycine mais aussi à differents stress environnementaux, nous permettant ainsi d’établir que Rrd1 est un facteur d’élongation de la transcription requis pour la régulation de la transcription via RNAPII en réponse au stress.

A new look at reversible logic implementation of decimal adder

Reversibility plays a fundamental role when logic gates such as AND, OR, and XOR are not reversible. computations with minimal energy dissipation are considered. Hence, these gates dissipate heat and may reduce the life of In recent years, reversible logic has emerged as one of the most the circuit. So, reversible logic is in demand in power aware important approaches for power optimization with its circuits. application in low power CMOS, quantum computing and A reversible conventional BCD adder was proposed in using conventional reversible gates.

Reconfigurable Architectures for General-Purpose Computing

General-purpose computing devices allow us to (1) customize computation after fabrication and (2) conserve area by reusing expensive active circuitry for different functions in time. We define RP-space, a restricted domain of the general-purpose architectural space focussed on reconfigurable computing architectures. Two dominant features differentiate reconfigurable from special-purpose architectures and account for most of the area overhead associated with RP devices: (1) instructions which tell the device how to behave, and (2) flexible interconnect which supports task dependent dataflow between operations. We can characterize RP-space by the allocation and structure of these resources and compare the efficiencies of architectural points across broad application characteristics. Conventional FPGAs fall at one extreme end of this space and their efficiency ranges over two orders of magnitude across the space of application characteristics. Understanding RP-space and its consequences allows us to pick the best architecture for a task and to search for more robust design points in the space. Our DPGA, a fine- grained computing device which adds small, on-chip instruction memories to FPGAs is one such design point. For typical logic applications and finite- state machines, a DPGA can implement tasks in one-third the area of a traditional FPGA. TSFPGA, a variant of the DPGA which focuses on heavily time-switched interconnect, achieves circuit densities close to the DPGA, while reducing typical physical mapping times from hours to seconds. Rigid, fabrication-time organization of instruction resources significantly narrows the range of efficiency for conventional architectures. To avoid this performance brittleness, we developed MATRIX, the first architecture to defer the binding of instruction resources until run-time, allowing the application to organize resources according to its needs. Our focus MATRIX design point is based on an array of 8-bit ALU and register-file building blocks interconnected via a byte-wide network. With today's silicon, a single chip MATRIX array can deliver over 10 Gop/s (8-bit ops). On sample image processing tasks, we show that MATRIX yields 10-20x the computational density of conventional processors. Understanding the cost structure of RP-space helps us identify these intermediate architectural points and may provide useful insight more broadly in guiding our continual search for robust and efficient general-purpose computing structures.