Thermo-mechanical modelling of power electronics module structures

Power electronic modules distinguish themselves from other modules by their high power operation. These modules are used extensively in high power application markets such as aerospace, automotive, industrial and traction and drives. This paper discusses typical packaging technologies for power electronics modules. It also discusses the latest results from a UK research project investigating the physics-of-failure approach to reliability analysis and predictions for power modules. An integrated design enviroment for incorporating of affects of uncertainty into the design environment was outlined.

Effects of thermal cycling profiles on the performance of chip-on-flex assembly using anisotropic conductive films

Anisotropic conductive films (ACFs) are widely used in the electronic packaging industries because of their fine pitch potential and the assembly process is simpler compared to the soldering process. However, there are still unsolved issues in the volume productions using ACFs. The main reason is that the effects of many factors on the interconnects are not well understood. This work focuses on the performance of ACF-bonded chip-on-flex assemblies subjected to a range of thermal cycling test conditions. Both experimental and three-dimensional finite element computer modelling methods are used. It has been revealed that greater temperature ranges and longer dwell-times give rise to higher stresses in the ACF interconnects. Higher stresses are concentrated along the edges of the chip-ACF interfaces. In the experiments, the results show that higher temperature ranges and prolonged dwell times increase contact resistance values. Close examination of the microstructures along the bond-line through the scanning electron microscope (SEM) indicates that cyclic thermal loads disjoint the conductive particles from the bump of the chip and/or pad of the substrate and this is thought to be related to the increase of the contact resistance value and the failure of the ACF joints.

Comparative wetting behavior of Sn-0.7Cu and Sn-0.7Cu-0.3Ni solders on Cu and Ni substrates

Electronic packaging industries are now in great challenge to find a suitable lead-free solder as an interconnection material to replace the conventional SnPb solders. Many solders such as SnCu, SnAg, SnAgCu, SnZn, SnBi have already been proposed as the replacement but none of them has reached the physical and metallurgical properties similar to the SnPb solder. However, wetting is one of the basic problems that make the lead-free solder inferior as compared to the SnPb solder. Therefore, alloying with the help of third, fourth or fifth element is the researchers' interest to improve the wetting behavior of lead-free solders. This paper describes the comparative wetting behavior of Sn-0.7Cu and Sn-0.7Cu-0.3Ni solders on Cu and Ni substrates. Wetting balance tests were performed to assess the wetting behaviors. Three different commercial fluxes namely no-clean (NC), non-activated (R) and water soluble organic acid (WS)fluxes were used to assess the wettability for three solder bath temperatures. It was found that Sn0.7Cu-03Ni solder exhibits better wettability on Cu substrate for NC and WS fluxes whereas reverse results were found for R-type flux. In the case of Ni substrate, Sn-0.7Cu-0.3Ni solder showed better wetting behavior compared to the well-known Sn-0.7Cu solder. Among the three fluxes, R-type flux showed the worst performance. Very large contact angles were documented for both solders with this flux. Higher solder bath temperature lowered the contact angles, increased the wetting forces and enhanced the wettability. Computer modeling of wetting balance test revealed that both the wetting force and meniscus height are inversely proportional to the contact angles. Modeling results also reveal that increase in solder bath depths and radiuses do not affect significantly on the wetting behavior.

Modeling the effect of lead-free soldering on flexible substrates

Flexible Circuit Boards (FPCs) are now being widely used in the electronic industries especially in the areas of electronic packages. Due to European lead-free legislation which has been implemented since July 2006, electronic packaging industries have to switch to use in the lead-free soldering technology. This change has posed a number of challenges in terms of development of lead-free solders and compatible substrates. An increase of at least 20-50 degrees in the reflow temperature is a concern and substantial research is required to investigate a sustainable design of flexible circuit boards as carrier substrates. This paper investigates a number of design variables such as copper conductor width, type of substrate materials, effect of insulating materials, etc. Computer modeling has been used to investigate thermo-mechanical behavior, and reliability, of flexible substrates after they have been subjected to a lead- free solder processing. Results will show particular designs that behave better for a particular rise in peak reflow temperature. Also presented will be the types of failures that can occur in these substrates and what particular materials are more reliable.

Predicting the behaviour of micro-electronic displays using computational mechanics

Micro-electronic displays are indispensible devices used in high performance applications such as aerospace, medical, marine and industrial sectors.These devices provide an interface to real time mission critical devices and therefore require good optical visual performance and high reliability, all this within varied and challenging environments.

Thermo-mechanical analysis of the packaging process for micro-electronic displays

Micro-electronic displays are sensitive devices and its performance is easily affected by external environmental factors. To enable the display to perform in extreme conditions, the device must be structurally strengthened, the effects of this packaging process was investigated. A thermo-mechanical finite element analysis was used to discover potential problems in the packaging process and to improve the overall design of the device. The main concern from the analysis predicted that displacement of the borosilicate glass and the Y stress of the adhesive are important. Using this information a design which reduced the variation of displacement and kept the stress to a minimum was suggested

Analysis of the thermo mechanical effects on packaging process of performance enhanced AMLCD's and the optical performance of the display

The performance enhancement of AMLCD's has been hindered with problems encountered during the curing process, such as window framing and de-lamination of the glass and adhesive. A thermo-mechanical analysis using FEA was conducted to help optimise the design of the rugged display and enhance the optical performance.

Analyzing the performance of flexible substrates for lead-free applications

The performance of flexible substrates for lead-free applications was studied using finite element method (FEM). Firstly, the thermal induced stress in the flex substrate during the lead free solder reflow process was predicted. The shear stress at the interface between the copper track and flex was plotted. This shear stress increases with the thickness of the copper track and the thickness of the flex. Secondly, an anisotropic conductive film (ACF) flip chip was taken as a typical lead-free application of the flex substrate and the moisture effect on the reliability of ACF joints were studied using a 3D macro-micro modeling technique. It is found that the time to be saturated of an ACF flip chip is much dependent on the moisture diffusion rate in the polyimide substrate. The majority moisture diffuses into the ACF layer from the substrate side rather than the periphery of the ACF. The moisture induced stress was predicted and the predominant tensile stress was found at the interface between the conductive particle and metallization which could reduce the contact area and even cause the electrical failure

Thermal-mechanical analysis of flexible substrates during lead-free solder reflow

This paper presents modeling results about the performance of flexible substrates when subjected to higher lead-free reflow temperatures. Both adhesiveless and adhesive types of polyimide substrates were studied. Finite element (FE) models of flex substrates were built, two copper tracks located in the centre of the substrate was considered. The thermal induced shear stress in the flex substrate during the lead-free reflow process was studied and the effect of the design changes including the track thickness, flex thickness, and copper width were studied. For both types of flexes, the one of most important variables for minimizing damage to the substrate is the height of the copper tracks. The height of flex and the width of copper track show less impact. Beside of the geometry effects, the increase in reflow peak temperature can also result in a significant increase in the interfacial stress between the copper track and flex. Higher stresses were identified within the adhesive flex due to the big CTE mismatch between the copper and adhesive/dielectric

Computer modeling of a micro-manufactured one-turn inductor

The results of a finite element computer modelling analysis of a micro-manufactured one-turn magnetic inductor using the software package ANSYS 10.0 are presented. The inductor is designed for a DC-DC converter used in microelectronic devices. It consists of a copper conductor with a rectangular cross-section plated with an insulation layer and a layer of magnetic core. The analysis has focused on the effects of the frequency and the air gaps on the on the inductance values and the Joule losses in the core and conductor. It has been found that an inductor with small multiple air gaps has lower losses than an inductor with a single larger gap

Assessment of microInductors for DC-DC converters

There are increasing demands on the power density and efficiency of DC-DC power converters due to the soaring functionality and operational longevity required for today's electronic products. In addition, DC-DC converters are required to operate at new elevated frequencies in the MHz frequency regime. Typical ferrite cores, whose useable flux density falls drastically at these frequencies, have to be replaced and a method of producing compact component windings developed. In this study, two types of microinductors, pot-core and solenoid, for DC-DC converter applications have been analyzed for their performance in the MHz frequency range. The inductors were manufactured using an adapted UV-LIGA process and included electrodeposited nickel-iron and the commercial alloy Vitrovac 6025 as core materials. Using a vibrating sample magnetometer (VSM) and a Hewlett Packard 4192A LF- impedance analyzer, the inductor characteristics such as power density, efficiency, inductance and Q-factor were recorded. Experimental, finite element and analytical results were used to assess the suitability of the magnetic materials and component geometries for low MHz operation.

An analysis of a microfabricated solenoid inductor

A microscale solenoid inductor is manufactured using electrodeposition method. The inductor is designed for switching mode DC-DC converters operating at switching frequencies in the mega-Hertz range. Two magnetic core materials, electroformed permalloy Ni80 Fe20 film and Vitrovac 6025 which is a commercial magnetic film, have been analyzed using experimental and computer modeling techniques

Design and modeling challenges for high density packaging

Today most of the IC and board designs are undertaken using two-dimensional graphics tools and rule checks. System-in-package is driving three-dimensional design concepts and this is posing a number of challenges for electronic design automation (EDA) software vendors. System-in-package requires three-dimensional EDA tools and design collaboration systems with appropriate manufacturing and assembly rules for these expanding technologies. Simulation and Analysis tools today focus on one aspect of the design requirement, for example, thermal, electrical or mechanical. System-in-Package requires analysis and simulation tools that can easily capture the complex three dimensional structures and provided integrated fast solutions to issues such as thermal management, reliability, electromagnetic interference, etc. This paper discusses some of the challenges faced by the design and analysis community in providing appropriate tools to engineers for System-in-Package design

Review of the technology and reliability issues arising as optical interconnects migrate onto the circuit board

Light has the greatest information carrying potential of all the perceivable interconnect mediums; consequently, optical fiber interconnects rapidly replaced copper in telecommunications networks, providing bandwidth capacity far in excess of its predecessors. As a result the modern telecommunications infrastructure has evolved into a global mesh of optical networks with VCSEL’s (Vertical Cavity Surface Emitting Lasers) dominating the short-link markets, predominately due to their low-cost. This cost benefit of VCSELs has allowed optical interconnects to again replace bandwidth limited copper as bottlenecks appear on VSR (Very Short Reach) interconnects between co-located equipment inside the CO (Central-Office). Spurred by the successful deployment in the VSR domain and in response to both intra-board backplane applications and inter-board requirements to extend the bandwidth between IC’s (Integrated Circuits), current research is migrating optical links toward board level USR (Ultra Short Reach) interconnects. Whilst reconfigurable Free Space Optical Interconnect (FSOI) are an option, they are complicated by precise line-of-sight alignment conditions hence benefits exist in developing guided wave technologies, which have been classified into three generations. First and second generation technologies are based upon optical fibers and are both capable of providing a suitable platform for intra-board applications. However, to allow component assembly, an integral requirement for inter-board applications, 3rd generation Opto-Electrical Circuit Boards (OECB’s) containing embedded waveguides are desirable. Currently, the greatest challenge preventing the deployment of OECB’s is achieving the out-of-plane coupling to SMT devices. With the most suitable low-cost platform being to integrate the optics into the OECB manufacturing process, several research avenues are being explored although none to date have demonstrated sufficient coupling performance. Once in place, the OECB assemblies will generate new reliability issues such as assembly configurations, manufacturing tolerances, and hermetic requirements that will also require development before total off-chip photonic interconnection can truly be achieved

"System in package technology" - design for manufacture challenges

Purpose – To present key challenges associated with the evolution of system-in-package technologies and present technical work in reliability modeling and embedded test that contributes to these challenges. Design/methodology/approach – Key challenges have been identified from the electronics and integrated MEMS industrial sectors. Solutions to optimising the reliability of a typical assembly process and reducing the cost of production test have been studied through simulation and modelling studies based on technology data released by NXP and in collaboration with EDA tool vendors Coventor and Flomerics. Findings – Characterised models that deliver special and material dependent reliability data that can be used to optimize robustness of SiP assemblies together with results that indicate relative contributions of various structural variables. An initial analytical model for solder ball reliability and a solution for embedding a low cost test for a capacitive RF-MEMS switch identified as an SiP component presenting a key test challenge. Research limitations/implications – Results will contribute to the further development of NXP wafer level system-in-package technology. Limitations are that feedback on the implementation of recommendations and the physical characterisation of the embedded test solution. Originality/value – Both the methodology and associated studies on the structural reliability of an industrial SiP technology are unique. The analytical model for solder ball life is new as is the embedded test solution for the RF-MEMS switch.