Femtosecond time-resolved molecular multiphoton ionization: the Na_2 system

We report here the first experimental study of femtosecond time-resolved molecular multiphoton ionization. Femtosecond pump-probe techniques are combined with time-of-flight spectroscopy to measure transient ionization spectra of Na_2 in a molecular-beam experiment. The wave-packet motions in different molecular potentials show that incoherent contributions from direct photoionization of a singly excited state and from excitation and autoionization of a bound doubly excited molecular state determine the observed transient ionization signal.

Photochromic dithienylethene derivatives containing Ru(II) or Os(II) metal units. Sensitized photocyclization from a triplet state

Efficient photocyclization from a low-lying triplet state is reported for a photochromic dithienylperfluorocyclopentene with Ru(bpy)(3) units attached via a phenylene linker to the thiophene rings. The ring-closure reaction in the nanosecond domain is sensitized by the metal complexes. Upon photoexcitation into the lowest Ru-to-bpy (MLCT)-M-1 state followed by intersystem crossing to emitting (MLCT)-M-3 states, photoreactive (IL)-I-3 states are populated by an efficient energy-transfer process. The involvement of these (IL)-I-3 states explains the quantum yield of the photocyclization, which is independent of the excitation wavelength but decreases strongly in the presence of dioxygen. This behavior differs substantially from the photocyclization of the nonemissive dithienylperfluorocyclopentene free ligand, which occurs from the lowest (IL)-I-1 state on a picosecond time scale and is insensitive to oxygen quenching. Cyclic voltammetric studies have also been performed to gain further insight into the energetics of the system. The very high photocyclization quantum yields, far above 0.5 in both cases, are ascribed to the strong steric repulsion between the bulky substituents on the dithienylperfluorocyclopentene bridge bearing the chelating bipyridine sites or the Ru(bpy)(3) moieties, forcing the system to adopt nearly exclusively the reactive antiparallel conformation. In contrast, replacement of both Ru(II) centers by Os(II) completely prevents the photocyclization reaction upon light excitation into the low-lying Os-to-bpy (MLCT)-M-1 state. The photoreaction can only be triggered by optical population of the higher lying (IL)-I-1 excited state of the central photochromic unit, but its yield is low due to efficient energy transfer to the luminescent lowest (MLCT)-M-3 state.

Solvent-dependent modulation of metal–metal electronic interactions in a dinuclear cyanoruthenate complex: a detailed electrochemical, spectroscopic and computational study

The dinuclear complex [{Ru(CN)4}2(μ-bppz)]4− shows a strongly solvent-dependent metal–metal electronic interaction which allows the mixed-valence state to be switched from class 2 to class 3 by changing solvent from water to CH2Cl2. In CH2Cl2 the separation between the successive Ru(II)/Ru(III) redox couples is 350 mVand the IVCT band (from the UV/Vis/NIR spectroelectrochemistry) is characteristic of a borderline class II/III or class III mixed valence state. In water, the redox separation is only 110 mVand the much broader IVCT transition is characteristic of a class II mixed-valence state. This is consistent with the observation that raising and lowering the energy of the d(π) orbitals in CH2Cl2 or water, respectively, will decrease or increase the energy gap to the LUMO of the bppz bridging ligand, which provides the delocalisation pathway via electron-transfer. IR spectroelectrochemistry could only be carried out successfully in CH2Cl2 and revealed class III mixed-valence behaviour on the fast IR timescale. In contrast to this, time-resolved IR spectroscopy showed that the MLCTexcited state, which is formulated as RuIII(bppz˙−)RuII and can therefore be considered as a mixed-valence Ru(II)/Ru(III) complex with an intermediate bridging radical anion ligand, is localised on the IR timescale with spectroscopically distinct Ru(II) and Ru(III) termini. This is because the necessary electron-transfer via the bppz ligand is more difficult because of the additional electron on bppz˙− which raises the orbital through which electron exchange occurs in energy. DFT calculations reproduce the electronic spectra of the complex in all three Ru(II)/Ru(II), Ru(II)/Ru(III) and Ru(III)/Ru(III) calculations in both water and CH2Cl2 well as long as an explicit allowance is made for the presence of water molecules hydrogen-bonded to the cyanides in the model used. They also reproduce the excited-state IR spectra of both [Ru(CN)4(μ-bppz)]2– and [{Ru(CN)4}2(μ-bppz)]4− very well in both solvents. The reorganization of the water solvent shell indicates a possible dynamical reason for the longer life time of the triplet state in water compared to CH2Cl2.

Dinitrogen release from arylpentazole: A picosecond time-resolved infrared, spectroelectrochemical, and DFT computational study

p-(Dimethylamino)phenyl pentazole, DMAP-N5 (DMAP = Me2N−C6H4), was characterized by picosecond transient infrared spectroscopy and infrared spectroelectrochemistry. Femtosecond laser excitation at 310 or 330 nm produces the DMAP-N5 (S1) excited state, part of which returns to the ground state (τ = 82 ± 4 ps), while DMAP-N and DMAP-N3 (S0) are generated as double and single N2-loss photoproducts with η ≈ 0.14. The lifetime of DMAP-N5 (S1) is temperature and solvent dependent. [DMAP-N3]+ is produced from DMAP-N5 in a quasireversible, one-electron oxidation process (E1/2 = +0.67 V). Control experiments with DMAP-N3 support the findings. DFT B3LYP/6-311G** calculations were used to identify DMAP-N5 (S1), DMAP-N3 +, and DMAP-N in the infrared spectra. Both DMAP-N5 (S1) and [DMAP-N5]+ have a weakened N5 ring structure.

Study of picosecond processes of an intercalated dipyridophenazine Cr(iii) complex bound to defined sequence DNAs using transient absorption and time-resolved infrared methods

Picosecond transient absorption (TA) and time-resolved infrared (TRIR) measurements of rac-[Cr(phen)2(dppz)]3+ (1) intercalated into double-stranded guanine-containing DNA reveal that the excited state is very rapidly quenched. As no evidence was found for the transient electron transfer products, it is proposed that the back electron transfer reaction must be even faster (<3 ps).

A three-state model for the photophysics of guanine

The nonadiabatic photochemistry of the guanine molecule (2-amino-6-oxopurine) and some of its tautomers has been studied by means of the high-level theoretical ab initio quantum chemistry methods CASSCF and CASPT2. Accurate computations, based by the first time on minimum energy reaction paths, states minima, transition states, reaction barriers, and conical intersections on the potential energy hypersurfaces of the molecules lead to interpret the photochemistry of guanine and derivatives within a three-state model. As in the other purine DNA nucleobase, adenine, the ultrafast subpicosecond fluorescence decay measured in guanine is attributed to the barrierless character of the path leading from the initially populated (1)(pi pi* L-a) spectroscopic state of the molecule toward the low-lying methanamine-like conical intersection (gs/pi pi* L-a)(CI). On the contrary, other tautomers are shown to have a reaction energy barrier along the main relaxation profile. A second, slower decay is attributed to a path involving switches toward two other states, (1)(pi pi* L-b) and, in particular, (1)(n(o)pi*), ultimately leading to conical intersections with the ground state. A common framework for the ultrafast relaxation of the natural nucleobases is obtained in which the predominant role of a pi pi*-type state is confirmed.

Intrachain Energy Migration to Weak Charge-Transfer State in Polyfluorene End-Capped with Naphthalimide Derivative

Polyfluorene end-capped with N-(2-benzothiazole)-1 8-naphthalimide (PF-BNI) is a highly fluorescent material with fluorescence emission modulated by solvent polarity Its low energy excited state is assigned as a mixed configuration state between the singlet S(1) of the fluorene backbone (F) with the charge transfer (CI) of the end group BNI The triexponential fluorescence decays of PF-BNI were associated with fast energy migration to form an intrachain charge-transfer (ICCT) state polyfluorene backbone decay and ICCT deactivation Time-resolved fluorescence anisotropy exhibited biexponential relaxation with a fast component of 12-16 ps in addition to a slow one in the range 0 8-1 4 ns depending on the solvent showing that depolarization occurs from two different processes energy migration to form the ICCT state and slow rotational diffusion motion of end segments at a longer time Results from femtosecond transient absorption measurements agreed with anisotropy decay and showed a decay component of about 16 ps at 605 nm in PF BNI ascribed to the conversion of S(1) to the ICCT excited state From the ratio of asymptotic and initial amplitudes of the transient absorption measurement the efficiency of intrachain ICCT formation is estimated in 0 5 which means that on average, half of the excited state formed in a BNI-(F)(n)-BNI chain with n = 32 is converted to its low energy intrachain charge-transfer (ICCT) state

Trajectory of neutron-neutron-C-18 excited three-body state

The trajectory of the first excited Efimov state is investigated by using a renormalized zero-range three-body model for a system with two bound and one virtual two-body subsystems. The approach is applied to n-n-C-18, where the n-n virtual energy and the three-body ground state are kept fixed. It is shown that such three-body excited state goes from a bound to a virtual state when the n-C-18 binding energy is increased. Results obtained for the n-C-19 elastic cross-section at low energies also show dominance of an S-matrix pole corresponding to a bound or virtual Efimov state. It is also presented a brief discussion of these findings in the context of ultracold atom physics with tunable scattering lengths. (C) 2008 Elsevier B.V. All rights reserved.

Time dependence and energy-transfer mechanisms in Tm3+Ho3+ and Tm3+-Ho3+ co-doped alkali niobium tellurite glasses sensitized by Yb3+

Glass samples with the composition (mol%) 80TeO(2)-10Nb(2)O(5)-5K(2)O-5Li(2)O, stable against crystallization, were prepared containing Yb3+, Tm3+ and Ho3+. The energy transfer and energy back transfer mechanisms in samples containing 5% Yb3+-5% Tm3+ and 5% Yb3+-5% Tm3+-0.5% Ho3+ were estimated by measuring the absorption and fluorescence spectra together with the time dependence of the Yb3+ F-2(5/2) excited state. A good fit for the luminescence time evolution was obtained with the Yokota-Tanimoto's diffusion-limited model. The up-conversion fluorescence was also studied in 5% Yb-5% Tm. 5% Yb-0.5% Ho and 5% Yb-5% Tm-0.5% Ho tellurite glasses under laser excitation at 975 nm. Strong emission was observed from (1)G(4) and F-3(2) Tm3+ energy levels in all samples. The S-5(2) Ho3+ emission was observed only in Yb3+Ho3+ samples being completely quenched in Yb3+/Tm3+/Tm3+ samples. (C) 2001 Elsevier B.V. B.V. All rights reserved.

Time-resolved Z-scan and thermal lens measurements in Er+3 and Nd+3 doped fluoroindate glasses

In rare earth ion doped solids, a resonant non-linear refractive index, n2, appears when the laser pumps one of the ion excited states and the refractive index change is proportional to the excited state population. In these solids there are usually thermal and non-thermal lensing effects, where the non-thermal one is due to the polarizability difference, Δα, between excited and ground states of the ions. We have used the time resolved Z-scan and a mode-mismatched thermal lens technique with an Ar+ ion laser in Er+3 (20ZnF2-20SrF2-2NaF-16BaF2-6GaF3-(36 - x)InF3-xErF3, with x= 1, 2, 3 and 4 mol%) and Nd+3 (20SrF2-16BaF2-20ZnF2-2GdF3-2NaF-(40 - x)InF3-xNdF3, with x = 0.1, 0.25, 0.5-1 mol%) doped fluoroindate glasses. In both samples we found that the non-linear refraction is due to the thermal effect, while the non-thermal effect is negligible. This result indicates that in fluoride glasses Δα is very small (less than 10-26 cm3). We also measured the imaginary part of the non-linear refractive index (n″2) due to absorption saturation.

Time-resolved random laser spectroscopy of inhomogeneously broadened systems

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

Synthesis and characterization of new discotic polycyclic aromatic hydrocarbons and related pyrolytic nanostructures

Diskotische Hexa-peri-hexabenzocoronene (HBC) als molekulare, definierte graphitische Substrukturen sind bereits seit langem Gegenstand von Untersuchungen zu der Delokalisierung von π-Elektronen. In dieser Arbeit wurden zusätzlich Platin-Komplexe in das periphere Substitutionsmuster von HBC eingeführt. Dies führte zu einer Verbesserung der Emission von dem angeregten Triplett-Zustand in den Singulett-Grundzustand mit einer zusätzlichen Verlängerung der Lebensdauer des angeregten Zustandes. Zusätzlich erlaubte diese Konfiguration ein schnelles Intersystem-Crossing mittels einer verstärkten Spin-Orbit Kopplung, die sowohl bei tiefen Temperaturen, als auch bei Raumtemperatur exklusiv zu Phosphoreszenz (T1→S0) führte. Das Verständniss über solche Prozesse ist auch essentiell für die Entwicklung verbesserter opto-elektronischer Bauteile. Die Erstellung von exakt definierten molekularen Strukturen, die speziell für spezifische Interaktionen hergestellt wurden, machten eine Inkorporation von hydrophoben-hydrophilen, wasserstoffverbrückten oder elektrostatischen funktionalisierten Einheiten notwendig, um damit den supramolekularen Aufbau zu kontrollieren. Mit Imidazolium-Salzen funktionalisierte HBC Derivate wurden zu diesem Zwecke hergestellt. Eine interessante Eigenschaft dieser Moleküle ist ihre Amphiphilie. Dies gestattete die Untersuchung ihrer Eigenschaften in einem polaren Solvens und sowohl der Prozessierbarkeit als auch der Faserbildung auf Siliziumoxid-Trägern. Abhängig vom Lösungsmittel und der gewählten Konditionen konnten hochkristalline Fasern erhalten werden. Durch eine Substitution der HBCs mit langen, sterisch anspruchsvollen Seitenketten, konnte durch eine geeignete Prozessierung eine homöotrope Ausrichtung auf Substraten erreicht werden, was dieses Material interessant für photovoltaische Applikationen macht. Neuartige Polyphenylen-Metall-Komplexe mit diskotischen, linearen und dendritischen Geometrien wurden mittels einer einfachen Reaktion zwischen Co2(CO)8 und Ethinyl-Funktionalitäten in Dichlormethan hergestellt. Nach der Pyrolyse dieser Komplexe ergaben sich unterschiedliche Kohlenstoff-Nanopartikel, inklusive Nanoröhren, graphitischen Nanostäben und Kohlenstoff/Metall Hybrid Komplexe, die durch Elektronenmikroskopie untersucht wurden. Die resultierenden Strukturen waren dabei abhängig von der Zusammensetzung und Struktur der Ausgangssubstanzen. Anhand dieser Resultate ergeben sich diverse Möglichkeiten, um den Mechanismus, der zur Herstellung graphitischer Nanopartikel führt, besser zu verstehen.

Distribution of quality adjusted life expectancy: A systems approach

Statistical methods are developed which assess survival data for two attributes; (1) prolongation of life, (2) quality of life. Health state transition probabilities correspond to prolongation of life and are modeled as a discrete-time semi-Markov process. Imbedded within the sojourn time of a particular health state are the quality of life transitions. They reflect events which differentiate perceptions of pain and suffering over a fixed time period. Quality of life transition probabilities are derived from the assumptions of a simple Markov process. These probabilities depend on the health state currently occupied and the next health state to which a transition is made. Utilizing the two forms of attributes the model has the capability to estimate the distribution of expected quality adjusted life years (in addition to the distribution of expected survival times). The expected quality of life can also be estimated within the health state sojourn time making more flexible the assessment of utility preferences. The methods are demonstrated on a subset of follow-up data from the Beta Blocker Heart Attack Trial (BHAT). This model contains the structure necessary to make inferences when assessing a general survival problem with a two dimensional outcome. ^

Run-Time Scalable Hardware for Reconfigurable Systems

La optimización de parámetros tales como el consumo de potencia, la cantidad de recursos lógicos empleados o la ocupación de memoria ha sido siempre una de las preocupaciones principales a la hora de diseñar sistemas embebidos. Esto es debido a que se trata de sistemas dotados de una cantidad de recursos limitados, y que han sido tradicionalmente empleados para un propósito específico, que permanece invariable a lo largo de toda la vida útil del sistema. Sin embargo, el uso de sistemas embebidos se ha extendido a áreas de aplicación fuera de su ámbito tradicional, caracterizadas por una mayor demanda computacional. Así, por ejemplo, algunos de estos sistemas deben llevar a cabo un intenso procesado de señales multimedia o la transmisión de datos mediante sistemas de comunicaciones de alta capacidad. Por otra parte, las condiciones de operación del sistema pueden variar en tiempo real. Esto sucede, por ejemplo, si su funcionamiento depende de datos medidos por el propio sistema o recibidos a través de la red, de las demandas del usuario en cada momento, o de condiciones internas del propio dispositivo, tales como la duración de la batería. Como consecuencia de la existencia de requisitos de operación dinámicos es necesario ir hacia una gestión dinámica de los recursos del sistema. Si bien el software es inherentemente flexible, no ofrece una potencia computacional tan alta como el hardware. Por lo tanto, el hardware reconfigurable aparece como una solución adecuada para tratar con mayor flexibilidad los requisitos variables dinámicamente en sistemas con alta demanda computacional. La flexibilidad y adaptabilidad del hardware requieren de dispositivos reconfigurables que permitan la modificación de su funcionalidad bajo demanda. En esta tesis se han seleccionado las FPGAs (Field Programmable Gate Arrays) como los dispositivos más apropiados, hoy en día, para implementar sistemas basados en hardware reconfigurable De entre todas las posibilidades existentes para explotar la capacidad de reconfiguración de las FPGAs comerciales, se ha seleccionado la reconfiguración dinámica y parcial. Esta técnica consiste en substituir una parte de la lógica del dispositivo, mientras el resto continúa en funcionamiento. La capacidad de reconfiguración dinámica y parcial de las FPGAs es empleada en esta tesis para tratar con los requisitos de flexibilidad y de capacidad computacional que demandan los dispositivos embebidos. La propuesta principal de esta tesis doctoral es el uso de arquitecturas de procesamiento escalables espacialmente, que son capaces de adaptar su funcionalidad y rendimiento en tiempo real, estableciendo un compromiso entre dichos parámetros y la cantidad de lógica que ocupan en el dispositivo. A esto nos referimos con arquitecturas con huellas escalables. En particular, se propone el uso de arquitecturas altamente paralelas, modulares, regulares y con una alta localidad en sus comunicaciones, para este propósito. El tamaño de dichas arquitecturas puede ser modificado mediante la adición o eliminación de algunos de los módulos que las componen, tanto en una dimensión como en dos. Esta estrategia permite implementar soluciones escalables, sin tener que contar con una versión de las mismas para cada uno de los tamaños posibles de la arquitectura. De esta manera se reduce significativamente el tiempo necesario para modificar su tamaño, así como la cantidad de memoria necesaria para almacenar todos los archivos de configuración. En lugar de proponer arquitecturas para aplicaciones específicas, se ha optado por patrones de procesamiento genéricos, que pueden ser ajustados para solucionar distintos problemas en el estado del arte. A este respecto, se proponen patrones basados en esquemas sistólicos, así como de tipo wavefront. Con el objeto de poder ofrecer una solución integral, se han tratado otros aspectos relacionados con el diseño y el funcionamiento de las arquitecturas, tales como el control del proceso de reconfiguración de la FPGA, la integración de las arquitecturas en el resto del sistema, así como las técnicas necesarias para su implementación. Por lo que respecta a la implementación, se han tratado distintos aspectos de bajo nivel dependientes del dispositivo. Algunas de las propuestas realizadas a este respecto en la presente tesis doctoral son un router que es capaz de garantizar el correcto rutado de los módulos reconfigurables dentro del área destinada para ellos, así como una estrategia para la comunicación entre módulos que no introduce ningún retardo ni necesita emplear recursos configurables del dispositivo. El flujo de diseño propuesto se ha automatizado mediante una herramienta denominada DREAMS. La herramienta se encarga de la modificación de las netlists correspondientes a cada uno de los módulos reconfigurables del sistema, y que han sido generadas previamente mediante herramientas comerciales. Por lo tanto, el flujo propuesto se entiende como una etapa de post-procesamiento, que adapta esas netlists a los requisitos de la reconfiguración dinámica y parcial. Dicha modificación la lleva a cabo la herramienta de una forma completamente automática, por lo que la productividad del proceso de diseño aumenta de forma evidente. Para facilitar dicho proceso, se ha dotado a la herramienta de una interfaz gráfica. El flujo de diseño propuesto, y la herramienta que lo soporta, tienen características específicas para abordar el diseño de las arquitecturas dinámicamente escalables propuestas en esta tesis. Entre ellas está el soporte para el realojamiento de módulos reconfigurables en posiciones del dispositivo distintas a donde el módulo es originalmente implementado, así como la generación de estructuras de comunicación compatibles con la simetría de la arquitectura. El router has sido empleado también en esta tesis para obtener un rutado simétrico entre nets equivalentes. Dicha posibilidad ha sido explotada para aumentar la protección de circuitos con altos requisitos de seguridad, frente a ataques de canal lateral, mediante la implantación de lógica complementaria con rutado idéntico. Para controlar el proceso de reconfiguración de la FPGA, se propone en esta tesis un motor de reconfiguración especialmente adaptado a los requisitos de las arquitecturas dinámicamente escalables. Además de controlar el puerto de reconfiguración, el motor de reconfiguración ha sido dotado de la capacidad de realojar módulos reconfigurables en posiciones arbitrarias del dispositivo, en tiempo real. De esta forma, basta con generar un único bitstream por cada módulo reconfigurable del sistema, independientemente de la posición donde va a ser finalmente reconfigurado. La estrategia seguida para implementar el proceso de realojamiento de módulos es diferente de las propuestas existentes en el estado del arte, pues consiste en la composición de los archivos de configuración en tiempo real. De esta forma se consigue aumentar la velocidad del proceso, mientras que se reduce la longitud de los archivos de configuración parciales a almacenar en el sistema. El motor de reconfiguración soporta módulos reconfigurables con una altura menor que la altura de una región de reloj del dispositivo. Internamente, el motor se encarga de la combinación de los frames que describen el nuevo módulo, con la configuración existente en el dispositivo previamente. El escalado de las arquitecturas de procesamiento propuestas en esta tesis también se puede beneficiar de este mecanismo. Se ha incorporado también un acceso directo a una memoria externa donde se pueden almacenar bitstreams parciales. Para acelerar el proceso de reconfiguración se ha hecho funcionar el ICAP por encima de la máxima frecuencia de reloj aconsejada por el fabricante. Así, en el caso de Virtex-5, aunque la máxima frecuencia del reloj deberían ser 100 MHz, se ha conseguido hacer funcionar el puerto de reconfiguración a frecuencias de operación de hasta 250 MHz, incluyendo el proceso de realojamiento en tiempo real. Se ha previsto la posibilidad de portar el motor de reconfiguración a futuras familias de FPGAs. Por otro lado, el motor de reconfiguración se puede emplear para inyectar fallos en el propio dispositivo hardware, y así ser capaces de evaluar la tolerancia ante los mismos que ofrecen las arquitecturas reconfigurables. Los fallos son emulados mediante la generación de archivos de configuración a los que intencionadamente se les ha introducido un error, de forma que se modifica su funcionalidad. Con el objetivo de comprobar la validez y los beneficios de las arquitecturas propuestas en esta tesis, se han seguido dos líneas principales de aplicación. En primer lugar, se propone su uso como parte de una plataforma adaptativa basada en hardware evolutivo, con capacidad de escalabilidad, adaptabilidad y recuperación ante fallos. En segundo lugar, se ha desarrollado un deblocking filter escalable, adaptado a la codificación de vídeo escalable, como ejemplo de aplicación de las arquitecturas de tipo wavefront propuestas. El hardware evolutivo consiste en el uso de algoritmos evolutivos para diseñar hardware de forma autónoma, explotando la flexibilidad que ofrecen los dispositivos reconfigurables. En este caso, los elementos de procesamiento que componen la arquitectura son seleccionados de una biblioteca de elementos presintetizados, de acuerdo con las decisiones tomadas por el algoritmo evolutivo, en lugar de definir la configuración de las mismas en tiempo de diseño. De esta manera, la configuración del core puede cambiar cuando lo hacen las condiciones del entorno, en tiempo real, por lo que se consigue un control autónomo del proceso de reconfiguración dinámico. Así, el sistema es capaz de optimizar, de forma autónoma, su propia configuración. El hardware evolutivo tiene una capacidad inherente de auto-reparación. Se ha probado que las arquitecturas evolutivas propuestas en esta tesis son tolerantes ante fallos, tanto transitorios, como permanentes y acumulativos. La plataforma evolutiva se ha empleado para implementar filtros de eliminación de ruido. La escalabilidad también ha sido aprovechada en esta aplicación. Las arquitecturas evolutivas escalables permiten la adaptación autónoma de los cores de procesamiento ante fluctuaciones en la cantidad de recursos disponibles en el sistema. Por lo tanto, constituyen un ejemplo de escalabilidad dinámica para conseguir un determinado nivel de calidad, que puede variar en tiempo real. Se han propuesto dos variantes de sistemas escalables evolutivos. El primero consiste en un único core de procesamiento evolutivo, mientras que el segundo está formado por un número variable de arrays de procesamiento. La codificación de vídeo escalable, a diferencia de los codecs no escalables, permite la decodificación de secuencias de vídeo con diferentes niveles de calidad, de resolución temporal o de resolución espacial, descartando la información no deseada. Existen distintos algoritmos que soportan esta característica. En particular, se va a emplear el estándar Scalable Video Coding (SVC), que ha sido propuesto como una extensión de H.264/AVC, ya que este último es ampliamente utilizado tanto en la industria, como a nivel de investigación. Para poder explotar toda la flexibilidad que ofrece el estándar, hay que permitir la adaptación de las características del decodificador en tiempo real. El uso de las arquitecturas dinámicamente escalables es propuesto en esta tesis con este objetivo. El deblocking filter es un algoritmo que tiene como objetivo la mejora de la percepción visual de la imagen reconstruida, mediante el suavizado de los "artefactos" de bloque generados en el lazo del codificador. Se trata de una de las tareas más intensivas en procesamiento de datos de H.264/AVC y de SVC, y además, su carga computacional es altamente dependiente del nivel de escalabilidad seleccionado en el decodificador. Por lo tanto, el deblocking filter ha sido seleccionado como prueba de concepto de la aplicación de las arquitecturas dinámicamente escalables para la compresión de video. La arquitectura propuesta permite añadir o eliminar unidades de computación, siguiendo un esquema de tipo wavefront. La arquitectura ha sido propuesta conjuntamente con un esquema de procesamiento en paralelo del deblocking filter a nivel de macrobloque, de tal forma que cuando se varía del tamaño de la arquitectura, el orden de filtrado de los macrobloques varia de la misma manera. El patrón propuesto se basa en la división del procesamiento de cada macrobloque en dos etapas independientes, que se corresponden con el filtrado horizontal y vertical de los bloques dentro del macrobloque. Las principales contribuciones originales de esta tesis son las siguientes: - El uso de arquitecturas altamente regulares, modulares, paralelas y con una intensa localidad en sus comunicaciones, para implementar cores de procesamiento dinámicamente reconfigurables. - El uso de arquitecturas bidimensionales, en forma de malla, para construir arquitecturas dinámicamente escalables, con una huella escalable. De esta forma, las arquitecturas permiten establecer un compromiso entre el área que ocupan en el dispositivo, y las prestaciones que ofrecen en cada momento. Se proponen plantillas de procesamiento genéricas, de tipo sistólico o wavefront, que pueden ser adaptadas a distintos problemas de procesamiento. - Un flujo de diseño y una herramienta que lo soporta, para el diseño de sistemas reconfigurables dinámicamente, centradas en el diseño de las arquitecturas altamente paralelas, modulares y regulares propuestas en esta tesis. - Un esquema de comunicaciones entre módulos reconfigurables que no introduce ningún retardo ni requiere el uso de recursos lógicos propios. - Un router flexible, capaz de resolver los conflictos de rutado asociados con el diseño de sistemas reconfigurables dinámicamente. - Un algoritmo de optimización para sistemas formados por múltiples cores escalables que optimice, mediante un algoritmo genético, los parámetros de dicho sistema. Se basa en un modelo conocido como el problema de la mochila. - Un motor de reconfiguración adaptado a los requisitos de las arquitecturas altamente regulares y modulares. Combina una alta velocidad de reconfiguración, con la capacidad de realojar módulos en tiempo real, incluyendo el soporte para la reconfiguración de regiones que ocupan menos que una región de reloj, así como la réplica de un módulo reconfigurable en múltiples posiciones del dispositivo. - Un mecanismo de inyección de fallos que, empleando el motor de reconfiguración del sistema, permite evaluar los efectos de fallos permanentes y transitorios en arquitecturas reconfigurables. - La demostración de las posibilidades de las arquitecturas propuestas en esta tesis para la implementación de sistemas de hardware evolutivos, con una alta capacidad de procesamiento de datos. - La implementación de sistemas de hardware evolutivo escalables, que son capaces de tratar con la fluctuación de la cantidad de recursos disponibles en el sistema, de una forma autónoma. - Una estrategia de procesamiento en paralelo para el deblocking filter compatible con los estándares H.264/AVC y SVC que reduce el número de ciclos de macrobloque necesarios para procesar un frame de video. - Una arquitectura dinámicamente escalable que permite la implementación de un nuevo deblocking filter, totalmente compatible con los estándares H.264/AVC y SVC, que explota el paralelismo a nivel de macrobloque. El presente documento se organiza en siete capítulos. En el primero se ofrece una introducción al marco tecnológico de esta tesis, especialmente centrado en la reconfiguración dinámica y parcial de FPGAs. También se motiva la necesidad de las arquitecturas dinámicamente escalables propuestas en esta tesis. En el capítulo 2 se describen las arquitecturas dinámicamente escalables. Dicha descripción incluye la mayor parte de las aportaciones a nivel arquitectural realizadas en esta tesis. Por su parte, el flujo de diseño adaptado a dichas arquitecturas se propone en el capítulo 3. El motor de reconfiguración se propone en el 4, mientras que el uso de dichas arquitecturas para implementar sistemas de hardware evolutivo se aborda en el 5. El deblocking filter escalable se describe en el 6, mientras que las conclusiones finales de esta tesis, así como la descripción del trabajo futuro, son abordadas en el capítulo 7. ABSTRACT The optimization of system parameters, such as power dissipation, the amount of hardware resources and the memory footprint, has been always a main concern when dealing with the design of resource-constrained embedded systems. This situation is even more demanding nowadays. Embedded systems cannot anymore be considered only as specific-purpose computers, designed for a particular functionality that remains unchanged during their lifetime. Differently, embedded systems are now required to deal with more demanding and complex functions, such as multimedia data processing and high-throughput connectivity. In addition, system operation may depend on external data, the user requirements or internal variables of the system, such as the battery life-time. All these conditions may vary at run-time, leading to adaptive scenarios. As a consequence of both the growing computational complexity and the existence of dynamic requirements, dynamic resource management techniques for embedded systems are needed. Software is inherently flexible, but it cannot meet the computing power offered by hardware solutions. Therefore, reconfigurable hardware emerges as a suitable technology to deal with the run-time variable requirements of complex embedded systems. Adaptive hardware requires the use of reconfigurable devices, where its functionality can be modified on demand. In this thesis, Field Programmable Gate Arrays (FPGAs) have been selected as the most appropriate commercial technology existing nowadays to implement adaptive hardware systems. There are different ways of exploiting reconfigurability in reconfigurable devices. Among them is dynamic and partial reconfiguration. This is a technique which consists in substituting part of the FPGA logic on demand, while the rest of the device continues working. The strategy followed in this thesis is to exploit the dynamic and partial reconfiguration of commercial FPGAs to deal with the flexibility and complexity demands of state-of-the-art embedded systems. The proposal of this thesis to deal with run-time variable system conditions is the use of spatially scalable processing hardware IP cores, which are able to adapt their functionality or performance at run-time, trading them off with the amount of logic resources they occupy in the device. This is referred to as a scalable footprint in the context of this thesis. The distinguishing characteristic of the proposed cores is that they rely on highly parallel, modular and regular architectures, arranged in one or two dimensions. These architectures can be scaled by means of the addition or removal of the composing blocks. This strategy avoids implementing a full version of the core for each possible size, with the corresponding benefits in terms of scaling and adaptation time, as well as bitstream storage memory requirements. Instead of providing specific-purpose architectures, generic architectural templates, which can be tuned to solve different problems, are proposed in this thesis. Architectures following both systolic and wavefront templates have been selected. Together with the proposed scalable architectural templates, other issues needed to ensure the proper design and operation of the scalable cores, such as the device reconfiguration control, the run-time management of the architecture and the implementation techniques have been also addressed in this thesis. With regard to the implementation of dynamically reconfigurable architectures, device dependent low-level details are addressed. Some of the aspects covered in this thesis are the area constrained routing for reconfigurable modules, or an inter-module communication strategy which does not introduce either extra delay or logic overhead. The system implementation, from the hardware description to the device configuration bitstream, has been fully automated by modifying the netlists corresponding to each of the system modules, which are previously generated using the vendor tools. This modification is therefore envisaged as a post-processing step. Based on these implementation proposals, a design tool called DREAMS (Dynamically Reconfigurable Embedded and Modular Systems) has been created, including a graphic user interface. The tool has specific features to cope with modular and regular architectures, including the support for module relocation and the inter-module communications scheme based on the symmetry of the architecture. The core of the tool is a custom router, which has been also exploited in this thesis to obtain symmetric routed nets, with the aim of enhancing the protection of critical reconfigurable circuits against side channel attacks. This is achieved by duplicating the logic with an exactly equal routing. In order to control the reconfiguration process of the FPGA, a Reconfiguration Engine suited to the specific requirements set by the proposed architectures was also proposed. Therefore, in addition to controlling the reconfiguration port, the Reconfiguration Engine has been enhanced with the online relocation ability, which allows employing a unique configuration bitstream for all the positions where the module may be placed in the device. Differently to the existing relocating solutions, which are based on bitstream parsers, the proposed approach is based on the online composition of bitstreams. This strategy allows increasing the speed of the process, while the length of partial bitstreams is also reduced. The height of the reconfigurable modules can be lower than the height of a clock region. The Reconfiguration Engine manages the merging process of the new and the existing configuration frames within each clock region. The process of scaling up and down the hardware cores also benefits from this technique. A direct link to an external memory where partial bitstreams can be stored has been also implemented. In order to accelerate the reconfiguration process, the ICAP has been overclocked over the speed reported by the manufacturer. In the case of Virtex-5, even though the maximum frequency of the ICAP is reported to be 100 MHz, valid operations at 250 MHz have been achieved, including the online relocation process. Portability of the reconfiguration solution to today's and probably, future FPGAs, has been also considered. The reconfiguration engine can be also used to inject faults in real hardware devices, and this way being able to evaluate the fault tolerance offered by the reconfigurable architectures. Faults are emulated by introducing partial bitstreams intentionally modified to provide erroneous functionality. To prove the validity and the benefits offered by the proposed architectures, two demonstration application lines have been envisaged. First, scalable architectures have been employed to develop an evolvable hardware platform with adaptability, fault tolerance and scalability properties. Second, they have been used to implement a scalable deblocking filter suited to scalable video coding. Evolvable Hardware is the use of evolutionary algorithms to design hardware in an autonomous way, exploiting the flexibility offered by reconfigurable devices. In this case, processing elements composing the architecture are selected from a presynthesized library of processing elements, according to the decisions taken by the algorithm, instead of being decided at design time. This way, the configuration of the array may change as run-time environmental conditions do, achieving autonomous control of the dynamic reconfiguration process. Thus, the self-optimization property is added to the native self-configurability of the dynamically scalable architectures. In addition, evolvable hardware adaptability inherently offers self-healing features. The proposal has proved to be self-tolerant, since it is able to self-recover from both transient and cumulative permanent faults. The proposed evolvable architecture has been used to implement noise removal image filters. Scalability has been also exploited in this application. Scalable evolvable hardware architectures allow the autonomous adaptation of the processing cores to a fluctuating amount of resources available in the system. Thus, it constitutes an example of the dynamic quality scalability tackled in this thesis. Two variants have been proposed. The first one consists in a single dynamically scalable evolvable core, and the second one contains a variable number of processing cores. Scalable video is a flexible approach for video compression, which offers scalability at different levels. Differently to non-scalable codecs, a scalable video bitstream can be decoded with different levels of quality, spatial or temporal resolutions, by discarding the undesired information. The interest in this technology has been fostered by the development of the Scalable Video Coding (SVC) standard, as an extension of H.264/AVC. In order to exploit all the flexibility offered by the standard, it is necessary to adapt the characteristics of the decoder to the requirements of each client during run-time. The use of dynamically scalable architectures is proposed in this thesis with this aim. The deblocking filter algorithm is the responsible of improving the visual perception of a reconstructed image, by smoothing blocking artifacts generated in the encoding loop. This is one of the most computationally intensive tasks of the standard, and furthermore, it is highly dependent on the selected scalability level in the decoder. Therefore, the deblocking filter has been selected as a proof of concept of the implementation of dynamically scalable architectures for video compression. The proposed architecture allows the run-time addition or removal of computational units working in parallel to change its level of parallelism, following a wavefront computational pattern. Scalable architecture is offered together with a scalable parallelization strategy at the macroblock level, such that when the size of the architecture changes, the macroblock filtering order is modified accordingly. The proposed pattern is based on the division of the macroblock processing into two independent stages, corresponding to the horizontal and vertical filtering of the blocks within the macroblock. The main contributions of this thesis are: - The use of highly parallel, modular, regular and local architectures to implement dynamically reconfigurable processing IP cores, for data intensive applications with flexibility requirements. - The use of two-dimensional mesh-type arrays as architectural templates to build dynamically reconfigurable IP cores, with a scalable footprint. The proposal consists in generic architectural templates, which can be tuned to solve different computational problems. •A design flow and a tool targeting the design of DPR systems, focused on highly parallel, modular and local architectures. - An inter-module communication strategy, which does not introduce delay or area overhead, named Virtual Borders. - A custom and flexible router to solve the routing conflicts as well as the inter-module communication problems, appearing during the design of DPR systems. - An algorithm addressing the optimization of systems composed of multiple scalable cores, which size can be decided individually, to optimize the system parameters. It is based on a model known as the multi-dimensional multi-choice Knapsack problem. - A reconfiguration engine tailored to the requirements of highly regular and modular architectures. It combines a high reconfiguration throughput with run-time module relocation capabilities, including the support for sub-clock reconfigurable regions and the replication in multiple positions. - A fault injection mechanism which takes advantage of the system reconfiguration engine, as well as the modularity of the proposed reconfigurable architectures, to evaluate the effects of transient and permanent faults in these architectures. - The demonstration of the possibilities of the architectures proposed in this thesis to implement evolvable hardware systems, while keeping a high processing throughput. - The implementation of scalable evolvable hardware systems, which are able to adapt to the fluctuation of the amount of resources available in the system, in an autonomous way. - A parallelization strategy for the H.264/AVC and SVC deblocking filter, which reduces the number of macroblock cycles needed to process the whole frame. - A dynamically scalable architecture that permits the implementation of a novel deblocking filter module, fully compliant with the H.264/AVC and SVC standards, which exploits the macroblock level parallelism of the algorithm. This document is organized in seven chapters. In the first one, an introduction to the technology framework of this thesis, specially focused on dynamic and partial reconfiguration, is provided. The need for the dynamically scalable processing architectures proposed in this work is also motivated in this chapter. In chapter 2, dynamically scalable architectures are described. Description includes most of the architectural contributions of this work. The design flow tailored to the scalable architectures, together with the DREAMs tool provided to implement them, are described in chapter 3. The reconfiguration engine is described in chapter 4. The use of the proposed scalable archtieectures to implement evolvable hardware systems is described in chapter 5, while the scalable deblocking filter is described in chapter 6. Final conclusions of this thesis, and the description of future work, are addressed in chapter 7.

The photoisomerization of retinal in bacteriorhodopsin: Experimental evidence for a three-state model

The primary events in the all-trans to 13-cis photoisomerization of retinal in bacteriorhodopsin have been investigated with femtosecond time-resolved absorbance spectroscopy. Spectra measured over a broad range extending from 7000 to 22,400 cm−1 reveal features whose dynamics are inconsistent with a model proposed earlier to account for the highly efficient photoisomerization process. Emerging from this work is a new three-state model. Photoexcitation of retinal with visible light accesses a shallow well on the excited state potential energy surface. This well is bounded by a small barrier, arising from an avoided crossing that separates the Franck–Condon region from the nearby reactive region of the photoisomerization coordinate. At ambient temperatures, the reactive region is accessed with a time constant of ≈500 fs, whereupon the retinal rapidly twists and encounters a second avoided crossing region. The protein mediates the passage into the second avoided crossing region and thereby exerts control over the quantum yield for forming 13-cis retinal. The driving force for photoisomerization resides in the retinal, not in the surrounding protein. This view contrasts with an earlier model where photoexcitation was thought to access directly a reactive region of the excited-state potential and thereby drive the retinal to a twisted conformation within 100–200 fs.