Effects of switching time on output voltages of a multilevel inverter used in high frequency applications

Employing multilevel inverters is a proper solution to reduce harmonic content of output voltage and electromagnetic interference in high power electronic applications. In this paper, a new pulse width modulation method for multilevel inverters is proposed in which power devices’ on-off switching times have been considered. This method can be surveyed in order to analyse the effect of switching time on harmonic contents of output voltage in high frequency applications when a switching time is not negligible compared to a switching cycle. Fast Fourier transform calculation and analysis of output voltage waveforms and harmonic contents with regard to switching time variation are presented in this paper for a single phase (3, 5)-level inverters used in high voltage and high frequency converters. Mathematical analysis and MATLAB simulation results have been carried out to validate the proposed method.

Cross voltage control with inner hysteresis current control for multi-output boost converter

Multi-output boost (MOB) converter is a novel DC-DC converter unlike the regular boost converter, has the ability to share its total output voltage and to have different series output voltage from a given duty cycle for low and high power applications. In this paper, discrete voltage control with inner hysteresis current control loop has been proposed to keep the simplicity of the control law for the double-output MOB converter, which can be implemented by a combination of analogue and logical ICs or simple microcontroller to constrain the output voltages of MOB converter at their reference voltages against variation in load or input voltage. The salient features of the proposed control strategy are simplicity of implementation and ease to extend to multiple outputs in the MOB converter. Simulation and experimental results are presented to show the validity of control strategy.

Hybrid cascade converter topology with series connected symmetrical and asymmetrical diode-clamped H-Bridge cells

A novel H-bridge multilevel PWM converter topology based on a series connection of a high voltage (HV) diode-clamped inverter and a low voltage (LV) conventional inverter is proposed. A DC link voltage arrangement for the new hybrid and asymmetric solution is presented to have a maximum number of output voltage levels by preserving the adjacent switching vectors between voltage levels. Hence, a fifteen-level hybrid converter can be attained with a minimum number of power components. A comparative study has been carried out to present high performance of the proposed configuration to approach a very low THD of voltage and current, which leads to the possible elimination of output filter. Regarding the proposed configuration, a new cascade inverter is verified by cascading an asymmetrical diode-clamped inverter, in which nineteen levels can be synthesized in output voltage with the same number of components. To balance the DC link capacitor voltages for the maximum output voltage resolution as well as synthesise asymmetrical DC link combination, a new Multi-output Boost (MOB) converter is utilised at the DC link voltage of a seven-level H-bridge diode-clamped inverter. Simulation and hardware results based on different modulations are presented to confirm the validity of the proposed approach to achieve a high quality output voltage.

Multi-output buck-boost converter with enhanced dynamic response to load and input voltage changes

This paper presents a new multi-output DC/DC converter topology that has step-up and step-down conversion capabilities. In this topology, several output voltages can be generated which can be used in different applications such as multilevel converters with diode-clamped topology or power supplies with several voltage levels. Steady state and dynamic equations of the proposed multi-output converter have been developed, that can be used for steady state and transient analysis. Two control techniques have been proposed for this topology based on constant and dynamic hysteresis band height control to address different applications. Simulations have been performed for different operating modes and load conditions to verify the proposed topology and its control technique. Additionally, a laboratory prototype is designed and implemented to verify the simulation results.

An optimization-based algorithm for shunt active filter under distorted supply voltages

When the supply voltages are balanced and sinusoidal, load compensation can give both unity power factor (UPF) and perfect harmonic cancellation (PHC) source currents. But under distorted supply voltages, achieving both UPF and PHC currents are not possible and contradictory to each other. Hence there should be an optimal performance between these two important compensation goals. This paper presents an optimal control algorithm for load compensation under unbalanced and distorted supply voltages. In this algorithm source currents are compensated for reactive, imbalance components and harmonic distortions set by the limits. By satisfying the harmonic distortion limits and power balance, this algorithm gives the source currents which will provide the maximum achievable power factor. The detailed simulation results using MATLAB are presented to support the performance of the proposed optimal control algorithm.

Static shunt and series compensations of an SMIB system using flying capacitor multilevel inverter

The flying capacitor multilevel inverter (FCMLI) is a multiple voltage level inverter topology intended for high-power and high-voltage operations at low distortion. It uses capacitors, called flying capacitors, to clamp the voltage across the power semiconductor devices. A method for controlling the FCMLI is proposed which ensures that the flying capacitor voltages remain nearly constant using the preferential charging and discharging of these capacitors. A static synchronous compensator (STATCOM) and a static synchronous series compensator (SSSC) based on five-level flying capacitor inverters are proposed. Control schemes for both the FACTS controllers are developed and verified in terms of voltage control, power flow control, and power oscillation damping when installed in a single-machine infinite bus (SMIB) system. Simulation studies are performed using PSCAD/EMTDC to validate the efficacy of the control scheme and the FCMLI-based flexible alternating current transmission system (FACTS) controllers.

Dwell-time and run-time control for DC mass rapid transit railways

Dwell times at stations and inter-station run times are the two major operational parameters to maintain train schedule in railway service. Current practices on dwell-time and run-time control are that they are only optimal with respect to certain nominal traffic conditions, but not necessarily the current service demand. The advantages of dwell-time and run-time control on trains are therefore not fully considered. The application of a dynamic programming approach, with the aid of an event-based model, to devise an optimal set of dwell times and run times for trains under given operational constraints over a regional level is presented. Since train operation is interactive and of multi-attributes, dwell-time and run-time coordination among trains is a multi-dimensional problem. The computational demand on devising trains' instructions, a prime concern in real-time applications, is excessively high. To properly reduce the computational demand in the provision of appropriate dwell times and run times for trains, a DC railway line is divided into a number of regions and each region is controlled by a dwell- time and run-time controller. The performance and feasibility of the controller in formulating the dwell-time and run-time solutions for real-time applications are demonstrated through simulations.

AC/DC electrical characteristics of epoxy-multi wall carbon nanotube nanocomposites

Expoxy nanocomposites with multiwell carbon nanotubes (mwcnts) filler up to 0.3%wt were prepared by sheer mixing and good dispersion of the MWCNTS in the epoxy was successfully achieved. The electrical behaviour was characterized by measurements of the alternating current (ac) and direct current (dc) conductives at room temperature. Typical percolation behaviour was observed at a low percolation threshold of 0.055%. Frequency independent ac conductivity was observed at low frequencies but not at high frequencies. An equivalent circuit models was used to predict the impedence response in these nanocomposites.

Corona ions from overhead transmission voltage powerlines : effect on DC e-field and ambient particle concentration levels

Along with their essential role in electricity transmission and distribution, some powerlines also generate large concentrations of corona ions. This study aimed at comprehensive investigation of corona ions, vertical dc e-field, ambient aerosol particle charge and particle number concentration levels in the proximity of some high/sub-transmission voltage powerlines. The influence of meteorology on the instantaneous value of these parameters, and the possible existence of links or associations between the parameters measured were also statistically investigated. The presence of positive and negative polarities of corona ions was associated with variation in the mean vertical dc e-field, ambient ion and particle charge concentration level. Though these variations increased with wind speed, their values also decreased with distance from the powerlines. Predominately positive polarities of ions were recorded up to a distance of 150 m (with the maximum values recorded 50 m downwind of the powerlines). At 200 m from the source, negative ions predominated. Particle number concentration levels however remained relatively constant (103 particle cm-3) irrespective of the sampling site and distance from the powerlines. Meteorological factors of temperature, humidity and wind direction showed no influence on the electrical parameters measured. The study also discovered that e-field measurements were not necessarily a true representation of the ground-level ambient ion/particle charge concentrations.

Development of a composite line source emission model for traffic interrupted microenvironments and its application in particle number emissions at a bus station

A composite line source emission (CLSE) model was developed to specifically quantify exposure levels and describe the spatial variability of vehicle emissions in traffic interrupted microenvironments. This model took into account the complexity of vehicle movements in the queue, as well as different emission rates relevant to various driving conditions (cruise, decelerate, idle and accelerate), and it utilised multi-representative segments to capture the accurate emission distribution for real vehicle flow. Hence, this model was able to quickly quantify the time spent in each segment within the considered zone, as well as the composition and position of the requisite segments based on the vehicle fleet information, which not only helped to quantify the enhanced emissions at critical locations, but it also helped to define the emission source distribution of the disrupted steady flow for further dispersion modelling. The model then was applied to estimate particle number emissions at a bi-directional bus station used by diesel and compressed natural gas fuelled buses. It was found that the acceleration distance was of critical importance when estimating particle number emission, since the highest emissions occurred in sections where most of the buses were accelerating and no significant increases were observed at locations where they idled. It was also shown that emissions at the front end of the platform were 43 times greater than at the rear of the platform. Although the CLSE model is intended to be applied in traffic management and transport analysis systems for the evaluation of exposure, as well as the simulation of vehicle emissions in traffic interrupted microenvironments, the bus station model can also be used for the input of initial source definitions in future dispersion models.

Prospective bus rapid transit scenarios for pilot corridor in Dhaka

Dhaka doesn’t have a mature transport system. Lacking in institutional arrangements, policy and planning, and law enforcement, the transport system operates has developed ad hoc and is situationally problematic. Absence of proper coordination between modes, poor public transport system, inadequate pedestrian facilities, and environmental degradation justify full consideration of Bus Rapid Transit (BRT) in Dhaka. BRT centres on sustainable transport principles. BRT is a system, which is capable to mitigate Dhaka’s transport problem if properly planned. In Strategic transport plan of Dhaka three BRT transport corridor has been proposed and BRT pre-feasibility study came up with one pilot corridor for early implementation of BRT. This paper first reviews international best practices then explores various BRT system packages and evaluates the suitability of these BRT packages by analyzing current bus service condition and physical and geometric configuration along the BRT pilot corridor. It concludes by proposing some BRT scenarios, which can be considered for further evaluation with respect to speed, delay, travel time and environmental pollution.

Optimal voltage support mechanism in distribution networks

Optimal scheduling of voltage regulators (VRs), fixed and switched capacitors and voltage on customer side of transformer (VCT) along with the optimal allocaton of VRs and capacitors are performed using a hybrid optimisation method based on discrete particle swarm optimisation and genetic algorithm. Direct optimisation of the tap position is not appropriate since in general the high voltage (HV) side voltage is not known. Therefore, the tap setting can be determined give the optimal VCT once the HV side voltage is known. The objective function is composed of the distribution line loss cost, the peak power loss cost and capacitors' and VRs' capital, operation and maintenance costs. The constraints are limits on bus voltage and feeder current along with VR taps. The bus voltage should be maintained within the standard level and the feeder current should not exceed the feeder-rated current. The taps are to adjust the output voltage of VRs between 90 and 110% of their input voltages. For validation of the proposed method, the 18-bus IEEE system is used. The results are compared with prior publications to illustrate the benefit of the employed technique. The results also show that the lowest cost planning for voltage profile will be achieved if a combination of capacitors, VRs and VCTs is considered.

The influence of platform walking on BRT station bus dwell time estimation

The common approach to estimate bus dwell time at a BRT station platform is to apply the traditional dwell time methodology derived for suburban bus stops. Current dwell time models are sensitive towards bus type, fare collection policy along with the number of boarding and alighting passengers. However, they fall short in accounting for the effects of passenger/s walking on a relatively longer BRT station platform. Analysis presented in this paper shows that the average walking time of a passenger at BRT platform is 10 times more than that of bus stop. The requirement of walking to the bus entry door at the BRT station platform may lead to the bus experiencing a higher dwell time. This paper presents a theory for a BRT network which explains the loss of station capacity during peak period operation. It also highlights shortcomings of present available bus dwell time models suggested for the analysis of BRT operation.

Test and evaluation of non conventional instrument transformers and sampled value process bus on Powerlink's transmission network

IEC 61850 Process Bus technology has the potential to improve cost, performance and reliability of substation design. Substantial costs associated with copper wiring (designing, documentation, construction, commissioning and troubleshooting) can be reduced with the application of digital Process Bus technology, especially those based upon international standards. An IEC 61850-9-2 based sampled value Process Bus is an enabling technology for the application of Non-Conventional Instrument Transformers (NCIT). Retaining the output of the NCIT in its native digital form, rather than conversion to an analogue output, allows for improved transient performance, dynamic range, safety, reliability and reduced cost. In this paper we report on a pilot installation using NCITs communicating across a switched Ethernet network using the UCAIug Implementation Guideline for IEC 61850-9-2 (9-2 Light Edition or 9-2LE). This system was commissioned in a 275 kV Line Reactor bay at Powerlink Queensland’s Braemar substation in 2009, with sampled value protection IEDs 'shadowing' the existing protection system. The results of commissioning tests and twelve months of service experience using a Fibre Optic Current Transformer (FOCT) from Smart Digital Optics (SDO) are presented, including the response of the system to fault conditions. A number of remaining issues to be resolved to enable wide-scale deployment of NCITs and IEC 61850-9-2 Process Bus technology are also discussed.

Natural balancing of flying capacitor voltages in multicell inverter under PD carrier-based PWM

The flying capacitor multicell inverter (FCMI) possesses natural balancing property. With the phase-shifted (PS) carrier-based scheme, natural balancing can be achieved in a straightforward manner. However, to achieve natural balancing with the harmonically optimal phase-disposition (PD) carrierbased scheme, the conventional approaches require (n-1) x (n-1) trapezoidal carrier signals for an n-level inverter, which is (n-1) x (n-2) times more than that in the standard PD scheme. This paper proposes two improved natural balancing strategies for FMI under PD scheme, which use the same (n-1) carrier signals as used in the standard PD scheme. In the first scheme, on-line detection is performed of the band in which the modulation signal is located, corresponding period number of the carrier, and rising or falling half cycle of the carrier waveform to generate the switching signals based on certain rules. In the second strategy, the output voltage level selection is first processed and the switching signals are then generated according to a rule based on preferential cell selection algorithm. These methods are easy to use and can be simply implemented as compared to the other available methods. Simulation and experimental results are presented for a five-level inverter to verify these proposed schemes.