Organic functionalisation, doping and characterisation of semiconductor surfaces for future CMOS device applications

Organic Functionalisation, Doping and Characterisation of Semiconductor Surfaces for Future CMOS Device Applications Semiconductor materials have long been the driving force for the advancement of technology since their inception in the mid-20th century. Traditionally, micro-electronic devices based upon these materials have scaled down in size and doubled in transistor density in accordance with the well-known Moore’s law, enabling consumer products with outstanding computational power at lower costs and with smaller footprints. According to the International Technology Roadmap for Semiconductors (ITRS), the scaling of metal-oxide-semiconductor field-effect transistors (MOSFETs) is proceeding at a rapid pace and will reach sub-10 nm dimensions in the coming years. This scaling presents many challenges, not only in terms of metrology but also in terms of the material preparation especially with respect to doping, leading to the moniker “More-than-Moore”. Current transistor technologies are based on the use of semiconductor junctions formed by the introduction of dopant atoms into the material using various methodologies and at device sizes below 10 nm, high concentration gradients become a necessity. Doping, the controlled and purposeful addition of impurities to a semiconductor, is one of the most important steps in the material preparation with uniform and confined doping to form ultra-shallow junctions at source and drain extension regions being one of the key enablers for the continued scaling of devices. Monolayer doping has shown promise to satisfy the need to conformally dope at such small feature sizes. Monolayer doping (MLD) has been shown to satisfy the requirements for extended defect-free, conformal and controllable doping on many materials ranging from the traditional silicon and germanium devices to emerging replacement materials such as III-V compounds This thesis aims to investigate the potential of monolayer doping to complement or replace conventional doping technologies currently in use in CMOS fabrication facilities across the world.

An ether-functionalised cyclic sulfonium based ionic liquid as an electrolyte for electrochemical double layer capacitors

A novel cyclic sulfonium cation-based ionic liquid (IL) with an ether-group appendage and the bis{(trifluoromethyl)sulfonyl}imide anion was synthesised and developed for electrochemical double layer capacitor (EDLC) testing. The synthesis and chemical-physical characterisation of the ether-group containing IL is reported in parallel with a similarly sized alkyl-functionalised sulfonium IL. Results of the chemical-physical measurements demonstrate how important transport properties, i.e. viscosity and conductivity, can be promoted through the introduction of the ether-functionality without impeding thermal, chemical or electrochemical stability of the IL. Although the apparent transport properties are improved relative to the alkyl-functionalised analogue, the ether-functionalised sulfonium cation-based IL exhibits moderately high viscosity, and poorer conductivity, when compared to traditional EDLC electrolytes based on organic solvents (propylene carbonate and acetonitrile). Electrochemical testing of the ether-functionalised sulfonium IL was conducted using activated carbon composite electrodes to inspect the performance of the IL as a solvent-free electrolyte for EDLC application. Good cycling stability was achieved over the studied range and the performance was comparable to other solvent free,
IL-based EDLC systems. Nevertheless, limitations of the attainable performance are primarily the result of sluggish transport properties and a restricted operative voltage of the IL, thus highlighting key aspects of this field which require further attention.

High-Performance WSe2 CMOS Technology and Integrated Circuits.

Because of their extraordinary structural and electrical properties, two dimensional materials are currently being pursued for applications such as thin-film transistors and integrated circuit. One of the main challenges that still needs to be overcome for these applications is the fabrication of air-stable transistors with industry-compatible complementary metal oxide semiconductor (CMOS) technology. In this work, we experimentally demonstrate a novel high performance air-stable WSe2 CMOS technology with almost ideal voltage transfer characteristic, full logic swing and high noise margin with different supply voltages. More importantly, the inverter shows large voltage gain (~38) and small static power (Pico-Watts), paving the way for low power electronic system in 2D materials.

Binary Mixtures of 1-Butyl-1-Methylpyrrolidinium Bis{(trifluoromethyl)Sulfonyl}Imide and Aliphatic Nitrile Solvents As Electrolyte for Electrochemical Double Layer Capacitors (Invited).

Electrochemical double layer capacitors (EDLCs), also known as supercapacitors, are promising energy storage devices, especially when considering high power applications [1]. EDLCs can be charged and discharged within seconds [1], feature high power (10 kW·kg-1) and an excellent cycle life (>500,000 cycles). All these properties are a result of the energy storage process of EDLCs, which relies on storing energy by charge separation instead of chemical redox reactions, as utilized in battery systems. Upon charging, double layers are forming at the electrode/electrolyte interface consisting of the electrolyte’s ions and electric charges at the electrode surface.In state-of-the-art EDLC systems activated carbons (AC) are used as active materials and tetraethylammonium tetrafluoroborate ([Et4N][BF4]) dissolved in organic solvents like propylene carbonate (PC) or acetonitrile (ACN) are commonly used as the electrolyte [2]. These combinations of materials allow operative voltages up to 2.7 V - 2.8 V and an energy in the order of 5 Wh·kg-1[3]. The energy of EDLCs is dependent on the square of the operative voltage, thus increasing the usable operative voltage has a strong effect on the delivered energy of the device [1]. Due to their high electrochemical stability, ionic liquids (ILs) were thoroughly investigated as electrolytes for EDLCs, as well as, batteries, enabling high operating voltages as high as 3.2 V - 3.5 V for the former [2]. While their unique ionic structure allows the usage of neat ILs as electrolyte in EDLCs, ILs suffer from low conductivity and high viscosity increasing the intrinsic resistance and, as a result, a lower power output of the device. In order to overcome this issue, the usage of blends of ionic liquids and organic solvents has been considered a feasible strategy as they combine high usable voltages, while still retaining good transport properties at the same time.In our recent work the ionic liquid 1-butyl-1-methylpyrrolidinium bis{(trifluoromethyl)sulfonyl}imide ([Pyrr14][TFSI]) was combined with two nitrile-based organic solvents, namely butyronitrile (BTN) and adiponitrile (ADN), and the resulting blends were investing regarding their usage in electrochemical double layer capacitors [4,5]. Firstly, the physicochemical properties were investigated, showing good transport properties for both blends, which are similar to the state-of-the-art combination of [Et4N][BF4] in PC. Secondly, the electrochemical properties for EDLC application were studied in depth revealing a high electrochemical stability with a maximum operative voltage as high as 3.7 V. In full cells these high voltage organic solvent based electrolytes have a good performance in terms of capacitance and an acceptable equivalent series resistance at cut-off voltages of 3.2 and 3.5 V. However, long term stability tests by float testing revealed stability issues when using a maximum voltage of 3.5 V for prolonged time, whereas at 3.2 V no such issues are observed (Fig. 1).Considering the obtained results, the usage of ADN and BTN blends with [Pyrr14][TFSI] in EDLCs appears to be an interesting alternative to state-of-the-art organic solvent based electrolytes, allowing the usage of higher maximum operative voltages while having similar transport properties to 1 mol∙dm-3 [Et4N][BF4] in PC at the same time.

Conception, caractérisation et optimisation de SPAD en technologie Dalsa HV CMOS 0.8 μm pour intégration dans un 3D-SiPM

Résumé : Les photodiodes à avalanche monophotonique (SPAD) sont d'intérêts pour les applications requérant la détection de photons uniques avec une grande résolution temporelle, comme en physique des hautes énergies et en imagerie médicale. En fait, les matrices de SPAD, souvent appelés photomultiplicateurs sur silicium (SiPM), remplacent graduellement les tubes photomultiplicateurs (PMT) et les photodiodes à avalanche (APD). De plus, il y a une tendance à utiliser les matrices de SPAD en technologie CMOS afin d'obtenir des pixels intelligents optimisés pour la résolution temporelle. La fabrication de SPAD en technologie CMOS commerciale apporte plusieurs avantages par rapport aux procédés optoélectroniques comme le faible coût, la capacité de production, l'intégration d'électronique et la miniaturisation des systèmes. Cependant, le défaut principal du CMOS est le manque de flexibilité de conception au niveau de l'architecture du SPAD, causé par le caractère fixe et standardisé des étapes de fabrication en technologie CMOS. Un autre inconvénient des matrices de SPAD CMOS est la perte de surface photosensible amenée par la présence de circuits CMOS. Ce document présente la conception, la caractérisation et l'optimisation de SPAD fabriqués dans une technologie CMOS commerciale (Teledyne DALSA 0.8µm HV CMOS - TDSI CMOSP8G). Des modifications de procédé sur mesure ont été introduites en collaboration avec l'entreprise CMOS pour optimiser les SPAD tout en gardant la compatibilité CMOS. Les matrices de SPAD produites sont dédiées à être intégrées en 3D avec de l'électronique CMOS économique (TDSI) ou avec de l'électronique CMOS submicronique avancée, produisant ainsi un SiPM 3D numérique. Ce SiPM 3D innovateur vise à remplacer les PMT, les APD et les SiPM commerciaux dans les applications à haute résolution temporelle. L'objectif principal du groupe de recherche est de développer un SiPM 3D avec une résolution temporelle de 10 ps pour usage en physique des hautes énergies et en imagerie médicale. Ces applications demandent des procédés fiables avec une capacité de production certifiée, ce qui justifie la volonté de produire le SiPM 3D avec des technologies CMOS commerciales. Ce mémoire étudie la conception, la caractérisation et l'optimisation de SPAD fabriqués en technologie TDSI-CMOSP8G.

Développement de procédés technologiques pour une intégration 3D monolithique de dispositifs nanoélectroniques sur CMOS

Résumé : Le transistor monoélectronique (SET) est un dispositif nanoélectronique très attractif à cause de son ultra-basse consommation d’énergie et sa forte densité d’intégration, mais il n’a pas les capacités suffisantes pour pouvoir remplacer complètement la technologie CMOS. Cependant, la combinaison de la technologie SET avec celle du CMOS est une voie intéressante puisqu’elle permet de profiter des forces de chacune, afin d’obtenir des circuits avec des fonctionnalités additionnelles et uniques. Cette thèse porte sur l’intégration 3D monolithique de nanodispositifs dans le back-end-of-line (BEOL) d’une puce CMOS. Cette approche permet d’obtenir des circuits hybrides et de donner une valeur ajoutée aux puces CMOS actuelles sans altérer le procédé de fabrication du niveau des transistors MOS. L’étude se base sur le procédé nanodamascène classique développé à l’UdeS qui a permis la fabrication de dispositifs nanoélectroniques sur un substrat de SiO2. Ce document présente les travaux réalisés sur l’optimisation du procédé de fabrication nanodamascène, afin de le rendre compatible avec le BEOL de circuits CMOS. Des procédés de gravure plasma adaptés à la fabrication de nanostructures métalliques et diélectriques sont ainsi développés. Le nouveau procédé nanodamascène inverse a permis de fabriquer des jonctions MIM et des SET métalliques sur une couche de SiO2. Les caractérisations électriques de MIM et de SET formés avec des jonctions TiN/Al2O3 ont permis de démontrer la présence de pièges dans les jonctions et la fonctionnalité d’un SET à basse température (1,5 K). Le transfert de ce procédé sur CMOS et le procédé d’interconnexions verticales sont aussi développés par la suite. Finalement, un circuit 3D composé d’un nanofil de titane connecté verticalement à un transistor MOS est réalisé et caractérisé avec succès. Les résultats obtenus lors de cette thèse permettent de valider la possibilité de co-intégrer verticalement des dispositifs nanoélectroniques avec une technologie CMOS, en utilisant un procédé de fabrication compatible.

Spatial and temporal measurements using polyoxometalate, enzymatic and biofilm layers on a CMOS 0.35 μm 64 X 64-pixel I.S.F.E.T. array sensor

This thesis presents the achievements and scientific work conducted using a previously designed and fabricated 64 x 64-pixel ion camera with the use of a 0.35 μm CMOS technology. We used an array of Ion Sensitive Field Effect Transistors (ISFETs) to monitor and measure chemical and biochemical reactions in real time. The area of our observation was a 4.2 x 4.3 mm silicon chip while the actual ISFET array covered an area of 715.8 x 715.8 μm consisting of 4096 ISFET pixels in total with a 1 μm separation space among them. The ion sensitive layer, the locus where all reactions took place was a silicon nitride layer, the final top layer of the austriamicrosystems 0.35 μm CMOS technology used. Our final measurements presented an average sensitivity of 30 mV/pH. With the addition of extra layers we were able to monitor a 65 mV voltage difference during our experiments with glucose and hexokinase, whereas a difference of 85 mV was detected for a similar glucose reaction mentioned in literature, and a 55 mV voltage difference while performing photosynthesis experiments with a biofilm made from cyanobacteria, whereas a voltage difference of 33.7 mV was detected as presented in literature for a similar cyanobacterial species using voltamemtric methods for detection. To monitor our experiments PXIe-6358 measurement cards were used and measurements were controlled by LabVIEW software. The chip was packaged and encapsulated using a PGA-100 chip carrier and a two-component commercial epoxy. Printed circuit board (PCB) has also been previously designed to provide interface between the chip and the measurement cards.

The Effect of Package Geometry on Moisture Driven Degradation of Polymer Aluminum Capacitors

Polymer aluminum electrolytic capacitors were introduced to provide an alternative to liquid electrolytic capacitors. Polymer electrolytic capacitor electric parameters of capacitance and ESR are less temperature dependent than those of liquid aluminum electrolytic capacitors. Furthermore, the electrical conductivity of the polymer used in these capacitors (poly-3,4ethylenedioxithiophene) is orders of magnitude higher than the electrolytes used in liquid aluminum electrolytic capacitors, resulting in capacitors with much lower equivalent series resistance which are suitable for use in high ripple-current applications. The presence of the moisture-sensitive polymer PEDOT introduces concerns on the reliability of polymer aluminum capacitors in high humidity conditions. Highly accelerated stress testing (or HAST) (110ºC, 85% relative humidity) of polymer aluminum capacitors in which the parts were subjected to unbiased HAST conditions for 700 hours was done to understand the design factors that contribute to the susceptibility to degradation of a polymer aluminum electrolytic capacitor exposed to HAST conditions. A large scale study involving capacitors of different electrical ratings (2.5V – 16V, 100µF – 470 µF), mounting types (surface-mount and through-hole) and manufacturers (6 different manufacturers) was done to determine a relationship between package geometry and reliability in high temperature-humidity conditions. A Geometry-Based HAST test in which the part selection limited variations between capacitor samples to geometric differences only was done to analyze the effect of package geometry on humidity-driven degradation more closely. Raman spectroscopy, x-ray imaging, environmental scanning electron microscopy, and destructive analysis of the capacitors after HAST exposure was done to determine the failure mechanisms of polymer aluminum capacitors under high temperature-humidity conditions.

The development of planar high-K/III-V p-channel MOSFETs for post-silicon CMOS

Conventional Si complementary-metal-oxide-semiconductor (CMOS) scaling is fast approaching its limits. The extension of the logic device roadmap for future enhancements in transistor performance requires non-Si materials and new device architectures. III-V materials, due to their superior electron transport properties, are well poised to replace Si as the channel material beyond the 10nm technology node to mitigate the performance loss of Si transistors from further reductions in supply voltage to minimise power dissipation in logic circuits. However several key challenges, including a high quality dielectric/III-V gate stack, a low-resistance source/drain (S/D) technology, heterointegration onto a Si platform and a viable III-V p-metal-oxide-semiconductor field-effect-transistor (MOSFET), need to be addressed before III-Vs can be employed in CMOS. This Thesis specifically addressed the development and demonstration of planar III-V p-MOSFETs, to complement the n-MOSFET, thereby enabling an all III-V CMOS technology to be realised. This work explored the application of InGaAs and InGaSb material systems as the channel, in conjunction with Al2O3/metal gate stacks, for p-MOSFET development based on the buried-channel flatband device architecture. The body of work undertaken comprised material development, process module development and integration into a robust fabrication flow for the demonstration of p-channel devices. The parameter space in the design of the device layer structure, based around the III-V channel/barrier material options of In_x≥0.53Ga_1-xAs/In_0.52Al_0.48As and In_x≥0.1Ga_1-xSb/AlSb, was systematically examined to improve hole channel transport. A mobility of 433 cm²/Vs, the highest room temperature hole mobility of any InGaAs quantum-well channel reported to date, was obtained for the In_0.85Ga_0.15As (2.1% strain) structure. S/D ohmic contacts were developed based on thermally annealed Au/Zn/Au metallisation and validated using transmission line model test structures. The effects of metallisation thickness, diffusion barriers and de-oxidation conditions were examined. Contacts to InGaSb-channel structures were found to be sensitive to de-oxidation conditions. A fabrication process, based on a lithographically-aligned double ohmic patterning approach, was realised for deep submicron gate-to-source/drain gap (L_side) scaling to minimise the access resistance, thereby mitigating the effects of parasitic S/D series resistance on transistor performance. The developed process yielded gaps as small as 20nm. For high-k integration on GaSb, ex-situ ammonium sulphide ((NH₄)₂S) treatments, in the range 1%-22%, for 10min at 295K were systematically explored for improving the electrical properties of the Al₂O₃/GaSb interface. Electrical and physical characterisation indicated the 1% treatment to be most effective with interface trap densities in the range of 4 - 10×10¹²cm^-2eV^-1 in the lower half of the bandgap. An extended study, comprising additional immersion times at each sulphide concentration, was further undertaken to determine the surface roughness and the etching nature of the treatments on GaSb. A number of p-MOSFETs based on III-V-channels with the most promising hole transport and integration of the developed process modules were successfully demonstrated in this work. Although the non-inverted InGaAs-channel devices showed good current modulation and switch-off characteristics, several aspects of performance were non-ideal; depletion-mode operation, modest drive current (I_d,sat=1.14mA/mm), double peaked transconductance (g_m=1.06mS/mm), high subthreshold swing (SS=301mV/dec) and high on-resistance (R_on=845kΩ.μm). Despite demonstrating substantial improvement in the on-state metrics of I_d,sat (11×), g_m (5.5×) and R_on (5.6×), inverted devices did not switch-off. Scaling gate-to-source/drain gap (L_side) from 1μm down to 70nm improved I_d,sat (72.4mA/mm) by a factor of 3.6 and gm (25.8mS/mm) by a factor of 4.1 in inverted InGaAs-channel devices. Well-controlled current modulation and good saturation behaviour was observed for InGaSb-channel devices. In the on-state In_0.3Ga_0.7Sb-channel (I_d,sat=49.4mA/mm, g_m=12.3mS/mm, R_on=31.7kΩ.μm) and In_0.4Ga_0.6Sb-channel (I_d,sat=38mA/mm, g_m=11.9mS/mm, R_on=73.5kΩ.μm) devices outperformed the InGaAs-channel devices. However the devices could not be switched off. These findings indicate that III-V p-MOSFETs based on InGaSb as opposed to InGaAs channels are more suited as the p-channel option for post-Si CMOS.

Improvement of carbon materials performance by nitrogen functional groups in electrochemical capacitors in organic electrolyte at severe conditions

N-doped activated carbon fibers have been synthesized by using chemically polymerized aniline as source of nitrogen. Commercial activated carbon fibers (A20) were chemically modified with a thin film of polyaniline (PANI) inside the microporosity of the carbon fibers. The modified activated carbon fibers were carbonized at 600 and 800 °C, respectively. In this way, activated carbon fibers modified with surface nitrogen species were prepared in order to analyze their influence in the performance of electrochemical capacitors in organic electrolyte. Symmetric capacitors were made of activated carbon fibers and N-doped activated carbon fibers and tested in a two-electrode cell configuration, using triethylmethylammonium tetrafluoroborate/propylene carbonate (TEMA-BF4/PC) as electrolyte. The effect of nitrogen species in the degradation or stabilization of the capacitor has been analyzed through floating durability tests using a high voltage charging (3.2 V). The results show higher stabilizing effect in carbonized samples (N-ACF) than in non-carbonized samples and pristine activated carbon fibers, which is attributed to the presence of aromatic nitrogen group, especially positively charged N-functional groups.

Post-CMOS compatible high-throughput fabrication of AIN-based piezoelectric microcantilevers

A post-complementary metal oxide semiconductor (CMOS) compatible microfabrication process of piezoelectric cantilevers has been developed. The fabrication process is suitable for standard silicon technology and provides low-cost and high-throughput manufacturing. This work reports design, fabrication and characterization of piezoelectric cantilevers based on aluminum nitride (AlN) thin films synthesized at room temperature. The proposed microcantilever system is a sandwich structure composed of chromium (Cr) electrodes and a sputtered AlN film. The key issue for cantilever fabrication is the growth at room temperature of the AlN layer by reactive sputtering, making possible the innovative compatibility of piezoelectric MEMS devices with CMOS circuits already processed. AlN and Cr have been etched by inductively coupled plasma (ICP) dry etching using a BCl3–Cl2–Ar plasma chemistry. As part of the novelty of the post-CMOS micromachining process presented here, a silicon Si (1 0 0) wafer has been used as substrate as well as the sacrificial layer used to release the microcantilevers. In order to achieve this, the Si surface underneath the structure has been wet etched using an HNA (hydrofluoric acid + nitric acid + acetic acid) based solution. X-ray diffraction (XRD) characterization indicated the high crystalline quality of the AlN film. An atomic force microscope (AFM) has been used to determine the Cr electrode surface roughness. The morphology of the fabricated devices has been studied by scanning electron microscope (SEM). The cantilevers have been piezoelectrically actuated and their out-of-plane vibration modes were detected by vibrometry.

Mixed Signal CMOS ASIC mit integrierten frei verschaltbaren Photodioden und Signalvorverarbeitung zur adaptierbaren Ortsfrequenzfilterung

Die vorliegende Arbeit untersucht die Integrierbarkeit von Photodioden und zugehörigen Signalvorverarbeitungen mit dem preisgünstigen Standard-0,5-µm-Prozess bzw. 0,35-µm-CMOS-Prozess. Als Pilotanwendung wurde die Realisierung eines flexiblen Ortfrequenzfilters vorgesehen, der durch die Verschaltung und die Wichtung von integrierten Photodioden gebildet wird. Mit einem integrierten optoelektronischen Bauteil (Opto-ASIC) sollte die Funktionaliät eines CORREVIT®-Sensors (der Firma Corrsys 3D Sensors) aus Prismengitter, Feldlinse, Photodioden und Vorverstärker nachgebildet und seine Funktionalität erweitert werden. Dazu sollte dieser Opto-ASIC eine Photodiodenzeile enthalten, die im Unterschied zu dem bestehenden CORREVIT®-Sensor durch die programmierbare Verschaltung und die Wichtung der Signale der Photodioden unterschiedliche Ortsfrequenz-Bandpassfilter erzeugen sollte, um unterschiedliche Gitterkonstanten (Ortsfrequenzen) zur optimalen Anpassung des Sensors an die jeweilige Oberfläche realisieren zu können. Neue Ortsfrequenzfilter können mehrere Fehlereinflüsse handelsüblicher Sensoren größtenteils vermeiden. Dazu sollten die Filter symmetrisch sein und die Summen ihrer Wichtungen sollten zu Null werden. Die Photodioden als Elementarbauteile der Ortsfilter werden genau untersucht und optimiert, da die Eigenschaften der Photodioden die Qualität der Messsignale stark beeinflussen. Mit einem neuen entwickelten Messverfahren lässt sich die lokale Empfindlichekeit auf dem ASIC mit einer Auflösung ab 0,5 µm messen. Durch diese Messungen konnte die optimale Geometrie festgelegt werden. Es konnte gezeigt werden, dass die Empfindlichkeit der Photodioden in den Randbereichen (lateraler Bereich) erheblich höher ist als im Tiefenbereich (vertikaler Bereich). Es wurde deshalb vorgeschlagen, die Photodioden, die dann abhängig von der Struktur als Fingerdiode oder geschlitzte Diode bezeichnet wurden, in viele Teilflächen zu unterteilen. Zur Realisierung des Ortsfrequenzfilters wurde ein Schaltungssystem zur Signalverarbeitung und Verschaltung der Photodioden entwickelt. Dieser Schaltkreis setzt sich aus Transimpedanzverstärker, Diffenzverstärker, Schalter und einem Schieberegister zusammen.

Real-Time Voltage Regulation in Power Distribution System Using Fuzzy Control

Two different fuzzy approaches to voltage control in electric power distribution systems are introduced in this paper. The real-time controller in each case would act on power transformers equipped with under-load tap changers. Learning systems are employed to turn the voltage-control relays into adaptive devices. The scope of this study has been limited to the power distribution substation, and the voltage measurements and control actions are carried out on the secondary bus. The capacity of fuzzy systems to handle approximate data, together with their unique ability to interpret qualitative information, make it possible to design voltage-control strategies that satisfy the requirements of the Brazilian regulatory bodies and the real concerns of the electric power distribution companies. Fuzzy control systems based on these two strategies have been implemented and the test results were highly satisfactory.

Fuzzy Control System for Voltage Regulation In Power Transformers

A fuzzy control strategy for voltage regulation in electric power distribution systems is introduced in this article. This real-time controller would act on power transformers equipped with under-load tap changers. The fuzzy system was employed to turn the voltage-control relays into adaptive devices. The scope of the present study has been limited to the power distribution substation, and both the voltage measurements and control actions are carried out on the secondary bus. The capacity of fuzzy systems to handle approximate data, together with their unique ability to interpret qualitative information, make it possible to design voltage control strategies that satisfy both the requirements of the Brazilian regulatory bodies and the real concerns of the electric power distribution companies. A prototype based on the fuzzy control strategy proposed in this paper has also been implemented for validation purposes and its experimental results were highly satisfactory.

Automatic tuning method for the design of supplementary damping controllers for flexible alternating current transmission system devices

The design of supplementary damping controllers to mitigate the effects of electromechanical oscillations in power systems is a highly complex and time-consuming process, which requires a significant amount of knowledge from the part of the designer. In this study, the authors propose an automatic technique that takes the burden of tuning the controller parameters away from the power engineer and places it on the computer. Unlike other approaches that do the same based on robust control theories or evolutionary computing techniques, our proposed procedure uses an optimisation algorithm that works over a formulation of the classical tuning problem in terms of bilinear matrix inequalities. Using this formulation, it is possible to apply linear matrix inequality solvers to find a solution to the tuning problem via an iterative process, with the advantage that these solvers are widely available and have well-known convergence properties. The proposed algorithm is applied to tune the parameters of supplementary controllers for thyristor controlled series capacitors placed in the New England/New York benchmark test system, aiming at the improvement of the damping factor of inter-area modes, under several different operating conditions. The results of the linear analysis are validated by non-linear simulation and demonstrate the effectiveness of the proposed procedure.