Differential amplifier with improved gain-accuracy and linearity

A novel circuit design technique is presented which improves gain-accuracy and linearity in differential amplifiers. The technique employs negative impedance compensation and results demonstrate a significant performance improvement in precision, lowering sensitivity, and wide dynamic range. A theoretical underpinning is given together with the results of a demonstrator differential input/output amplifier with gain of 12 dB. The simulation results show that, with the novel method, both the gain-accuracy and linearity can be improved greatly. Especially, the linearity improvement in IMD can get to more than 23 dB with a required gain.

Design of differential amplifier with negative impedance compensation

Design of differential amplifier with high gain accuracy and high linearity is presented in the paper. The amplifier design is based on the negative impedance compensation technique reported by the authors in [1]. A negative impedance with high precision, low sensitivity, wide input signal range and simple structure is used for the compensation of differential amplifier. Analysis and simulation results show that gain accuracy and linearity can be improved significantly with the negative impedance compensation

Stability analysis of the amplifier with negative impedance compensation

A novel amplifier design technique based on negative impedance compensation has been proposed in our recent paper. In this paper, we investigate the stability of this amplifier system. The parameter space approach has been used to determine system parameters in the negative impedance circuit such that the stability of the amplifier system can be guaranteed in a certain region represented by those parameters. The simulation results have demonstrated that stable circuit behavior for the amplifier can be achieved

Idealised operation of zero-voltage-switching series-L/parallel-tuned Class-E power amplifier

An analysis of a modified series-L/parallel-tuned Class-E power amplifier is presented, which includes the effects that a shunt capacitance placed across the switching device will have on Class-E behaviour. In the original series L/parallel-tuned topology in which the output transistor capacitance is not inherently included in the circuit, zero-current switching (ZCS) and zero-current derivative switching (ZCDS) conditions should be applied to obtain optimum Class-E operation. On the other hand, when the output transistor capacitance is incorporated in the circuit, i.e. in the modified series-L/parallel-tuned topology, the ZCS and ZCDS would not give optimum operation and therefore zero-voltage-switching (ZVS) and zero-voltage-derivative switching (ZVDS) conditions should be applied instead. In the modified series-L/parallel-tuned Class-E configuration, the output-device inductance and the output-device output capacitance, both of which can significantly affect the amplifier's performance at microwave frequencies, furnish part, if not all, of the series inductance L and the shunt capacitance COUT, respectively. Further, when compared with the classic shunt-C/series-tuned topology, the proposed Class-E configuration offers some advantages in terms of 44% higher maximum operating frequency (fMAX) and 4% higher power-output capability (PMAX). As in the classic topology, the fMAX of the proposed amplifier circuit is reached when the output-device output capacitance furnishes all of the capacitance COUT, for a given combination of frequency, output power and DC supply voltage. It is also shown that numerical simulations agree well with theoretical predictions.

Inverse Class E amplifier and oscillator phase noise characteristics

This paper gives the first experimental characterisation of the phase noise response of the recently introduced Inverse Class E topology when operated as an amplifier and then as an oscillator. The results indicate that in amplifier and oscillator modes of operation conversion efficiencies of 64%, and 42% respectively are available, and that the excess PM noise added as a consequence of saturated Class E operation results in about a 10 dB increase in PM over that expected from a small-signal Class A amplifier operating at much lower efficiency. Inverse Class E phase transfer dependence on device drain bias and flicker noise are presented in order to show, respectively, that the Inverse Class E amplifier and oscillator follow the trends predicted by conventional phase noise theory. © 2007 EuMA.

Balanced class e amplifier based multimode modulator

In this paper we present an adaptation to the classical I/Q modulator topology which simultaneously allows it to operate both as a multi-modulation standard modulator, and as a high efficiency balanced amplifier. This is made possible by concurrently exploiting the ability of the Class E amplifiers to produce variable output power at maximum power added efficiency, PAE, by simple dc bias control while faithfully reproducing phase encoded signals. Experimental evidence for the behaviour of the modulator when operated in QPSK mode at 2.33 GHz with a 1 Msymbol/s rate shows that Error Vector Magnitude of less than 5% with amplifier PAE of 65% is possible. The multimode modulator presented here should lead to significantly reduced complexity, enhanced functionality transceivers for use in dc power sensitive handheld wireless applications. © 2007 EuMA.

Design strategies for dual-band class-e power amplifier using composite right/left-handed transmission lines

In this article we propose a technique for dual-band Class-E power amplifier design using composite right/left-handed transmission lines, CRLH TLs. Design equations are presented and design procedures are elaborated. Because of the nonlinear phase dispersion characteristic of CRLH TLs, the single previous attempt at applying this method to dual bond Class-E amplifier design was not sufficient to simultaneously satisfy, the minimum requirement of Class-E impedances at both the fundamental and the second harmonic frequencies. This article rectifies this situation. A design example illustrating the synthesis procedure for a 0.5W-5V dual band Class-E amplifier circuit simultaneously operated at 900 MHz and 2.4 GHz is given and compared with ADS simulation.

Inverse Class-E Amplifier With Transmission-Line Harmonic Suppression

This paper reports on the design methodology and experimental characterization of the inverse Class-E power amplifier. A demonstration amplifier with excellent second and third harmonic-suppression levels has been designed, constructed, and measured. The circuit fabricated using a 1.2-min gate-width GaAs MESFET is shown to be able to deliver 22-dBm output power at 2.3 GHz. The amplifier achieves a peak power-added efficiency of 64 % and drain efficiency of 69 %, and exhibits 11.6 dB power gain when operated from a 3-V supply voltage. Comparisons of simulated and measured results are given with good agreement between them being obtained. Experimental results are presented for the amplifier's response to Gaussian minimum shift keying modulation, where a peak error vector modulation value of 0.6% is measured.

2.4 GHz Class-E power amplifier with transmissionline harmonic terminations

The design procedure, fabrication and measurement of a Class-E power amplifier with excellent second- and third-harmonic suppression levels are presented. A simplified design technique offering compact physical layout is proposed. With a 1.2 mm gate-width GaAs MESFET as a switching device, the amplifier is capable of delivering 19.2 dBm output power at 2.41 GHz, achieves peak PAE of 60% and drain efficiency of 69%, and exhibits 9 dB power gain when operated from a 3 V DC supply voltage. When compared to the classical Class-E two-harmonic termination amplifier, the Class-E amplifier employing three-harmonic terminations has more than 10% higher drain efficiency and 23 dB better third-harmonic suppression level. Experimental results are presented and good agreement with simulation is obtained. Further, to verify the practical implementation in communication systems, the Bluetooth-standard GFSK modulated signal is applied to both two- and three-harmonic amplifiers. The measured RMS FSK deviation error and RMS magnitude error were, for the three-harmonic case, 1.01 kHz and 0.122%, respectively, and, for the two-harmonic case, 1.09 kHz and 0.133%. © 2007 The Institution of Engineering and Technology.

Sensitivity characteristics of inverse Class-E power amplifier

In this paper, an analysis is performed in order to determine the effects that variations in circuit component values, frequency, and duty cycle have on the performance of the newly introduced inverse Class-E amplifier. Analysis of the inverse Class-E amplifier under the generalized condition of arbitrary duty cycle is performed and it is shown that the inverse Class-E amplifier is reasonably tolerant to circuit parameter variations. When compared to the conventional Class-E amplifier the inverse Class-E amplifier offers the potential for high efficiency at increased output power as well as higher peak output power levels than are available with a conventional Class-E amplifier. Further the inverse Class-E amplifier provides more flexibility for deployment with a pulsewidth modulator as the means of producing full-carrier amplitude modulation (AM) due to its ability to operate to high AM modulation indices.

Series-L/parallel-tuned comparison with shunt-C/series-tuned class-E power amplifier

An analysis of the operation of a series-L/parallel-tuned class-E amplifier and its equivalence to the classic shunt-C/series-tuned class-E amplifier are presented. The first reported closed form design equations for the series-L/parallel-tuned topology operating under ideal switching conditions are given. Furthermore, a design procedure is introduced that allows the effect that nonzero switch resistance has on amplifier performance efficiency to be accounted for. The technique developed allows optimal circuit components to be found for a given device series resistance. For a relatively high value of switching device ON series resistance of 4O, drain efficiency of around 66% for the series-L/parallel-tuned topology, and 73% for the shunt-C/series-tuned topology appear to be the theoretical limits. At lower switching device series resistance levels, the efficiency performance of each type are similar, but the series-L/parallel-tuned topology offers some advantages in terms of its potential for MMIC realisation. Theoretical analysis is confirmed by numerical simulation for a 500mW (27dBm), 10% bandwidth, 5 V series-L/parallel-tuned, then, shunt-C/series-tuned class E power amplifier, operating at 2.5 GHz, and excellent agreement between theory and simulation results is achieved. The theoretical work presented in the paper should facilitate the design of high-efficiency switched amplifiers at frequencies commensurate with the needs of modern mobile wireless applications in the microwave frequency range, where intrinsically low-output-capacitance MMIC switching devices such as pHEMTs are to be used.

Envelope-tracking-based Doherty power amplifier

From the instantaneous efficiency plot, it is observed that the conventional 2-stage Doherty power amplifier (DPA) with high upper power dynamic range (>12 dB) suffers from a substantial dip in the middle of the upper power regime, thus reducing the average efficiency. In this study, an envelope-tracking-based DPA is proposed in order to minimise this dip by adjusting the drain bias voltage of the auxiliary amplifier of the DPA proportional to the input power level.