185 resultados para solder


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Purpose: Computer vision has been widely used in the inspection of electronic components. This paper proposes a computer vision system for the automatic detection, localisation, and segmentation of solder joints on Printed Circuit Boards (PCBs) under different illumination conditions. Design/methodology/approach: An illumination normalization approach is applied to an image, which can effectively and efficiently eliminate the effect of uneven illumination while keeping the properties of the processed image the same as in the corresponding image under normal lighting conditions. Consequently special lighting and instrumental setup can be reduced in order to detect solder joints. These normalised images are insensitive to illumination variations and are used for the subsequent solder joint detection stages. In the segmentation approach, the PCB image is transformed from an RGB color space to a YIQ color space for the effective detection of solder joints from the background. Findings: The segmentation results show that the proposed approach improves the performance significantly for images under varying illumination conditions. Research limitations/implications: This paper proposes a front-end system for the automatic detection, localisation, and segmentation of solder joint defects. Further research is required to complete the full system including the classification of solder joint defects. Practical implications: The methodology presented in this paper can be an effective method to reduce cost and improve quality in production of PCBs in the manufacturing industry. Originality/value: This research proposes the automatic location, identification and segmentation of solder joints under different illumination conditions.

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This paper proposes the validity of a Gabor filter bank for feature extraction of solder joint images on Printed Circuit Boards (PCBs). A distance measure based on the Mahalanobis Cosine metric is also presented for classification of five different types of solder joints. From the experimental results, this methodology achieved high accuracy and a well generalised performance. This can be an effective method to reduce cost and improve quality in the production of PCBs in the manufacturing industry.

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Inspection of solder joints has been a critical process in the electronic manufacturing industry to reduce manufacturing cost, improve yield, and ensure product quality and reliability. The solder joint inspection problem is more challenging than many other visual inspections because of the variability in the appearance of solder joints. Although many research works and various techniques have been developed to classify defect in solder joints, these methods have complex systems of illumination for image acquisition and complicated classification algorithms. An important stage of the analysis is to select the right method for the classification. Better inspection technologies are needed to fill the gap between available inspection capabilities and industry systems. This dissertation aims to provide a solution that can overcome some of the limitations of current inspection techniques. This research proposes two inspection steps for automatic solder joint classification system. The “front-end” inspection system includes illumination normalisation, localization and segmentation. The illumination normalisation approach can effectively and efficiently eliminate the effect of uneven illumination while keeping the properties of the processed image. The “back-end” inspection involves the classification of solder joints by using Log Gabor filter and classifier fusion. Five different levels of solder quality with respect to the amount of solder paste have been defined. Log Gabor filter has been demonstrated to achieve high recognition rates and is resistant to misalignment. Further testing demonstrates the advantage of Log Gabor filter over both Discrete Wavelet Transform and Discrete Cosine Transform. Classifier score fusion is analysed for improving recognition rate. Experimental results demonstrate that the proposed system improves performance and robustness in terms of classification rates. This proposed system does not need any special illumination system, and the images are acquired by an ordinary digital camera. In fact, the choice of suitable features allows one to overcome the problem given by the use of non complex illumination systems. The new system proposed in this research can be incorporated in the development of an automated non-contact, non-destructive and low cost solder joint quality inspection system.

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Inspection of solder joints has been a critical process in the electronic manufacturing industry to reduce manufacturing cost, improve yield, and ensure project quality and reliability. This paper proposes the use of the Log-Gabor filter bank, Discrete Wavelet Transform and Discrete Cosine Transform for feature extraction of solder joint images on Printed Circuit Boards (PCBs). A distance based on the Mahalanobis Cosine metric is also presented for classification of five different types of solder joints. From the experimental results, this methodology achieved high accuracy and a well generalised performance. This can be an effective method to reduce cost and improve quality in the production of PCBs in the manufacturing industry.

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A nonlinear finite element analysis was carried out to investigate the viscoplastic deformation of solder joints in a ball grid array (BGA) package under temperature cycle. The effects of constraint on print circuit board (PCB) and stiffness of substrate on the deformation behaviour of the solder joints were also studied. A relative damage stress was adopted to analyze the potential failure sites in the solder joints. The results indicated that high inelastic strain and strain energy density were developed in the joints close to the package center. On the other hand, high constraint and high relative damage stress were associated with the joint closest to the edge of the silicon chip. The joint closest to the edge of the silicon chip was regarded as the most susceptible failure site if cavitation instability is the dominant failure mechanism. Increase the external constraint on the print circuit board (PCB) causes a slight increase in stress triaxiality (m/eq) and relative damage stress in the joint closest to the edge of silicon die. The relative damage stress is not sensitive to the Young’s modulus of the substrate.

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The drive to replace lead (Pb) from electronics has led to the replacement of tin (Sn) alloys as the terminal plating for electronic devices. However, the deposition of Sn based alloys as the component surface finish tends to induce Sn whisker that causes unintended electric shorts when the conductive whiskers grow across to the adjacent conductor. Internal stress is considered as the driving force that causes the growth of Sn whiskers. In this study, stress type of elevated temperature/ humidity exposure at 55C/85%RH with the storage for up to 24 months was conducted to define the acceleration factor in samples with deposition of immersion Sn plating and Sn solder dipping. The addition of Nickel (Ni) under-layer was also applied to examine the correlation to field conditions. The results showed that the whisker length increased in high humidity irrespective of the deposition methods. It was also shown that pure Sn solder dipping mitigated the whisker growth but does not completely prevent it when alloying Sn with 0.4%wtCu. Additionally, Ni under-layer was indicated to be more efficient in mitigating the growth of whisker by prolonging the incubation time for whisker formation.

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Othman et al. (Intermetallics 2012;22:1-6) recently published a manuscript on ``Effects of current density on the formation and microstructure of Sn-9Zn, Sn-8Zn-3Bi and Sn-3Ag-0.5Cu solder joints''. We found problems in calculation of diffusion parameters. Even the comment on the formation of Cu5Zn8 instead of Cu6Sn5 is not correct. In this comment, we have explained the correct procedure to calculate the diffusion coefficients. Further, we have also explained the reason for the formation of Cu5Zn8 instead of Cu6Sn5 in the Cu/Sn-9Zn system. (C) 2012 Elsevier Ltd. All rights reserved.

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The effect of different pre-aging treatments on the microstructural evolution of lead-free solder and growth of interfacial intermetallic compound layers under thermal cycling has been investigated in this work. The results show that there are distinct differences in the microstructural changes between samples with no pretreatment, samples that have experienced thermal annealing at 125A degrees C for 750 h before thermal cycling, and those that have had direct current (DC) stressing for 750 h as pretreatment. The microstructural evolution of the solder matrix is rationalized by utilizing the science of microstructures and analysis of the influence of electron flow on the precipitation phenomena. The finite-element method is utilized to understand the loading conditions imposed on the solder interconnections during cyclic stressing. The growth of intermetallic reaction layers is further analyzed by utilizing quantitative thermodynamic calculations coupled with kinetic analysis. The latter is based on the changes in the intrinsic diffusion fluxes of elements induced by current flow and alloying elements present in the system. With this concurrent approach the differences seen in thermal cycling behavior between the different pre-aging treatments can be explained.

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Sn-Ag-Cu (SAC) solders are susceptible to appreciable microstructural coarsening during storage or service. This results in evolution of joint properties over time and thereby influences the long-term reliability of microelectronic packages. Accurate reliability prediction of SAC solders requires prediction of microstructural evolution during service. Microstructure evolution in two SAC solder alloys, such as, Sn-3.0Ag-0.5Cu (SAC 305) and Sn-1.0Ag-0.5 Cu (SAC 105), under different thermomechanical excursions, including isothermal aging at 150 degrees C and thermomechanical cycling (TMC) was studied. In general, between 200 and 600 cycles during TMC, recrystallization of the Sn matrix was observed, along with redistribution of Ag3Sn particles because of dissolution and reprecipitation. These latter effects have not been reported before. It was also observed that the Sn grains recrystallized near precipitate clusters in eutectic channels during extended isothermal aging. The relative orientation of Sn grains in proeutectic colonies did not change during isothermal aging.

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A fracture mechanism map (FMM) is a powerful tool which correlates the fracture behavior of a material to its microstructural characteristics in an explicit and convenient way. In the FMM for solder joints, an effective thickness of the interfacial intermetallic compound (IMC) layer (t (eff)) and the solder yield strength (sigma (ys,eff)) are used as abscissa and ordinate axes, respectively, as these two predominantly affect the fracture behavior of solder joints. Earlier, a definition of t (eff), based on the uniform thickness of IMC (t (u)) and the average height of the IMC scallops (t (s)), was proposed and shown to aptly explain the fracture behavior of solder joints on Cu. This paper presents a more general definition of t (eff) that is more widely applicable to a range of metallizations, including Cu and electroless nickel immersion gold (ENIG). Using this new definition of t (eff), mode I FMM for SAC387/Cu joints has been updated and its validity was confirmed. A preliminary FMM for SAC387/Cu joints with ENIG metallization is also presented.

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Solder joints in electronic packages undergo thermo-mechanical cycling, resulting in nucleation of micro-cracks, especially at the solder/bond-pad interface, which may lead to fracture of the joints. The fracture toughness of a solder joint depends on material properties, process conditions and service history, as well as strain rate and mode-mixity. This paper reports on a methodology for determining the mixed-mode fracture toughness of solder joints with an interfacial starter-crack, using a modified compact mixed mode (CMM) specimen containing an adhesive joint. Expressions for stress intensity factor (K) and strain energy release rate (G) are developed, using a combination of experiments and finite element (FE) analysis. In this methodology, crack length dependent geometry factors to convert for the modified CMM sample are first obtained via the crack-tip opening displacement (CTOD)-based linear extrapolation method to calculate the under far-field mode I and II conditions (f(1a) and f(2a)), (ii) generation of a master-plot to determine a(c), and (iii) computation of K and G to analyze the fracture behavior of joints. The developed methodology was verified using J-integral calculations, and was also used to calculate experimental fracture toughness values of a few lead-free solder-Cu joints. (C) 2014 Elsevier Ltd. All rights reserved.

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The effect of thermal-mechanical loading on a surface mount assembly with interface cracks between the solder and the resistor and between the solder and the printed circuit board (PCB) was studied using a non-linear thermal finite element analysis. The thermal effect was taken as cooling from the solder eutectic temperature to room temperature. Mechanical loading at the ends of the PCB was also applied. The results showed that cooling had the effect of causing large residual shear displacement at the region near the interface cracks. The mechanical loading caused additional crack opening displacements. The analysis on the values of J-integral for the interface cracks showed that J-integral was approximately path independent, and that the effect of crack at the solder/PCB interface is much more serious than that between the component and solder.

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The objective of this paper is to investigate the effect of the pad size ratio between the chip and board end of a solder joint on the shape of that solder joint in combination with the solder volume available. The shape of the solder joint is correlated to its reliability and thus of importance. For low density chip bond pad applications Flip Chip (FC) manufacturing costs can be kept down by using larger size board pads suitable for solder application. By using “Surface Evolver” software package the solder joint shapes associated with different size/shape solder preforms and chip/board pad ratios are predicted. In this case a so called Flip-Chip Over Hole (FCOH) assembly format has been used. Assembly trials involved the deposition of lead-free 99.3Sn0.7Cu solder on the board side, followed by reflow, an underfill process and back die encapsulation. During the assembly work pad off-sets occurred that have been taken into account for the Surface Evolver solder joint shape prediction and accurately matched the real assembly. Overall, good correlation was found between the simulated solder joint shape and the actual fabricated solder joint shapes. Solder preforms were found to exhibit better control over the solder volume. Reflow simulation of commercially available solder preform volumes suggests that for a fixed stand-off height and chip-board pad ratio, the solder volume value and the surface tension determines the shape of the joint.

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Solder materials are used to provide a connection between electronic components and printed circuit boards (PCBs) using either the reflow or wave soldering process. As a board assembly passes through a reflow furnace the solder (initially in the form of solder paste) melts, reflows, then solidifies, and finally deforms between the chip and board. A number of defects may occur during this process such as flux entrapment, void formation, and cracking of the joint, chip or board. These defects are a serious concern to industry, especially with trends towards increasing component miniaturisation and smaller pitch sizes. This paper presents a modelling methodology for predicting solder joint shape, solidification, and deformation (stress) during the assembly process.

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A computational model of solder joint formation and the subsequent cooling behaviour is described. Given the rapid changes in the technology of printed circuit boards, there is a requirement for comprehensive models of solder joint formation which permit detailed analysis of design and optimization options. Solder joint formation is complex, involving a range of interacting phenomena. This paper describes a model implementation (as part of a more comprehensive framework) to describe the shape formation (conditioned by surface tension), heat transfer, phase change and the development of elastoviscoplastic stress. The computational modelling framework is based upon mixed finite element and finite volume procedures, and has unstructured meshes enabling arbitrarily complex geometries to be analysed. Initial results for both through-hole and surface-mount geometries are presented.