Crossing genetic and swarm intelligence algorithms to generate logic circuits

Genetic Algorithms (GAs) are adaptive heuristic search algorithm based on the evolutionary ideas of natural selection and genetic. The basic concept of GAs is designed to simulate processes in natural system necessary for evolution, specifically those that follow the principles first laid down by Charles Darwin of survival of the fittest. On the other hand, Particle swarm optimization (PSO) is a population based stochastic optimization technique inspired by social behavior of bird flocking or fish schooling. PSO shares many similarities with evolutionary computation techniques such as GAs. The system is initialized with a population of random solutions and searches for optima by updating generations. However, unlike GA, PSO has no evolution operators such as crossover and mutation. In PSO, the potential solutions, called particles, fly through the problem space by following the current optimum particles. PSO is attractive because there are few parameters to adjust. This paper presents hybridization between a GA algorithm and a PSO algorithm (crossing the two algorithms). The resulting algorithm is applied to the synthesis of combinational logic circuits. With this combination is possible to take advantage of the best features of each particular algorithm.

Bounding of switching activity in logic circuits

Thèse diffusée initialement dans le cadre d'un projet pilote des Presses de l'Université de Montréal/Centre d'édition numérique UdeM (1997-2008) avec l'autorisation de l'auteur.

A Fractional Calculus Perspective in the Evolutionary Design of Combinational Circuits

This paper analyses the performance of a genetic algorithm (GA) in the synthesis of digital circuits using two novel approaches. The first concept consists in improving the static fitness function by including a discontinuity evaluation. The measure of variability in the error of the Boolean table has similarities with the function continuity issue in classical calculus. The second concept extends the static fitness by introducing a fractional-order dynamical evaluation.

New Concepts Towards the Synthesis of Digital Circuits Through Genetic Algorithms

This paper analyses the performance of a Genetic Algorithm using two new concepts, namely a static fitness function including a discontinuity measure and a fractional-order dynamic fitness function, for the synthesis of combinational logic circuits. In both cases, experiments reveal superior results in terms of speed and convergence to achieve a solution.

Optimal networks with NOR-OR gates and Wired OR logic /

Originally presented as the author's thesis (M.S.), University of Illinois at Urbana-Champaign.

A manual of SIMPL, a logic network simulator for PLATO /

"UILU-ENG 79 1728."

Synthesis of logic networks with MOS complex cells.

Vita.

Data structures for SIMD logic simulation

Due to the growth of design size and complexity, design verification is an important aspect of the Logic Circuit development process. The purpose of verification is to validate that the design meets the system requirements and specification. This is done by either functional or formal verification. The most popular approach to functional verification is the use of simulation based techniques. Using models to replicate the behaviour of an actual system is called simulation. In this thesis, a software/data structure architecture without explicit locks is proposed to accelerate logic gate circuit simulation. We call thus system ZSIM. The ZSIM software architecture simulator targets low cost SIMD multi-core machines. Its performance is evaluated on the Intel Xeon Phi and 2 other machines (Intel Xeon and AMD Opteron). The aim of these experiments is to: • Verify that the data structure used allows SIMD acceleration, particularly on machines with gather instructions ( section 5.3.1). • Verify that, on sufficiently large circuits, substantial gains could be made from multicore parallelism ( section 5.3.2 ). • Show that a simulator using this approach out-performs an existing commercial simulator on a standard workstation ( section 5.3.3 ). • Show that the performance on a cheap Xeon Phi card is competitive with results reported elsewhere on much more expensive super-computers ( section 5.3.5 ). To evaluate the ZSIM, two types of test circuits were used: 1. Circuits from the IWLS benchmark suit [1] which allow direct comparison with other published studies of parallel simulators.2. Circuits generated by a parametrised circuit synthesizer. The synthesizer used an algorithm that has been shown to generate circuits that are statistically representative of real logic circuits. The synthesizer allowed testing of a range of very large circuits, larger than the ones for which it was possible to obtain open source files. The experimental results show that with SIMD acceleration and multicore, ZSIM gained a peak parallelisation factor of 300 on Intel Xeon Phi and 11 on Intel Xeon. With only SIMD enabled, ZSIM achieved a maximum parallelistion gain of 10 on Intel Xeon Phi and 4 on Intel Xeon. Furthermore, it was shown that this software architecture simulator running on a SIMD machine is much faster than, and can handle much bigger circuits than a widely used commercial simulator (Xilinx) running on a workstation. The performance achieved by ZSIM was also compared with similar pre-existing work on logic simulation targeting GPUs and supercomputers. It was shown that ZSIM simulator running on a Xeon Phi machine gives comparable simulation performance to the IBM Blue Gene supercomputer at very much lower cost. The experimental results have shown that the Xeon Phi is competitive with simulation on GPUs and allows the handling of much larger circuits than have been reported for GPU simulation. When targeting Xeon Phi architecture, the automatic cache management of the Xeon Phi, handles and manages the on-chip local store without any explicit mention of the local store being made in the architecture of the simulator itself. However, targeting GPUs, explicit cache management in program increases the complexity of the software architecture. Furthermore, one of the strongest points of the ZSIM simulator is its portability. Note that the same code was tested on both AMD and Xeon Phi machines. The same architecture that efficiently performs on Xeon Phi, was ported into a 64 core NUMA AMD Opteron. To conclude, the two main achievements are restated as following: The primary achievement of this work was proving that the ZSIM architecture was faster than previously published logic simulators on low cost platforms. The secondary achievement was the development of a synthetic testing suite that went beyond the scale range that was previously publicly available, based on prior work that showed the synthesis technique is valid.

Sistema de multiprocessamento para simulação de N-corpos em FPGA

Trabalho Final de Mestrado para obtenção do grau de Mestre em Engenharia de Electrónica e Telecomunicações

Fitness function evaluation through fractional algorithms

This paper proposes a Genetic Algorithm (GA) for the design of combinational logic circuits. The fitness function evaluation is calculated using Fractional Calculus. This approach extends the classical fitness function by including a fractional-order dynamical evaluation. The experiments reveal superior results when comparing with the classical method.

Modeling and manufacturability assessment of bistable quantum-dot cells

We have investigated the behavior of bistable cells made up of four quantum dots and occupied by two electrons, in the presence of realistic confinement potentials produced by depletion gates on top of a GaAs/AlGaAs heterostructure. Such a cell represents the basic building block for logic architectures based on the concept of quantum cellular automata (QCA) and of ground state computation, which have been proposed as an alternative to traditional transistor-based logic circuits. We have focused on the robustness of the operation of such cells with respect to asymmetries derived from fabrication tolerances. We have developed a two-dimensional model for the calculation of the electron density in a driven cell in response to the polarization state of a driver cell. Our method is based on the one-shot configuration-interaction technique, adapted from molecular chemistry. From the results of our simulations, we conclude that an implementation of QCA logic based on simple ¿hole arrays¿ is not feasible, because of the extreme sensitivity to fabrication tolerances. As an alternative, we propose cells defined by multiple gates, where geometrical asymmetries can be compensated for by adjusting the bias voltages. Even though not immediately applicable to the implementation of logic gates and not suitable for large scale integration, the proposed cell layout should allow an experimental demonstration of a chain of QCA cells.

Discrete wavelet transform signal analyzer

This paper addresses the problem of processing biological data, such as cardiac beats in the audio and ultrasonic range, and on calculating wavelet coefficients in real time, with the processor clock running at a frequency of present application-specified integrated circuits and field programmable gate array. The parallel filter architecture for discrete wavelet transform (DWT) has been improved, calculating the wavelet coefficients in real time with hardware reduced up to 60%. The new architecture, which also processes inverse DWT, is implemented with the Radix-2 or the Booth-Wallace constant multipliers. One integrated circuit signal analyzer in the ultrasonic range, including series memory register banks, is presented. © 2007 IEEE.

Hardware implementation of type-2 programmable fuzzifier

The design of full programmable type-2 membership function circuit is presented in this paper. This circuit is used to implement the fuzzifier block of Type-2 Fuzzy Logic Controller chip. In this paper the type-2 fuzzy set was obtained by blurring the width of the type-1 fuzzy set. This circuit allows programming the height and the shape of the membership function. It operates in current mode, with supply voltage of 3.3V. The simulation results of interval type-2 membership function circuit have been done in CMOS 0.35μm technology using Mentor Graphics software. © 2011 IEEE.

Tailoring, synthesis and structure-property relationships of 2,3-thienoimide based molecular materials

Organic molecular semiconductors are subject of intense research for their crucial role as key components of new generation low cost, flexible, and large area electronic devices such as displays, thin-film transistors, solar cells, sensors and logic circuits. In particular, small molecular thienoimide (TI) based materials are emerging as novel multifunctional materials combining a good processability together to ambipolar or n-type charge transport and electroluminescence at the solid state, thus enabling the fabrication of integrated devices like organic field effect transistors (OFETs) and light emitting transistor (OLETs). Given this peculiar combination of characteristics, they also constitute the ideal substrates for fundamental studies on the structure-property relationships in multifunctional molecular systems. In this scenario, this thesis work is focused on the synthesis of new thienoimide based materials with tunable optical, packing, morphology, charge transport and electroluminescence properties by following a fine molecular tailoring, thus optimizing their performances in device as well as investigating and enabling new applications. Investigation on their structure-property relationships has been carried out and in particular, the effect of different π-conjugated cores (heterocycles, length) and alkyl end chain (shape, length) changes have been studied, obtaining materials with enhanced electron transport capability end electroluminescence suitable for the realization of OFETs and single layer OLETs. Moreover, control on the polymorphic behaviour characterizing thienoimide materials has been reached by synthetic and post-synthetic methodologies, developing multifunctional materials from a single polymorphic compound. Finally, with the aim of synthesizing highly pure materials, simplifying the purification steps and avoiding organometallic residues, procedures based on direct arylation reactions replacing conventional cross-couplings have been investigated and applied to different classes of molecules, bearing thienoimidic core or ends, as well as thiophene and anthracene derivatives, validating this approach as a clean alternative for the synthesis of several molecular materials.

NOR network transduction procedures : "merging of gates" and "substitution of gates" for fan-in and fan-out restricted networks, NETTRA-G3-FIFO and NETTRA-PG1-FIFO /

"December 1974."--T.p.