COMUNICAÇÃO NO PONTO-DE-VENDA: ASPECTOS SENSORIAIS NA AMBIENTAÇÃO DAS MEGALIVRARIAS

Esta pesquisa tem como objetivo investigar e discutir a ambientação como elemento de comunicação aplicado ao ponto-de-venda livraria e observar e analisar como as atuais lojas se adaptaram a uma realidade de mercado, que visa envolver o cliente em uma experiência prazerosa, tendo em vista a concorrência do comércio virtual e a crescente venda de livros em supermercados. Pretende-se, neste trabalho, compreender a utilização dos diversos elementos sensoriais que envolvem: tato, olfato, paladar, visão e audição no ponto-de-venda físico. O objeto de estudo é a Livraria Cultura do Conjunto Nacional, sua relevância ocorre pelo fato da livraria ser a maior loja em metros quadrados do país. Por tratar-se de um fenômeno contemporâneo inserido no contexto da vida real, a metodologia utilizada é o Estudo de Caso Único e os procedimentos metodológicos são observação direta do consumidor no ponto-de-venda, pesquisa bibliográfica, entrevistas com freqüentadores da loja e com profissionais do setor. Pode-se concluir que as características hedônicas do consumidor contemporâneo que busca experiências prazerosas associada a sinergia da comunicação integrada de marketing favorecem para os resultados positivos apresentados pela livraria.(AU)

COMUNICAÇÃO NO PONTO-DE-VENDA: ASPECTOS SENSORIAIS NA AMBIENTAÇÃO DAS MEGALIVRARIAS

Esta pesquisa tem como objetivo investigar e discutir a ambientação como elemento de comunicação aplicado ao ponto-de-venda livraria e observar e analisar como as atuais lojas se adaptaram a uma realidade de mercado, que visa envolver o cliente em uma experiência prazerosa, tendo em vista a concorrência do comércio virtual e a crescente venda de livros em supermercados. Pretende-se, neste trabalho, compreender a utilização dos diversos elementos sensoriais que envolvem: tato, olfato, paladar, visão e audição no ponto-de-venda físico. O objeto de estudo é a Livraria Cultura do Conjunto Nacional, sua relevância ocorre pelo fato da livraria ser a maior loja em metros quadrados do país. Por tratar-se de um fenômeno contemporâneo inserido no contexto da vida real, a metodologia utilizada é o Estudo de Caso Único e os procedimentos metodológicos são observação direta do consumidor no ponto-de-venda, pesquisa bibliográfica, entrevistas com freqüentadores da loja e com profissionais do setor. Pode-se concluir que as características hedônicas do consumidor contemporâneo que busca experiências prazerosas associada a sinergia da comunicação integrada de marketing favorecem para os resultados positivos apresentados pela livraria.(AU)

COMUNICAÇÃO NO PONTO-DE-VENDA: ASPECTOS SENSORIAIS NA AMBIENTAÇÃO DAS MEGALIVRARIAS

Esta pesquisa tem como objetivo investigar e discutir a ambientação como elemento de comunicação aplicado ao ponto-de-venda livraria e observar e analisar como as atuais lojas se adaptaram a uma realidade de mercado, que visa envolver o cliente em uma experiência prazerosa, tendo em vista a concorrência do comércio virtual e a crescente venda de livros em supermercados. Pretende-se, neste trabalho, compreender a utilização dos diversos elementos sensoriais que envolvem: tato, olfato, paladar, visão e audição no ponto-de-venda físico. O objeto de estudo é a Livraria Cultura do Conjunto Nacional, sua relevância ocorre pelo fato da livraria ser a maior loja em metros quadrados do país. Por tratar-se de um fenômeno contemporâneo inserido no contexto da vida real, a metodologia utilizada é o Estudo de Caso Único e os procedimentos metodológicos são observação direta do consumidor no ponto-de-venda, pesquisa bibliográfica, entrevistas com freqüentadores da loja e com profissionais do setor. Pode-se concluir que as características hedônicas do consumidor contemporâneo que busca experiências prazerosas associada a sinergia da comunicação integrada de marketing favorecem para os resultados positivos apresentados pela livraria.(AU)

Application of the entropy technique and genetic algorithms to construction site layout planning of medium-size projects

Genetic algorithms (GAs) have been introduced into site layout planning as reported in a number of studies. In these studies, the objective functions were defined so as to employ the GAs in searching for the optimal site layout. However, few studies have been carried out to investigate the actual closeness of relationships between site facilities; it is these relationships that ultimately govern the site layout. This study has determined that the underlying factors of site layout planning for medium-size projects include work flow, personnel flow, safety and environment, and personal preferences. By finding the weightings on these factors and the corresponding closeness indices between each facility, a closeness relationship has been deduced. Two contemporary mathematical approaches - fuzzy logic theory and an entropy measure - were adopted in finding these results in order to minimize the uncertainty and vagueness of the collected data and improve the quality of the information. GAs were then applied to searching for the optimal site layout in a medium-size government project using the GeneHunter software. The objective function involved minimizing the total travel distance. An optimal layout was obtained within a short time. This reveals that the application of GA to site layout planning is highly promising and efficient.

Addressing the facilities layout design problem through constraint logic programming

One of the most difficult problems that face researchers experimenting with complex systems in real world applications is the Facility Layout Design Problem. It relies with the design and location of production lines, machinery and equipment, inventory storage and shipping facilities. In this work it is intended to address this problem through the use of Constraint Logic Programming (CLP) technology. The use of Genetic Algorithms (GA) as optimisation technique in CLP environment is also an issue addressed. The approach aims the implementation of genetic algorithm operators following the CLP paradigm.

Improvement of the quality factor of RF integrated inductors by layout optimization

A systematic method to improve the quality (Q) factor of RF integrated inductors is presented in this paper. The proposed method is based on the layout optimization to minimize the series resistance of the inductor coil, taking into account both ohmic losses, due to conduction currents, and magnetically induced losses, due to eddy currents. The technique is particularly useful when applied to inductors in which the fabrication process includes integration substrate removal. However, it is also applicable to inductors on low-loss substrates. The method optimizes the width of the metal strip for each turn of the inductor coil, leading to a variable strip-width layout. The optimization procedure has been successfully applied to the design of square spiral inductors in a silicon-based multichip-module technology, complemented with silicon micromachining postprocessing. The obtained experimental results corroborate the validity of the proposed method. A Q factor of about 17 have been obtained for a 35-nH inductor at 1.5 GHz, with Q values higher than 40 predicted for a 20-nH inductor working at 3.5 GHz. The latter is up to a 60% better than the best results for a single strip-width inductor working at the same frequency.

Via-configurable transistor array: a regular design technique to improve ICs yield

Process variations are a major bottleneck for digital CMOS integrated circuits manufacturability and yield. That iswhy regular techniques with different degrees of regularity are emerging as possible solutions. Our proposal is a new regular layout design technique called Via-Configurable Transistors Array (VCTA) that pushes to the limit circuit layout regularity for devices and interconnects in order to maximize regularity benefits. VCTA is predicted to perform worse than the Standard Cell approach designs for a certain technology node but it will allow the use of a future technology on an earlier time. Ourobjective is to optimize VCTA for it to be comparable to the Standard Cell design in an older technology. Simulations for the first unoptimized version of our VCTA of delay and energy consumption for a Full Adder circuit in the 90 nm technology node are presented and also the extrapolation for Carry-RippleAdders from 4 bits to 64 bits.

Disseny, layout i planificació d'una empresa de producció d'equips foraborda elèctrics

Aquest projecte es basa en l'aplicació de models de simulació de processos a un exemple d'empresa de producció i la seva adaptació en dimensió i recursos al mercat en un entorn de poca capacitat d'inversió i finançament, de forma que l'entorn de simulació digital aporti valor a la presa de decisions emmarcada en l'estratègia de l'empresa en cada escenari de mercat en que aquesta es trobi. Es realitza el treball sobre el cas d'una empresa, INNOVANAUTIC, dedicada a la innovació, desenvolupament i producció de sistemes de propulsió d'embarcacions. La simulació es una tècnica que permet optimitzar els processos, representant-ne i comprovant el funcionament dels processos, tant entorns físics, de producció com dels serveis associats o subcontractacions de diferents processos i els seus impactes en la disponibilitat de recursos, espais i terminis d'entrega, sense haver de recórrer a procediments de prova i error sobre sistemes reals que impliquen costos a tots nivells en l'empresa. Aquestes metodologies son habitualment emprades en d'altres països o també en el nostre país però en empreses de gran tamany. El present treball, emmarcat dins un entorn socioeconòmic convuls, amb grans limitacions financeres i de recursos per les empreses, demostra com la utilització d'eines de simulació és útil per a PIMES en aquest entorn i permet el dimensionament i la modelització dels processos de forma que es permeti trobar els punts òptims en els que l'empresa ha de donar un pas de creixement en alguns dels paràmetres. La metodologia amb que s'elabora el present treball es la de plantejar una simulació complerta del procés, i definir diversos escenaris de mercat per als productes fabricats, cercant els punt òptims de canvi de dimensió de l'empresa atenent a espai físic, sotscontractació de processos, personal i recursos.

PedVis: A Structured, Space-Efficient Technique for Pedigree Visualization

Public genealogical databases are becoming increasingly populated with historical data and records of the current population`s ancestors. As this increasing amount of available information is used to link individuals to their ancestors, the resulting trees become deeper and more dense, which justifies the need for using organized, space-efficient layouts to display the data. Existing layouts are often only able to show a small subset of the data at a time. As a result, it is easy to become lost when navigating through the data or to lose sight of the overall tree structure. On the contrary, leaving space for unknown ancestors allows one to better understand the tree`s structure, but leaving this space becomes expensive and allows fewer generations to be displayed at a time. In this work, we propose that the H-tree based layout be used in genealogical software to display ancestral trees. We will show that this layout presents an increase in the number of displayable generations, provides a nicely arranged, symmetrical, intuitive and organized fractal structure, increases the user`s ability to understand and navigate through the data, and accounts for the visualization requirements necessary for displaying such trees. Finally, user-study results indicate potential for user acceptance of the new layout.

Análise e melhoria de layout de processo na indústria de beneficiamento de couro

A aplicação de técnicas de estudo de sistemas em ambientes industriais com grande concorrência, é cada vez mais significativa devido às modificações e flexibilidade de produção exigidas. A aplicação de técnicas de análise e ajustes de layouts são algumas destas técnicas que podem trazer resultados competitivos positivos. O presente trabalho descreve os tipos de layouts existentes, com suas aplicações, vantagens e desvantagens com a finalidade de analisar e propor melhorias em layouts de processo na indústria coureira. O trabalho enfoca ainda os principais pontos a serem considerados quando da criação de um novo layout ou do ajuste e/ou melhoria de um existente. Para tal, foi realizado um estudo de caso utilizando a técnica de Melhoria de Layout de Silveira (1998), com a aplicação do Planejamento Sistemático de Layout em um layout de processo do setor da Secagem, característico em uma indústria beneficiadora de couro. Os resultados obtidos traduzem o re-arranjo de seus postos de trabalho com redução do fluxo de material de acordo com a aproximação de postos com relações de afinidade. Essa alteração possibilitou uma melhor organização espacial dos postos de trabalho e um melhor controle da produção, através da separação natural dos lotes. A metodologia adotada pode ser utilizada como ferramenta de melhoria nos demais setores, tanto da própria empresa, como do mercado coureiro em geral.

Automatic layout generation of static CMOS circuits targeting delay and power

The evolution of integrated circuits technologies demands the development of new CAD tools. The traditional development of digital circuits at physical level is based in library of cells. These libraries of cells offer certain predictability of the electrical behavior of the design due to the previous characterization of the cells. Besides, different versions of each cell are required in such a way that delay and power consumption characteristics are taken into account, increasing the number of cells in a library. The automatic full custom layout generation is an alternative each time more important to cell based generation approaches. This strategy implements transistors and connections according patterns defined by algorithms. So, it is possible to implement any logic function avoiding the limitations of the library of cells. Tools of analysis and estimate must offer the predictability in automatic full custom layouts. These tools must be able to work with layout estimates and to generate information related to delay, power consumption and area occupation. This work includes the research of new methods of physical synthesis and the implementation of an automatic layout generation in which the cells are generated at the moment of the layout synthesis. The research investigates different strategies of elements disposition (transistors, contacts and connections) in a layout and their effects in the area occupation and circuit delay. The presented layout strategy applies delay optimization by the integration with a gate sizing technique. This is performed in such a way the folding method allows individual discrete sizing to transistors. The main characteristics of the proposed strategy are: power supply lines between rows, over the layout routing (channel routing is not used), circuit routing performed before layout generation and layout generation targeting delay reduction by the application of the sizing technique. The possibility to implement any logic function, without restrictions imposed by a library of cells, allows the circuit synthesis with optimization in the number of the transistors. This reduction in the number of transistors decreases the delay and power consumption, mainly the static power consumption in submicrometer circuits. Comparisons between the proposed strategy and other well-known methods are presented in such a way the proposed method is validated.

Security through Obscurity: Layout Obfuscation of Digital Integrated Circuits using Don't Care Conditions

Contemporary integrated circuits are designed and manufactured in a globalized environment leading to concerns of piracy, overproduction and counterfeiting. One class of techniques to combat these threats is circuit obfuscation which seeks to modify the gate-level (or structural) description of a circuit without affecting its functionality in order to increase the complexity and cost of reverse engineering. Most of the existing circuit obfuscation methods are based on the insertion of additional logic (called “key gates”) or camouflaging existing gates in order to make it difficult for a malicious user to get the complete layout information without extensive computations to determine key-gate values. However, when the netlist or the circuit layout, although camouflaged, is available to the attacker, he/she can use advanced logic analysis and circuit simulation tools and Boolean SAT solvers to reveal the unknown gate-level information without exhaustively trying all the input vectors, thus bringing down the complexity of reverse engineering. To counter this problem, some ‘provably secure’ logic encryption algorithms that emphasize methodical selection of camouflaged gates have been proposed previously in literature [1,2,3]. The contribution of this paper is the creation and simulation of a new layout obfuscation method that uses don't care conditions. We also present proof-of-concept of a new functional or logic obfuscation technique that not only conceals, but modifies the circuit functionality in addition to the gate-level description, and can be implemented automatically during the design process. Our layout obfuscation technique utilizes don’t care conditions (namely, Observability and Satisfiability Don’t Cares) inherent in the circuit to camouflage selected gates and modify sub-circuit functionality while meeting the overall circuit specification. Here, camouflaging or obfuscating a gate means replacing the candidate gate by a 4X1 Multiplexer which can be configured to perform all possible 2-input/ 1-output functions as proposed by Bao et al. [4]. It is important to emphasize that our approach not only obfuscates but alters sub-circuit level functionality in an attempt to make IP piracy difficult. The choice of gates to obfuscate determines the effort required to reverse engineer or brute force the design. As such, we propose a method of camouflaged gate selection based on the intersection of output logic cones. By choosing these candidate gates methodically, the complexity of reverse engineering can be made exponential, thus making it computationally very expensive to determine the true circuit functionality. We propose several heuristic algorithms to maximize the RE complexity based on don’t care based obfuscation and methodical gate selection. Thus, the goal of protecting the design IP from malicious end-users is achieved. It also makes it significantly harder for rogue elements in the supply chain to use, copy or replicate the same design with a different logic. We analyze the reverse engineering complexity by applying our obfuscation algorithm on ISCAS-85 benchmarks. Our experimental results indicate that significant reverse engineering complexity can be achieved at minimal design overhead (average area overhead for the proposed layout obfuscation methods is 5.51% and average delay overhead is about 7.732%). We discuss the strengths and limitations of our approach and suggest directions that may lead to improved logic encryption algorithms in the future. References: [1] R. Chakraborty and S. Bhunia, “HARPOON: An Obfuscation-Based SoC Design Methodology for Hardware Protection,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 10, pp. 1493–1502, 2009. [2] J. A. Roy, F. Koushanfar, and I. L. Markov, “EPIC: Ending Piracy of Integrated Circuits,” in 2008 Design, Automation and Test in Europe, 2008, pp. 1069–1074. [3] J. Rajendran, M. Sam, O. Sinanoglu, and R. Karri, “Security Analysis of Integrated Circuit Camouflaging,” ACM Conference on Computer Communications and Security, 2013. [4] Bao Liu, Wang, B., "Embedded reconfigurable logic for ASIC design obfuscation against supply chain attacks,"Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014 , vol., no., pp.1,6, 24-28 March 2014.

Fracture Of Distal Humerus: Mipo Technique With Visualization Of The Radial Nerve.

To evaluate the outcomes in patients treated for humerus distal third fractures with MIPO technique and visualization of the radial nerve by an accessory approach, in those without radial palsy before surgery. The patients were treated with MIPO technique. The visualization and isolation of the radial nerve was done by an approach between the brachialis and the brachiorradialis, with an oblique incision, in the lateral side of the arm. MEPS was used to evaluate the elbow function. Seven patients were evaluated with a mean age of 29.8 years old. The average follow up was 29.85 months. The radial neuropraxis after surgery occurred in three patients. The sensorial recovery occurred after 3.16 months on average and also of the motor function, after 5.33 months on average, in all patients. We achieved fracture consolidation in all patients (M=4.22 months). The averages for flexion-extension and prono-supination were 112.85° and 145°, respectively. The MEPS average score was 86.42. There was no case of infection. This approach allowed excluding a radial nerve interposition on site of the fracture and/or under the plate, showing a high level of consolidation of the fracture and a good evolution of the range of movement of the elbow. Level of Evidence IV, Case Series.

In Vitro Effects Of Hydrogen Peroxide Combined With Different Activators For The In-office Bleaching Technique On Enamel.

Abstract Objective. The aim of this study was to evaluate the alteration of human enamel bleached with high concentrations of hydrogen peroxide associated with different activators. Materials and methods. Fifty enamel/dentin blocks (4 × 4 mm) were obtained from human third molars and randomized divided according to the bleaching procedure (n = 10): G1 = 35% hydrogen peroxide (HP - Whiteness HP Maxx); G2 = HP + Halogen lamp (HL); G3 = HP + 7% sodium bicarbonate (SB); G4 = HP + 20% sodium hydroxide (SH); and G5 = 38% hydrogen peroxide (OXB - Opalescence Xtra Boost). The bleaching treatments were performed in three sessions with a 7-day interval between them. The enamel content, before (baseline) and after bleaching, was determined using an FT-Raman spectrometer and was based on the concentration of phosphate, carbonate, and organic matrix. Statistical analysis was performed using two-way ANOVA for repeated measures and Tukey's test. Results. The results showed no significant differences between time of analysis (p = 0.5175) for most treatments and peak areas analyzed; and among bleaching treatments (p = 0.4184). The comparisons during and after bleaching revealed a significant difference in the HP group for the peak areas of carbonate and organic matrix, and for the organic matrix in OXB and HP+SH groups. Tukey's analysis determined that the difference, peak areas, and the interaction among treatment, time and peak was statistically significant (p < 0.05). Conclusion. The association of activators with hydrogen peroxide was effective in the alteration of enamel, mainly with regards to the organic matrix.

Preservation Of The External Jugular Vein In Bilateral Radical Neck Dissections: Technique In Two Cases And Review Of The Literature.

Context. The possibility of cephalic venous hypertension with the resultant facial edema and elevated cerebrospinal fluid pressure continues to challenge head and neck surgeons who perform bilateral radical neck dissections during simultaneous or staged procedures. Case Report. The staged procedure in patients who require bilateral neck dissections allows collateral venous drainage to develop, mainly through the internal and external vertebral plexuses, thereby minimizing the risks of deleterious consequences. Nevertheless, this procedure has disadvantages, such as a delay in definitive therapy, the need for a second hospitalization and anesthesia, and the risk of cutting lymphatic vessels and spreading viable cancer cells. In this paper, we discuss the rationale and feasibility of preserving the external jugular vein. Considering the limited number of similar reports in the literature, two cases in which this procedure was accomplished are described. The relevant anatomy and technique are reviewed and the patients' outcomes are discussed. Conclusion. Preservation of the EJV during bilateral neck dissections is technically feasible, fast, and safe, with clinically and radiologically demonstrated patency.