A study of the effects metal residues in poly(9,9-dioctylfluorene) have on field-effect transistor device characteristics

The amount of metal residues from organometallic reagents used in preparation of poly(9,9-dioctylfluorene) by palladium catalysed Suzuki and nickel-induced Yamamoto polycondensations have been determined, and their effect upon the behaviour of the polymer in field-effect transistors (FETs) has been measured. The metal levels from material polymerised by Suzuki method were found to be much higher than from that made by the Yamamoto procedure. Simple treatment of the polymers with suitable metal trapping reagents lowered the metal levels significantly, with EDTA giving best results for nickel and triphenylphosphine for palladium. Comparison of the behaviour of FETs using polyfluorenes with varying levels of metal contamination, showed that the metal residues have little effect upon the mobility values, but often affect the degree of hysteresis, possibly acting as charge traps. Satisfactory device performances were obtained from polymer with palladium levels of 2000 μg/g suggesting that complete removal of metal residues may not be necessary for satisfactory device performance.

Analysis of size quantization and temperature effects on the threshold voltage of thin silicon film double-gate metal-oxide-semiconductor field-effect transistor (MOSFET)

In this paper, we analyze the combined effects of size quantization and device temperature variations (T = 50K to 400 K) on the intrinsic carrier concentration (n(i)), electron concentration (n) and thereby on the threshold voltage (V-th) for thin silicon film (t(si) = 1 nm to 10 nm) based fully-depleted Double-Gate Silicon-on-Insulator MOSFETs. The threshold voltage (V-th) is defined as the gate voltage (V-g) at which the potential at the center of the channel (Phi(c)) begins to saturate (Phi(c) = Phi(c(sat))). It is shown that in the strong quantum confinement regime (t(si) <= 3nm), the effects of size quantization far over-ride the effects of temperature variations on the total change in band-gap (Delta E-g(eff)), intrinsic carrier concentration (n(i)), electron concentration (n), Phi(c(sat)) and the threshold voltage (V-th). On the other hand, for t(si) >= 4 nm, it is shown that size quantization effects recede with increasing t(si), while the effects of temperature variations become increasingly significant. Through detailed analysis, a physical model for the threshold voltage is presented both for the undoped and doped cases valid over a wide-range of device temperatures, silicon film thicknesses and substrate doping densities. Both in the undoped and doped cases, it is shown that the threshold voltage strongly depends on the channel charge density and that it is independent of incomplete ionization effects, at lower device temperatures. The results are compared with the published work available in literature, and it is shown that the present approach incorporates quantization and temperature effects over the entire temperature range. We also present an analytical model for V-th as a function of device temperature (T). (C) 2013 AIP Publishing LLC.

Furan containing diketopyrrolopyrrole copolymers : synthesis, characterization, organic field effect transistor performance and photovoltaic properties

In this work, we report design, synthesis and characterization of solution processable low band gap polymer semiconductors, poly{3,6-difuran-2-yl-2,5-di(2- octyldodecyl)-pyrrolo[3,4-c]pyrrole-1,4-dione-alt-phenylene} (PDPP-FPF), poly{3,6-difuran-2-yl-2,5-di(2-octyldodecyl)-pyrrolo[3,4-c]pyrrole-1, 4-dione-alt-naphthalene} (PDPP-FNF) and poly{3,6-difuran-2-yl-2,5-di(2- octyldodecyl)-pyrrolo[3,4-c]pyrrole-1,4-dione-alt-anthracene} (PDPP-FAF) using the furan-containing 3,6-di(furan-2-yl)pyrrolo[3,4-c]pyrrole-1,4(2H,5H)-dione (DBF) building block. As DBF acts as an acceptor moiety, a series of donor-acceptor (D-A) copolymers can be generated when it is attached alternatively with phenylene, naphthalene or anthracene donor comonomer blocks. Optical and electrochemical characterization of thin films of these polymers reveals band gaps in the range of 1.55-1.64 eV. These polymers exhibit excellent hole mobility when used as the active layer in organic thin-film transistor (OTFT) devices. Among the series, the highest hole mobility of 0.11 cm 2 V -1 s -1 is achieved in bottom gate and top-contact OTFT devices using PDPP-FNF. When these polymers are used as a donor and [70]PCBM as the acceptor in organic photovoltaic (OPV) devices, power conversion efficiencies (PCE) of 2.5 and 2.6% are obtained for PDPP-FAF and PDPP-FNF polymers, respectively. Such mobility values in OTFTs and performance in OPV make furan-containing DBF a very promising block for designing new polymer semiconductors for a wide range of organic electronic applications.

Interfaces and traps in pentacene field-effect transistor

The equivalent circuit parameters for a pentacene organic field-effect transistor are determined from low frequency impedance measurements in the dark as well as under light illumination. The source-drain channel impedance parameters are obtained from Bode plot analysis and the deviations at low frequency are mainly due to the contact impedance. The charge accumulation at organic semiconductor-metal interface and dielectric-semiconductor interface is monitored from the response to light as an additional parameter to find out the contributions arising from photovoltaic and photoconductive effects. The shift in threshold voltage is due to the accumulation of photogenerated carriers under source-drain electrodes and at dielectric-semiconductor interface, and also this dominates the carrier transport. The charge carrier trapping at various interfaces and in the semiconductor is estimated from the dc and ac impedance measurements under illumination. (c) 2010 American Institute of Physics. doi: 10.1063/1.3517085]

Threshold voltage modeling under size quantization for ultra-thin silicon double-gate metal-oxide-semiconductor field-effect transistor

We report on the threshold voltage modeling of ultra-thin (1 nm-5 nm) silicon body double-gate (DG) MOSFETs using self-consistent Poisson-Schrodinger solver (SCHRED). We define the threshold voltage (V th) of symmetric DG MOSFETs as the gate voltage at which the center potential (Φ c) saturates to Φ c (s a t), and analyze the effects of oxide thickness (t ox) and substrate doping (N A) variations on V th. The validity of this definition is demonstrated by comparing the results with the charge transition (from weak to strong inversion) based model using SCHRED simulations. In addition, it is also shown that the proposed V t h definition, electrically corresponds to a condition where the inversion layer capacitance (C i n v) is equal to the oxide capacitance (C o x) across a wide-range of substrate doping densities. A capacitance based analytical model based on the criteria C i n v C o x is proposed to compute Φ c (s a t), while accounting for band-gap widening. This is validated through comparisons with the Poisson-Schrodinger solution. Further, we show that at the threshold voltage condition, the electron distribution (n(x)) along the depth (x) of the silicon film makes a transition from a strong single peak at the center of the silicon film to the onset of a symmetric double-peak away from the center of the silicon film. © 2012 American Institute of Physics.

Fabrication of an organic field effect transistor using nano imprinting of Ag inks and semiconducting polymers

A simple and cheap procedure for flexible electronics fabrication was demonstrated by imprinting metallic nanoparticles (NPs) on flexible substrates. Silver NPs with an average diameter of 10 nm were prepared via an improved chemical approach and Ag Np ink was produced in α-terpineol with a concentration up to 15%. Silver micro/nanostructures with a dimension varying from nanometres to microns were produced on a flexible substrate (polyimide) by imprinting the as-prepared silver ink. The fine fluidic properties of an Ag NP/α-terpineol solution and low melting temperatures of silver nanoparticles render a low pressure and low temperature procedure, which is well suited for flexible electronics fabrication. The effects of sintering and mechanical bending on the conductivity of imprinted silver contacts were also investigated. Large area organic field effect transistors (OFET) on flexible substrates were fabricated using an imprinted silver electrode and semiconducting polymer. The OFET with silver electrodes imprinted from our prepared oleic acid stabilized Ag nanoparticle ink show an ideal ohmic contact; therefore, the OFET exhibit high performance (Ion/Ioff ratio: 1 × 103; mobility: 0.071 cm2 V-1 s-1). © 2010 IOP Publishing Ltd.

A III-V channel field effect transistor for non-classical CMOS: process optimisation for improved gate stack function

This thesis describes a collection of studies into the electrical response of a III-V MOS stack comprising metal/GaGdO/GaAs layers as a function of fabrication process variables and the findings of those studies. As a result of this work, areas of improvement in the gate process module of a III-V heterostructure MOSFET were identified. Compared to traditional bulk silicon MOSFET design, one featuring a III-V channel heterostructure with a high-dielectric-constant oxide as the gate insulator provides numerous benefits, for example: the insulator can be made thicker for the same capacitance, the operating voltage can be made lower for the same current output, and improved output characteristics can be achieved without reducing the channel length further. It is known that transistors composed of III-V materials are most susceptible to damage induced by radiation and plasma processing. These devices utilise sub-10 nm gate dielectric films, which are prone to contamination, degradation and damage. Therefore, throughout the course of this work, process damage and contamination issues, as well as various techniques to mitigate or prevent those have been investigated through comparative studies of III-V MOS capacitors and transistors comprising various forms of metal gates, various thicknesses of GaGdO dielectric, and a number of GaAs-based semiconductor layer structures. Transistors which were fabricated before this work commenced, showed problems with threshold voltage control. Specifically, MOSFETs designed for normally-off (VTH > 0) operation exhibited below-zero threshold voltages. With the results obtained during this work, it was possible to gain an understanding of why the transistor threshold voltage shifts as the gate length decreases and of what pulls the threshold voltage downwards preventing normally-off device operation. Two main culprits for the negative VTH shift were found. The first was radiation damage induced by the gate metal deposition process, which can be prevented by slowing down the deposition rate. The second was the layer of gold added on top of platinum in the gate metal stack which reduces the effective work function of the whole gate due to its electronegativity properties. Since the device was designed for a platinum-only gate, this could explain the below zero VTH. This could be prevented either by using a platinum-only gate, or by matching the layer structure design and the actual gate metal used for the future devices. Post-metallisation thermal anneal was shown to mitigate both these effects. However, if post-metallisation annealing is used, care should be taken to ensure it is performed before the ohmic contacts are formed as the thermal treatment was shown to degrade the source/drain contacts. In addition, the programme of studies this thesis describes, also found that if the gate contact is deposited before the source/drain contacts, it causes a shift in threshold voltage towards negative values as the gate length decreases, because the ohmic contact anneal process affects the properties of the underlying material differently depending on whether it is covered with the gate metal or not. In terms of surface contamination; this work found that it causes device-to-device parameter variation, and a plasma clean is therefore essential. This work also demonstrated that the parasitic capacitances in the system, namely the contact periphery dependent gate-ohmic capacitance, plays a significant role in the total gate capacitance. This is true to such an extent that reducing the distance between the gate and the source/drain ohmic contacts in the device would help with shifting the threshold voltages closely towards the designed values. The findings made available by the collection of experiments performed for this work have two major applications. Firstly, these findings provide useful data in the study of the possible phenomena taking place inside the metal/GaGdO/GaAs layers and interfaces as the result of chemical processes applied to it. In addition, these findings allow recommendations as to how to best approach fabrication of devices utilising these layers.

Synthesis, characterization and organic field effect transistor performance of a diketopyrrolopyrrole-fluorenone copolymer

A diketopyrrolopyrrole (DPP) with fluorenone (FN) based low band gap alternating copolymer (PDPPT-alt-FN) has been synthesized via Suzuki coupling. PDPPT-alt-FN exhibits a deep HOMO level with a lower band gap. Fabricated organic thin film transistors using PDPPT-alt-FN as a channel semiconductor show p-channel behaviour with the highest hole mobility of 0.083 cm2 V-1 s-1 measured in air.

Density of trap states in a polymer field-effect transistor

We report a more accurate method to determine the density of trap states in a polymer field-effect transistor. In the approach, we describe in this letter, we take into consideration the sub-threshold behavior in the calculation of the density of trap states. This is very important since the sub-threshold regime of operation extends to fairly large gate voltages in these disordered semiconductor based transistors. We employ the sub-threshold drift-limited mobility model (for sub-threshold response) and the conventional linear mobility model for above threshold response. The combined use of these two models allows us to extract the density of states from charge transport data much more accurately. We demonstrate our approach by analyzing data from diketopyrrolopyrrole based co-polymer transistors with high mobility. This approach will also work well for other disordered semiconductors in which sub-threshold conduction is important.

Fabrication and characterization of polyterpenol as an insulating layer and incorporated organic field effect transistor

A non-synthetic polymer material, polyterpenol, was fabricated using a dry polymerization process namely RF plasma polymerization from an environmentally friendly monomer and its surface, optical and electrical properties investigated. Polyterpenol films were found to be transparent over the visible wavelength range, with a smooth surface with an average roughness of less than 0.4 nm and hardness of 0.4 GPa. The dielectric constant of 3.4 for polyterpenol was higher than that of the conventional polymer materials used in the organic electronic devices. The non-synthetic polymer material was then implemented as a surface modification of the gate insulator in field effect transistor (OFET) and the properties of the device were examined. In comparison to the similar device without the polymer insulating layer, the polyterpenol based OFET device showed significant improvements. The addition of the polyterpenol interlayer in the OFET shifted the threshold voltage significantly; + 20 V to -3 V. The presence of trapped charge was not observed in the polyterpenol interlayer. This assisted in the improvement of effective mobility from 0.012 to 0.021 cm 2/Vs. The switching property of the polyterpenol based OFET was also improved; 107 compared to 104. The results showed that the non-synthetic polyterpenol polymer film is a promising candidate of insulators in electronic devices.

Photoimpedance characterization of polymer field-effect transistor

The small signal ac response is measured across the source-drain terminals of poly(2,5-bis(3-tetradecylthiophen-2-yl)thieno[3,2-b]thiophene) field-effect transistor under dc bias to obtain the equivalent circuit parameters in the dark, and under a monochromatic light (540 nm) of various intensities. The numerically simulated response based on these parameters shows deviation at low frequency which is related to the charge accumulation at the interface and the contact resistance at the electrodes. This method can be used to differentiate the photophysical phenomena occurring in the bulk from that at the metal-semiconductor interface for polymer field-effect transistors. ©2009 American Institute of Physics

Ultralow noise field-effect transistor from multilayer graphene

We present low-frequency electrical resistance fluctuations, or noise, in graphene-based field-effect devices with varying number of layers. In single-layer devices, the noise magnitude decreases with increasing carrier density, which behaved oppositely in the devices with two or larger number of layers accompanied by a suppression in noise magnitude by more than two orders in the latter case. This behavior can be explained from the influence of external electric field on graphene band structure, and provides a simple transport-based route to isolate single-layer graphene devices from those with multiple layers. ©2009 American Institute of Physics

Probing top-gated field effect transistor of reduced graphene oxide monolayer made by dielectrophoresis

We demonstrate a top-gated field effect transistor made of a reduced graphene oxide (RGO) monolayer (graphene) by dielectrophoresis. The Raman spectrum of RGO flakes of typical size of 5 mu m x 5 mu m shows a single 2D band at 2687 cm(-1), characteristic of single-layer graphene.The two-probe current-voltage measurements of RGO flakes, deposited in between the patterned electrodes with a gap of 2.5 mu m using ac dielectrophoresis, show ohmic behavior with a resistance of similar to 37 k Omega. The temperature dependence of the resistance (R) of RGO measured between 305 K and 393 K yields a temperature coefficient of resistance [dR/dT]/R similar to -9.5 x 10(-4)/K, the same as that of mechanically exfoliated single-layer graphene. The field-effect transistor action was obtained by electrochemical top-gating using a solid polymer electrolyte (PEO + LiClO4) and Pt wire. The ambipolar nature of graphene flakes is observed up to a doping level of similar to 6 x 10(12)/cm(2) and carrier mobility of similar to 50 cm(2)/V s. The source-drain current characteristics show a tendency of current saturation at high source-drain voltage which is analyzed quantitatively by a diffusive transport model. (C) 2010 Elsevier Ltd. All rights reserved.