Performance study of the Galway Bay wave energy test site floating power system

The Galway Bay wave energy test site promises to be a vital resource for wave energy researchers and developers. As part of the development of this site, a floating power system is being developed to provide power and data acquisition capabilities, including its function as a local grid connection, allowing for the connection of up to three wave energy converter devices. This work shows results from scaled physical model testing and numerical modelling of the floating power system and an oscillating water column connected with an umbilical. Results from this study will be used to influence further scaled testing as well as the full scale design and build of the floating power system in Galway Bay.

Design of Scaled Bridge Prototype for Energy Harvesting Testing

Energy harvesting from ambient vibration is a promising field, especially for applications in larger infrastructures such as bridges. These structures are more frequently monitored for damage detection because of their extended life, increased traffic load and environmental deterioration. In this regard, the possibility of sourcing the power necessary for the sensors from devices embedded in the structure, thus cutting the cost due to the management of battery replacing over the lifespan of the structure, is particularly attracting. Among others, piezoelectric devices have proven to be especially effective and easy to apply since they can be bonded to existing host structure. For these devices the energy harvesting capacity is achieved directly from the variation in the strain conditions from the surface of the structure. However these systems need to undergo significant research for optimisation of their harvesting capacity and for assessing the feasibility of application to various ranges of bridge span and load. In this regard scaled bridge prototypes can be effectively used not only to assess numerical models and studies in an inexpensive and repeatable way but also to test the electronic devices under realistic field conditions. In this paper the theory of physical similitude is applied to the design of bridge beams with embedded energy harvesting systems and health monitoring sensors. It will show both how bridge beams can be scaled in such a way to apply and test energy harvesting systems and 2) how experimental data from existing bridges can be applied to prototypes in a laboratory environment. The study will be used for assessing the reliability of the system over a train bridge case study undergoing a set load cycles and induced localised damage.

Design, Construction and Testing of a Hydraulic Power Take-Off for Wave Energy Converters

This paper presents the construction, mathematical modeling and testing of a scaled universal hydraulic Power Take-Off (PTO) device for Wave Energy Converters (WECs). A specific prototype and test bench were designed and built to carry out the tests. The results obtained from these tests were used to adjust an in-house mathematical model. The PTO was initially designed to be coupled to a scaled wave energy capture device with a low speed and high torque oscillating motion and high power fluctuations. Any Energy Capture Device (ECD) that fulfils these requirements can be coupled to this PTO, provided that its scale is adequately defined depending on the rated power of the full scale prototype. The initial calibration included estimation of the pressure drops in the different components, the pressurization time of the oil inside the hydraulic cylinders and the volumetric efficiency of the complete circuit. Since the overall efficiency measured during the tests ranged from 0.69 to 0.8 and the dynamic performance of the PTO was satisfactory, the results are really promising and it is believed that this solution might prove effective in real devices.

Scaling the Costs of 404 Testing to Fit the Needs of Small Public Companies

In July of 2002, the Sarbanes-Oxley Act was passed by Congress, including section 404 which requires the auditors to test and opine on the company's internal controls. Since that time there has been much debate about whether the intended benefits of increased investor confidence and financial statement transparency trump the unexpectedly high compliance costs, especially for public companies with market-caps less than $75 million. Before these companies begin complying in the upcoming year, interest groups are calling for the requirements to be 'scaled' to better fit the needs of these companies. While auditors already are expected to scale their audit approach to each individual client, more must be done to significantly decrease the costs in order to reverse the trend of small companies foregoing listing on U.S. capital markets. Increased guidance from the PCAOB, SEC, and other related parties could help the small-cap companies and their auditors be aware of best practices. Also, exempting industries that already follow similar guidelines or are significantly injured by the compliance requirements could help. Lastly, the controversial proposal of rotational audits could be put in place if the affected parties cooperate to remove the undue burden on these small-cap companies. Without some form of significant action, the investors could soon lose the ability to buy small-cap companies in U.S. markets.

A scaled-time test method

The Pseudo-Dynamic Test Method (PDTM) is being developped currently as an alternative to the shaking table testing of large size models. However, the stepped slow execution of the former type of test has been found to be the source of important errors arising from the stress relaxation. A new continuous test method, wich allows the selection of a suitable time-scale factor in the response in order to control these errors, es proposed here. Such scaled-time response is theoretically obtained by simply augmenting the mass of the structure for wich some practical solutions are proposed.

Testing Independence in High Dimensions & Identifiability of Graphical Models

Thesis (Ph.D.)--University of Washington, 2016-06

Testing of Interposer-Based 2.5D Integrated Circuits

The unprecedented and relentless growth in the electronics industry is feeding the demand for integrated circuits (ICs) with increasing functionality and performance at minimum cost and power consumption. As predicted by Moore's law, ICs are being aggressively scaled to meet this demand. While the continuous scaling of process technology is reducing gate delays, the performance of ICs is being increasingly dominated by interconnect delays. In an effort to improve submicrometer interconnect performance, to increase packing density, and to reduce chip area and power consumption, the semiconductor industry is focusing on three-dimensional (3D) integration. However, volume production and commercial exploitation of 3D integration are not feasible yet due to significant technical hurdles.

At the present time, interposer-based 2.5D integration is emerging as a precursor to stacked 3D integration. All the dies and the interposer in a 2.5D IC must be adequately tested for product qualification. However, since the structure of 2.5D ICs is different from the traditional 2D ICs, new challenges have emerged: (1) pre-bond interposer testing, (2) lack of test access, (3) limited ability for at-speed testing, (4) high density I/O ports and interconnects, (5) reduced number of test pins, and (6) high power consumption. This research targets the above challenges and effective solutions have been developed to test both dies and the interposer.

The dissertation first introduces the basic concepts of 3D ICs and 2.5D ICs. Prior work on testing of 2.5D ICs is studied. An efficient method is presented to locate defects in a passive interposer before stacking. The proposed test architecture uses e-fuses that can be programmed to connect or disconnect functional paths inside the interposer. The concept of a die footprint is utilized for interconnect testing, and the overall assembly and test flow is described. Moreover, the concept of weighted critical area is defined and utilized to reduce test time. In order to fully determine the location of each e-fuse and the order of functional interconnects in a test path, we also present a test-path design algorithm. The proposed algorithm can generate all test paths for interconnect testing.

In order to test for opens, shorts, and interconnect delay defects in the interposer, a test architecture is proposed that is fully compatible with the IEEE 1149.1 standard and relies on an enhancement of the standard test access port (TAP) controller. To reduce test cost, a test-path design and scheduling technique is also presented that minimizes a composite cost function based on test time and the design-for-test (DfT) overhead in terms of additional through silicon vias (TSVs) and micro-bumps needed for test access. The locations of the dies on the interposer are taken into consideration in order to determine the order of dies in a test path.

To address the scenario of high density of I/O ports and interconnects, an efficient built-in self-test (BIST) technique is presented that targets the dies and the interposer interconnects. The proposed BIST architecture can be enabled by the standard TAP controller in the IEEE 1149.1 standard. The area overhead introduced by this BIST architecture is negligible; it includes two simple BIST controllers, a linear-feedback-shift-register (LFSR), a multiple-input-signature-register (MISR), and some extensions to the boundary-scan cells in the dies on the interposer. With these extensions, all boundary-scan cells can be used for self-configuration and self-diagnosis during interconnect testing. To reduce the overall test cost, a test scheduling and optimization technique under power constraints is described.

In order to accomplish testing with a small number test pins, the dissertation presents two efficient ExTest scheduling strategies that implements interconnect testing between tiles inside an system on chip (SoC) die on the interposer while satisfying the practical constraint that the number of required test pins cannot exceed the number of available pins at the chip level. The tiles in the SoC are divided into groups based on the manner in which they are interconnected. In order to minimize the test time, two optimization solutions are introduced. The first solution minimizes the number of input test pins, and the second solution minimizes the number output test pins. In addition, two subgroup configuration methods are further proposed to generate subgroups inside each test group.

Finally, the dissertation presents a programmable method for shift-clock stagger assignment to reduce power supply noise during SoC die testing in 2.5D ICs. An SoC die in the 2.5D IC is typically composed of several blocks and two neighboring blocks that share the same power rails should not be toggled at the same time during shift. Therefore, the proposed programmable method does not assign the same stagger value to neighboring blocks. The positions of all blocks are first analyzed and the shared boundary length between blocks is then calculated. Based on the position relationships between the blocks, a mathematical model is presented to derive optimal result for small-to-medium sized problems. For larger designs, a heuristic algorithm is proposed and evaluated.

In summary, the dissertation targets important design and optimization problems related to testing of interposer-based 2.5D ICs. The proposed research has led to theoretical insights, experiment results, and a set of test and design-for-test methods to make testing effective and feasible from a cost perspective.

The Hurst exponent as an indicator of the behaviour of a model monopile in an ocean wave testing basin

With the importance of renewable energy well-established worldwide, and targets of such energy quantified in many cases, there exists a considerable interest in the assessment of wind and wave devices. While the individual components of these devices are often relatively well understood and the aspects of energy generation well researched, there seems to be a gap in the understanding of these devices as a whole and especially in the field of their dynamic responses under operational conditions. The mathematical modelling and estimation of their dynamic responses are more evolved but research directed towards testing of these devices still requires significant attention. Model-free indicators of the dynamic responses of these devices are important since it reflects the as-deployed behaviour of the devices when the exposure conditions are scaled reasonably correctly, along with the structural dimensions. This paper demonstrates how the Hurst exponent of the dynamic responses of a monopile exposed to different exposure conditions in an ocean wave basin can be used as a model-free indicator of various responses. The scaled model is exposed to Froude scaled waves and tested under different exposure conditions. The analysis and interpretation is carried out in a model-free and output-only environment, with only some preliminary ideas regarding the input of the system. The analysis indicates how the Hurst exponent can be an interesting descriptor to compare and contrast various scenarios of dynamic response conditions.