Systematic delay-driven power optimisation and power-driven delay optimisation of combinational circuits

With the proliferation of mobile wireless communication and embedded systems, the energy efficiency becomes a major design constraint. The dissipated energy is often referred as the product of power dissipation and the input-output delay. Most of electronic design automation techniques focus on optimising only one of these parameters either power or delay. Industry standard design flows integrate systematic methods of optimising either area or timing while for power consumption optimisation one often employs heuristics which are characteristic to a specific design. In this work we answer three questions in our quest to provide a systematic approach to joint power and delay Optimisation. The first question of our research is: How to build a design flow which incorporates academic and industry standard design flows for power optimisation? To address this question, we use a reference design flow provided by Synopsys and integrate in this flow academic tools and methodologies. The proposed design flow is used as a platform for analysing some novel algorithms and methodologies for optimisation in the context of digital circuits. The second question we answer is: Is possible to apply a systematic approach for power optimisation in the context of combinational digital circuits? The starting point is a selection of a suitable data structure which can easily incorporate information about delay, power, area and which then allows optimisation algorithms to be applied. In particular we address the implications of a systematic power optimisation methodologies and the potential degradation of other (often conflicting) parameters such as area or the delay of implementation. Finally, the third question which this thesis attempts to answer is: Is there a systematic approach for multi-objective optimisation of delay and power? A delay-driven power and power-driven delay optimisation is proposed in order to have balanced delay and power values. This implies that each power optimisation step is not only constrained by the decrease in power but also the increase in delay. Similarly, each delay optimisation step is not only governed with the decrease in delay but also the increase in power. The goal is to obtain multi-objective optimisation of digital circuits where the two conflicting objectives are power and delay. The logic synthesis and optimisation methodology is based on AND-Inverter Graphs (AIGs) which represent the functionality of the circuit. The switching activities and arrival times of circuit nodes are annotated onto an AND-Inverter Graph under the zero and a non-zero-delay model. We introduce then several reordering rules which are applied on the AIG nodes to minimise switching power or longest path delay of the circuit at the pre-technology mapping level. The academic Electronic Design Automation (EDA) tool ABC is used for the manipulation of AND-Inverter Graphs. We have implemented various combinatorial optimisation algorithms often used in Electronic Design Automation such as Simulated Annealing and Uniform Cost Search Algorithm. Simulated Annealing (SMA) is a probabilistic meta heuristic for the global optimization problem of locating a good approximation to the global optimum of a given function in a large search space. We used SMA to probabilistically decide between moving from one optimised solution to another such that the dynamic power is optimised under given delay constraints and the delay is optimised under given power constraints. A good approximation to the global optimum solution of energy constraint is obtained. Uniform Cost Search (UCS) is a tree search algorithm used for traversing or searching a weighted tree, tree structure, or graph. We have used Uniform Cost Search Algorithm to search within the AIG network, a specific AIG node order for the reordering rules application. After the reordering rules application, the AIG network is mapped to an AIG netlist using specific library cells. Our approach combines network re-structuring, AIG nodes reordering, dynamic power and longest path delay estimation and optimisation and finally technology mapping to an AIG netlist. A set of MCNC Benchmark circuits and large combinational circuits up to 100,000 gates have been used to validate our methodology. Comparisons for power and delay optimisation are made with the best synthesis scripts used in ABC. Reduction of 23% in power and 15% in delay with minimal overhead is achieved, compared to the best known ABC results. Also, our approach is also implemented on a number of processors with combinational and sequential components and significant savings are achieved.

Optimal static voltage stability improvement using a numerically stable SLP algorithm, for real time applications

A numerically stable sequential Primal–Dual LP algorithm for the reactive power optimisation (RPO) is presented in this article. The algorithm minimises the voltage stability index C 2 [1] of all the load buses to improve the system static voltage stability. Real time requirements such as numerical stability, identification of the most effective subset of controllers for curtailing the number of controllers and their movement can be handled effectively by the proposed algorithm. The algorithm has a natural characteristic of selecting the most effective subset of controllers (and hence curtailing insignificant controllers) for improving the objective. Comparison with transmission loss minimisation objective indicates that the most effective subset of controllers and their solution identified by the static voltage stability improvement objective is not the same as that of the transmission loss minimisation objective. The proposed algorithm is suitable for real time application for the improvement of the system static voltage stability.

Optimisation techniques for planning automatic under frequency load shedding in New Zealand’s power system

Electricity generation is vital in developed countries to power the many mechanical and electrical devices that people require. Unfortunately electricity generation is costly. Though electricity can be generated it cannot be stored efficiently. Electricity generation is also difficult to manage because exact demand is unknown from one instant to the next. A number of services are required to manage fluctuations in electricity demand, and to protect the system when frequency falls too low. A current approach is called automatic under frequency load shedding (AUFLS). This article proposes new methods for optimising AUFLS in New Zealand’s power system. The core ideas were developed during the 2015 Maths and Industry Study Group (MISG) in Brisbane, Australia. The problem has been motivated by Transpower Limited, a company that manages New Zealand’s power system and transports bulk electricity from where it is generated to where it is needed. The approaches developed in this article can be used in electrical power systems anywhere in the world.

Optimisation of fuel usage and steam availability in the power and steam plant of a paper mill

This paper presents the results of a project aimed at minimising fuel usage while maximising steam availability in the power and steam plant of a large newsprint mill. The approach taken was to utilise the better regulation and plant wide optimisation capabilities of Advanced Process Control, especially Model Predictive Control (MPC) techniques. These have recently made their appearance in the pulp and paper industry but are better known in the oil and petrochemical industry where they have been used for nearly 30 years. The issue in the power and steam plant is to ensure that sufficient steam is available when the paper machines require it and yet not to have to waste too much steam when one or more of the machines suffers an outage. This is a problem for which MPC is well suited. It allows variables to be kept within declared constraint ranges, a feature which has been used, effectively, to increase the steam storage capacity of the existing plant. This has resulted in less steam being condensed when it is not required and in significant reductions in the need for supplementary firing. The incidence of steam being dump-condensed while also supplementary firing the Combined Heat & Power (CHP) plant has been reduced by 95% and the overall use of supplementary firing is less than 30% of what it was. In addition the plant runs more smoothly and requires less operator time. The yearly benefit provided by the control system is greater than £200,000, measured in terms of 2005 gas prices.

Predictive optimisation of high-power IGBT switching under Active Voltage Control

Active Voltage Control (AVC) is an implementation of classic Proportional-Derivative (PD) control and multi-loop feedback control to force IGBT to follow a pre-set switching trajectory. The initial objective of AVC was mainly to synchronise the switching of IGBTs connected in series so as to realise voltage balancing between devices. For a single IGBT switching, the AVC reference needs further optimisation. Thus, a predictive manner of AVC reference generation is required to cope with the nonlinear IGBT switching parameters while performing low loss switching. In this paper, an improved AVC structure is adopted along with a revised reference which accommodates the IGBT nonlinearity during switching and is predictive based on current being switched. Experimental and simulation results show that close control of a single IGBT switching is realised. It is concluded that good performance can be obtained, but the proposed method needs careful stability analysis for parameter choice. © 2013 IEEE.