Text segmentation using a cache memory

International audience

A parallel programming model for ada

Over the last three decades, computer architects have been able to achieve an increase in performance for single processors by, e.g., increasing clock speed, introducing cache memories and using instruction level parallelism. However, because of power consumption and heat dissipation constraints, this trend is going to cease. In recent times, hardware engineers have instead moved to new chip architectures with multiple processor cores on a single chip. With multi-core processors, applications can complete more total work than with one core alone. To take advantage of multi-core processors, parallel programming models are proposed as promising solutions for more effectively using multi-core processors. This paper discusses some of the existent models and frameworks for parallel programming, leading to outline a draft parallel programming model for Ada.

The value of a small microkernel for dreamy memory and the RAMpage memory hierarchy

This paper explores potential for the RAMpage memory hierarchy to use a microkernel with a small memory footprint, in a specialized cache-speed static RAM (tightly-coupled memory, TCM). Dreamy memory is DRAM kept in low-power mode, unless referenced. Simulations show that a small microkernel suits RAMpage well, in that it achieves significantly better speed and energy gains than a standard hierarchy from adding TCM. RAMpage, in its best 128KB L2 case, gained 11% speed using TCM, and reduced energy 14%. Equivalent conventional hierarchy gains were under 1%. While 1MB L2 was significantly faster against lower-energy cases for the smaller L2, the larger SRAM's energy does not justify the speed gain. Using a 128KB L2 cache in a conventional architecture resulted in a best-case overall run time of 2.58s, compared with the best dreamy mode run time (RAMpage without context switches on misses) of 3.34s, a speed penalty of 29%. Energy in the fastest 128KB L2 case was 2.18J vs. 1.50J, a reduction of 31%. The same RAMpage configuration without dreamy mode took 2.83s as simulated, and used 2.39J, an acceptable trade-off (penalty under 10%) for being able to switch easily to a lower-energy mode.

Evaluating the SEE sensitivity of a 45nm SOI Multi-core Processor due to 14 MeV Neutrons

The aim of this work is to evaluate the SEE sensitivity of a multi-core processor having implemented ECC and parity in their cache memories. Two different application scenarios are studied. The first one configures the multi-core in Asymmetric Multi-Processing mode running a memory-bound application, whereas the second one uses the Symmetric Multi-Processsing mode running a CPU-bound application. The experiments were validated through radiation ground testing performed with 14 MeV neutrons on the Freescale P2041 multi-core manufactured in 45nm SOI technology. A deep analysis of the observed errors in cache memories was carried-out in order to reveal vulnerabilities in the cache protection mechanisms. Critical zones like tag addresses were affected during the experiments. In addition, the results show that the sensitivity strongly depends on the application and the multi-processsing mode used.

Cache-Integrated Network Interfaces: Flexible On-Chip Communication and Synchronization for Large-Scale CMPs

Per-core scratchpad memories (or local stores) allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architectures become more distributed. We have designed cache-integrated network interfaces, appropriate for scalable multicores, that combine the best of two worlds – the flexibility of caches and the efficiency of scratchpad memories: on-chip SRAM is configurably shared among caching, scratchpad, and virtualized network interface (NI) functions. This paper presents our architecture, which provides local and remote scratchpad access, to either individual words or multiword blocks through RDMA copy. Furthermore, we introduce event responses, as a technique that enables software configurable communication and synchronization primitives. We present three event response mechanisms that expose NI functionality to software, for multiword transfer initiation, completion notifications for software selected sets of arbitrary size transfers, and multi-party synchronization queues. We implemented these mechanisms in a four-core FPGA prototype, and measure the logic overhead over a cache-only design for basic NI functionality to be less than 20%. We also evaluate the on-chip communication performance on the prototype, as well as the performance of synchronization functions with simulation of CMPs with up to 128 cores. We demonstrate efficient synchronization, low-overhead communication, and amortized-overhead bulk transfers, which allow parallelization gains for fine-grain tasks, and efficient exploitation of the hardware bandwidth.

A Hierarchical Cache Coherent Protocol

As the number of processors in distributed-memory multiprocessors grows, efficiently supporting a shared-memory programming model becomes difficult. We have designed the Protocol for Hierarchical Directories (PHD) to allow shared-memory support for systems containing massive numbers of processors. PHD eliminates bandwidth problems by using a scalable network, decreases hot-spots by not relying on a single point to distribute blocks, and uses a scalable amount of space for its directories. PHD provides a shared-memory model by synthesizing a global shared memory from the local memories of processors. PHD supports sequentially consistent read, write, and test- and-set operations. This thesis also introduces a method of describing locality for hierarchical protocols and employs this method in the derivation of an abstract model of the protocol behavior. An embedded model, based on the work of Johnson[ISCA19], describes the protocol behavior when mapped to a k-ary n-cube. The thesis uses these two models to study the average height in the hierarchy that operations reach, the longest path messages travel, the number of messages that operations generate, the inter-transaction issue time, and the protocol overhead for different locality parameters, degrees of multithreading, and machine sizes. We determine that multithreading is only useful for approximately two to four threads; any additional interleaving does not decrease the overall latency. For small machines and high locality applications, this limitation is due mainly to the length of the running threads. For large machines with medium to low locality, this limitation is due mainly to the protocol overhead being too large. Our study using the embedded model shows that in situations where the run length between references to shared memory is at least an order of magnitude longer than the time to process a single state transition in the protocol, applications exhibit good performance. If separate controllers for processing protocol requests are included, the protocol scales to 32k processor machines as long as the application exhibits hierarchical locality: at least 22% of the global references must be able to be satisfied locally; at most 35% of the global references are allowed to reach the top level of the hierarchy.

Effects of visuospatial tasks on desensitization to emotive memories

Objectives. Intrusive memories of extreme trauma can disrupt a stepwise approach to imaginal exposure. Concurrent tasks that load the visuospatial sketchpad (VSSP) of working memory reduce the vividness of recalled images. This study tested whether relief of distress from competing VSSP tasks during imaginal exposure is at the cost of impaired desensitization . Design. This study examined repeated exposure to emotive memories using 18 unselected undergraduates and a within-subjects design with three exposure conditions (Eye Movement, Visual Noise, Exposure Alone) in random, counterbalanced order. Method. At baseline, participants recalled positive and negative experiences, and rated the vividness and emotiveness of each image. A different positive and negative recollection was then used for each condition. Vividness and emotiveness were rated after each of eight exposure trials. At a post-exposure session 1 week later, participants rated each image without any concurrent task. Results. Consistent with previous research, vividness and distress during imaging were lower during Eye Movements than in Exposure Alone, with passive visual interference giving intermediate results. A reduction in emotional responses from Baseline to Post was of similar size for the three conditions. Conclusion. Visuospatial tasks may offer a temporary response aid for imaginal exposure without affecting desensitization.

Lost talent collects around memories [REVIEW]

Review of 'Toy Symphony', Queensland Theatre Company, published in The Australian, 17 November 2009.

Maternal reminiscing style during early childhood predicts the age of adolescents' earliest memories

Individual differences in parental reminiscing style are hypothesized to have long-lasting effects on children’s autobiographical memory development, including the age of their earliest memories. This study represents the first prospective test of this hypothesis. Conversations about past events between 17 mother–child dyads were recorded on multiple occasions between the children’s 2nd and 4th birthdays. When these children were aged 12–13 years, they were interviewed about their early memories. Adolescents whose mothers used a greater ratio of elaborations to repetitions during the early childhood conversations had earlier memories than adolescents whose mothers used a smaller ratio of elaborations to repetitions. This finding is consistent with the hypothesis that past-event conversations during early childhood have long-lasting effects on autobiographical memory.

Preservice teachers’ memories of their secondary science education experiences

Understanding preservice teachers’ memories of their education may aid towards articulating high-impact teaching practices. This study describes 246 preservice teachers’ perceptions of their secondary science education experiences through a questionnaire and 28-item survey. ANOVA was statistically significant about participants’ memories of science with 15 of the 28 survey items. Descriptive statistics through SPSS further showed that a teacher’s enthusiastic nature (87%) and positive attitude towards science (87%) were regarded as highly memorable. In addition, explaining abstract concepts well (79%), and guiding the students’ conceptual development with practical science activities (73%) may be considered as memorable secondary science teaching strategies. Implementing science lessons with one or more of these memorable science teaching practices may “make a difference” towards influencing high school students’ positive long-term memories about science and their science education. Further research in other key learning areas may provide a clearer picture of high-impact teaching and a way to enhance pedagogical practices.

Adaptive cache aware multiprocessor scheduling framework

Computer resource allocation represents a significant challenge particularly for multiprocessor systems, which consist of shared computing resources to be allocated among co-runner processes and threads. While an efficient resource allocation would result in a highly efficient and stable overall multiprocessor system and individual thread performance, ineffective poor resource allocation causes significant performance bottlenecks even for the system with high computing resources. This thesis proposes a cache aware adaptive closed loop scheduling framework as an efficient resource allocation strategy for the highly dynamic resource management problem, which requires instant estimation of highly uncertain and unpredictable resource patterns. Many different approaches to this highly dynamic resource allocation problem have been developed but neither the dynamic nature nor the time-varying and uncertain characteristics of the resource allocation problem is well considered. These approaches facilitate either static and dynamic optimization methods or advanced scheduling algorithms such as the Proportional Fair (PFair) scheduling algorithm. Some of these approaches, which consider the dynamic nature of multiprocessor systems, apply only a basic closed loop system; hence, they fail to take the time-varying and uncertainty of the system into account. Therefore, further research into the multiprocessor resource allocation is required. Our closed loop cache aware adaptive scheduling framework takes the resource availability and the resource usage patterns into account by measuring time-varying factors such as cache miss counts, stalls and instruction counts. More specifically, the cache usage pattern of the thread is identified using QR recursive least square algorithm (RLS) and cache miss count time series statistics. For the identified cache resource dynamics, our closed loop cache aware adaptive scheduling framework enforces instruction fairness for the threads. Fairness in the context of our research project is defined as a resource allocation equity, which reduces corunner thread dependence in a shared resource environment. In this way, instruction count degradation due to shared cache resource conflicts is overcome. In this respect, our closed loop cache aware adaptive scheduling framework contributes to the research field in two major and three minor aspects. The two major contributions lead to the cache aware scheduling system. The first major contribution is the development of the execution fairness algorithm, which degrades the co-runner cache impact on the thread performance. The second contribution is the development of relevant mathematical models, such as thread execution pattern and cache access pattern models, which in fact formulate the execution fairness algorithm in terms of mathematical quantities. Following the development of the cache aware scheduling system, our adaptive self-tuning control framework is constructed to add an adaptive closed loop aspect to the cache aware scheduling system. This control framework in fact consists of two main components: the parameter estimator, and the controller design module. The first minor contribution is the development of the parameter estimators; the QR Recursive Least Square(RLS) algorithm is applied into our closed loop cache aware adaptive scheduling framework to estimate highly uncertain and time-varying cache resource patterns of threads. The second minor contribution is the designing of a controller design module; the algebraic controller design algorithm, Pole Placement, is utilized to design the relevant controller, which is able to provide desired timevarying control action. The adaptive self-tuning control framework and cache aware scheduling system in fact constitute our final framework, closed loop cache aware adaptive scheduling framework. The third minor contribution is to validate this cache aware adaptive closed loop scheduling framework efficiency in overwhelming the co-runner cache dependency. The timeseries statistical counters are developed for M-Sim Multi-Core Simulator; and the theoretical findings and mathematical formulations are applied as MATLAB m-file software codes. In this way, the overall framework is tested and experiment outcomes are analyzed. According to our experiment outcomes, it is concluded that our closed loop cache aware adaptive scheduling framework successfully drives co-runner cache dependent thread instruction count to co-runner independent instruction count with an error margin up to 25% in case cache is highly utilized. In addition, thread cache access pattern is also estimated with 75% accuracy.

Stories of cross-dressing and the body : family memories in fiction

Ruth Finnegan (2006, 179) describes how family myths have the power to provoke images that recur throughout generations. This paper will document my own encounter with such persistent images in the stories of a mother and daughter. Both mother and daughter told stories about encountering cross-dressing men in the streets of Brisbane, and both showed similar anxiety over their own body size. As a creative writer working with oral histories, I found these stories of the disguised body compelling. By drawing on the storytelling strategies and preoccupations present in the interview, I used imagination and fictional techniques to investigate the possibility of symbolic resonance of memories across generations. In her novel Beloved, Toni Morrison (1987) uses the notion of ‘rememory’ to describe how characters actively make and suppress meanings in their recollections. Like Morrison, my writing speaks to notions around the way stories are remembered and told.

Legal Institutions and Collective Memories

In recent decades the debate among scholars, lawyers, politicians and others about how societies deal with their past has been constant and intensive. 'Legal Institutions and Collective Memories' situates the processes of transitional justice at the intersection between legal procedures and the production of collective and shared meanings of the past. Building upon the work of Maurice Halbwachs, this collection of essays emphasises the extended role and active involvement of contemporary law and legal institutions in public discourse about the past, and explores their impact on the shape that collective memories take in the course of time. The authors uncover a complex pattern of searching for truth, negotiating the past and cultivating the art of forgetting. Their contributions explore the ambiguous and intricate links between the production of justice, truth and memory. The essays cover a broad range of legal institutions, countries and topics. These include transitional trials as 'monumental spectacles' as well as constitutional courts, and the restitution of property rights in Central and Eastern Europe and Australia. The authors explore the biographies of victims and how their voices were repressed, as in the case of Korean Comfort Women. They explore the role of law and legal institutions in linking individual and collective memories in the transitional period through processes of lustration, and they analyse divided memories about the past and their impact on future reconciliation in South Africa. The collection offers a genuinely comparative approach, allied to cutting-edge theory.

Urban renewal, migration and memories : the affordances of place-based pedagogies for developing immigrant students’ literate repertoires

This paper reports on the new literacy demands in the middle years of schooling project in which the affordances of placed-based pedagogy are being explored through teacher inquiries and classroom-based design experiments. The school is located within a large-scale urban renewal project in which houses are being demolished and families relocated. The original school buildings have recently been demolished and replaced by a large ‘superschool’ which serves a bigger student population from a wider area. Drawing on both quantitative and qualitative data, the teachers reported that the language literacy learning of students (including a majority of students learning English as a second language) involved in the project exceeded their expectations. The project provided the motivation for them to develop their oral language repertoires, by involving them in processes such as conducting interviews with adults for their oral histories, through questioning the project manager in regular meetings, and through reporting to their peers and the wider community at school assemblies. At the same time students’ written and multimodal documentation of changes in the neighbourhood and the school grounds extended their literate and semiotic repertoires as they produced books, reports, films, powerpoints, visual designs and models of structures.