All-Optical Label Stacking: Easing the Trade-offs Between Routing and Architecture Cost in All-Optical Packet Switching

All-optical label swapping (AOLS) forms a key technology towards the implementation of all-optical packet switching nodes (AOPS) for the future optical Internet. The capital expenditures of the deployment of AOLS increases with the size of the label spaces (i.e. the number of used labels), since a special optical device is needed for each recognized label on every node. Label space sizes are affected by the way in which demands are routed. For instance, while shortest-path routing leads to the usage of fewer labels but high link utilization, minimum interference routing leads to the opposite. This paper studies all-optical label stacking (AOLStack), which is an extension of the AOLS architecture. AOLStack aims at reducing label spaces while easing the compromise with link utilization. In this paper, an integer lineal program is proposed with the objective of analyzing the softening of the aforementioned trade-off due to AOLStack. Furthermore, a heuristic aiming at finding good solutions in polynomial-time is proposed as well. Simulation results show that AOLStack either a) reduces the label spaces with a low increase in the link utilization or, similarly, b) uses better the residual bandwidth to decrease the number of labels even more

All-optical routing functionalities

All-optical solutions for switching and routing packet-based traffic are crucial for realizing a truly transparent network. To meet the increasing requirements for higher bandwidth, such optical packet switched networks may require the implementation of digital functions in the physical layer. This scenario stimulated us to research and develop innovative high-speed all-optical storage memories, focusing mainly on bistables whose state switching is triggered by a pulsed clock signal. In clocked devices, a synchronization signal is responsible for controlling the enabling of the bistable. This thesis also presents novel solutions to implement optical logic gates, which are basic building blocks of any processing system and a fundamental element for the development of complex processing functionalities. Most of the proposed schemes developed in this work are based on SOA-MZI structures due to their inherent characteristics such as, high extinction ratio, high operation speed, high integration capability and compactness. We addressed the experimental implementation of an all-optical packet routing scheme, with contention resolution capability, using interconnected SOAMZIs. The impact on the system performance of the reminiscent power of the blocked packets, from the non ideal switching performed by the SOA-MZIs, was also assessed.

Self-configuring intelligent control for short reach 100Gb/s optical packet routing

An advanced control architecture is proposed which recognizes and configures new connections, automatically performs calibration and initiates the routing of 100Gb/s data packets. The scheme is proposed for high capacity, low overhead, short reach networking. ©2005 Optical Society of America.

Self-configuring intelligent control for short reach 100Gb/s optical packet routing

An advanced control architecture is proposed which recognizes and configures new connections, automatically performs calibration and initiates the routing of 100Gb/s data packets. The scheme is proposed for high capacity, low overhead, short reach networking. © 2005 Optical Society of America.

Label space reduction in GMPLs and All-Optical Label Swapping networks

All-Optical Label Swapping (AOLS) es una tecnología clave para la implementación de nodos de conmutación completamente óptica de paquetes. Sin embargo, el costo de su desarrollo es proporcional al tamaño del espacio de etiquetas (label space). Debido a que los principios de funcionamiento de AOLS son casos particulares de los del MultiProtocol Label Switching (MPLS), esta tesis estudia métodos generales, aplicables a ambos, con el propósito de reducir el espacio de etiquetas tanto como sea posible. Modelos de programación lineal entera y heurísticas son propuestos para el caso en el que se permite apilar una etiqueta extra. Encontramos que cerca del 50% del espacio de etiquetas puede ser reducido, si se permite colocar una etiqueta extra en la pila. Además, particularmente para AOLS, encontramos que se puede reducir el espacio de etiquetas cerca al 25% si se duplica la capacidad de los enlaces y se permite re-encaminar el tráfico.