Isotopic studies of the Guerrero composite terrane, west-central Mexico: Implications for provenance of crustal rocks and genesis of ore metals

A variety of world-class mineral deposits occur in Mesozoic and Tertiary rocks of the Guerrero terrane. New Pb isotope analyses of various crustal units and ores from distinct subterranes of the Guerrero terrane are presented to trace metal sources in these deposits and infer source reservoirs. New Sr and Nd isotope results are provided to gain insight into the provenance of the crustal rocks from the Guerrero terrane. Triassic schist samples from the Arteaga Complex and Triassic-Jurassic phyllite and slate samples from the Tejupilco metamorphic suite contain radiogenic Pb (206Pb/204Pb = 18.701–19.256) relative to bulk earth models. Cretaceous sedimentary rocks of the Zihuatanejo Sequence are more radiogenic (206Pb/204Pb = 18.763–19.437) than samples from the Huetamo Sequence (206Pb/204Pb = 18.630–18.998). Tertiary intrusive rocks from La Verde, Inguaran, La Esmeralda, and El Malacate plot to the right of the average Pb crust evolution curve of Stacey and Kramers (206Pb/204Pb = 18.705–19.033). Ores from the La Verde and La Esmeralda porphyry copper deposits yield isotopic ratios (206Pb/204Pb = 18.678–18.723) that are generally less radiogenic than the host igneous rocks, but plot within the field defined by the sedimentary rocks from the Huetamo Sequence. Tertiary intrusive rocks from the Zimapan and La Negra districts in the Sierra Madre terrane plot above and to the right of the Stacey-Kramers reference line (206Pb/204Pb = 18.804–18.972). Lead isotope ratios of ore minerals from the Zimapan and La Negra skarn mines ( 206Pb/204Pb = 18.775–18.975) resemble those of the associated igneous rocks, implying a magmatic Pb input in the skarn deposits. New Sr and Nd isotope data on metamorphic rocks (87Sr/ 86Sr = 0.707757–0.726494 and 143Nd/144 Nd = 0.512109–0.512653) suggest that the basement of the Guerrero terrane originated from sources that had been derived from an old cratonic area. The narrow ranges and generally low 87Sr/86Sr ratios (0.704860–0.705755) and 143Nd/144Nd values (0.512765–0.512772) above that of bulk earth for igneous rocks from Inguaran, El Malacate, and La Esmeralda suggest a relatively low degree of crustal contamination. However, the isotopic values for the La Verde site (87Sr/86Sr = 0.708784 and 143Nd/144Nd = 0.512640) may indicate the involvement of a more evolved crustal component.

In vivo biocompatibility evaluation of composite polymeric materials for use in a novel artificial heart valve

A novel trileaflet polymer valve is a composite design of a biostable polymer poly(styrene-isobutylene-styrene) (SIBS) with a reinforcement polyethylene terephthalate (PET) fabric. Surface roughness and hydrophilicity vary with fabrication methods and influence leaflet biocompatibility. The purpose of this study was to investigate the biocompatibility of this composite material using both small animal (nonfunctional mode) and large animal (functional mode) models. Composite samples were manufactured using dip coating and solvent casting with different coating thickness (251μm and 50μm). Sample's surface was characterized through qualitative SEM observation and quantitative surface roughness analysis. A novel rat abdominal aorta model was developed to test the composite samples in a similar pulsatile flow condition as its intended use. The sample's tissue response was characterized by histological examination. Among the samples tested, the 25μm solvent-cast sample exhibited the smoothest surface and best biocompatibility in terms of tissue capsulation thickness, and was chosen as the method for fabrication of the SIBS valve. Phosphocholine was used to create a hydrophilic surface on selected composite samples, which resulted in improved blood compatibility. Four SIBS valves (two with phosphocholine modification) were implanted into sheep. Echocardiography, blood chemistry, and system pathology were conducted to evaluate the valve's performance and biocompatibility. No adverse response was identified following implantation. The average survival time was 76 days, and one sheep with the phosphocholine modified valve passed the FDA minimum requirement of 140 days with approximately 20 million cycles of valve activity. The explanted valves were observed under the aid of a dissection microscope, and evaluated via histology, SEM and X-ray. Surface cracks and calcified tissue deposition were found on the leaflets. In conclusion, we demonstrated the applicability of using a new rat abdominal aorta model for biocompatibility assessment of polymeric materials. A smooth and complete coating surface is essential for the biocompatibility of PET/SIBS composite, and surface modification using phosphocholine improves blood compatibility. Extrinsic calcification was identified on the leaflets and was associated with regions of surface cracks.

A multi-method approach for the assessment of composite indices and rankings

There is growing popularity in the use of composite indices and rankings for cross-organizational benchmarking. However, little attention has been paid to alternative methods and procedures for the computation of these indices and how the use of such methods may impact the resulting indices and rankings. This dissertation developed an approach for assessing composite indices and rankings based on the integration of a number of methods for aggregation, data transformation and attribute weighting involved in their computation. The integrated model developed is based on the simulation of composite indices using methods and procedures proposed in the area of multi-criteria decision making (MCDM) and knowledge discovery in databases (KDD). The approach developed in this dissertation was automated through an IT artifact that was designed, developed and evaluated based on the framework and guidelines of the design science paradigm of information systems research. This artifact dynamically generates multiple versions of indices and rankings by considering different methodological scenarios according to user specified parameters. The computerized implementation was done in Visual Basic for Excel 2007. Using different performance measures, the artifact produces a number of excel outputs for the comparison and assessment of the indices and rankings. In order to evaluate the efficacy of the artifact and its underlying approach, a full empirical analysis was conducted using the World Bank's Doing Business database for the year 2010, which includes ten sub-indices (each corresponding to different areas of the business environment and regulation) for 183 countries. The output results, which were obtained using 115 methodological scenarios for the assessment of this index and its ten sub-indices, indicated that the variability of the component indicators considered in each case influenced the sensitivity of the rankings to the methodological choices. Overall, the results of our multi-method assessment were consistent with the World Bank rankings except in cases where the indices involved cost indicators measured in per capita income which yielded more sensitive results. Low income level countries exhibited more sensitivity in their rankings and less agreement between the benchmark rankings and our multi-method based rankings than higher income country groups.

System-on-a-Chip (SoC) based hardware acceleration in Register Transfer Level (RTL) design

Today, modern System-on-a-Chip (SoC) systems have grown rapidly due to the increased processing power, while maintaining the size of the hardware circuit. The number of transistors on a chip continues to increase, but current SoC designs may not be able to exploit the potential performance, especially with energy consumption and chip area becoming two major concerns. Traditional SoC designs usually separate software and hardware. Thus, the process of improving the system performance is a complicated task for both software and hardware designers. The aim of this research is to develop hardware acceleration workflow for software applications. Thus, system performance can be improved with constraints of energy consumption and on-chip resource costs. The characteristics of software applications can be identified by using profiling tools. Hardware acceleration can have significant performance improvement for highly mathematical calculations or repeated functions. The performance of SoC systems can then be improved, if the hardware acceleration method is used to accelerate the element that incurs performance overheads. The concepts mentioned in this study can be easily applied to a variety of sophisticated software applications. The contributions of SoC-based hardware acceleration in the hardware-software co-design platform include the following: (1) Software profiling methods are applied to H.264 Coder-Decoder (CODEC) core. The hotspot function of aimed application is identified by using critical attributes such as cycles per loop, loop rounds, etc. (2) Hardware acceleration method based on Field-Programmable Gate Array (FPGA) is used to resolve system bottlenecks and improve system performance. The identified hotspot function is then converted to a hardware accelerator and mapped onto the hardware platform. Two types of hardware acceleration methods – central bus design and co-processor design, are implemented for comparison in the proposed architecture. (3) System specifications, such as performance, energy consumption, and resource costs, are measured and analyzed. The trade-off of these three factors is compared and balanced. Different hardware accelerators are implemented and evaluated based on system requirements. 4) The system verification platform is designed based on Integrated Circuit (IC) workflow. Hardware optimization techniques are used for higher performance and less resource costs. Experimental results show that the proposed hardware acceleration workflow for software applications is an efficient technique. The system can reach 2.8X performance improvements and save 31.84% energy consumption by applying the Bus-IP design. The Co-processor design can have 7.9X performance and save 75.85% energy consumption.

System-on-a-Chip (SoC) based Hardware Acceleration in Register Transfer Level (RTL) Design

Today, modern System-on-a-Chip (SoC) systems have grown rapidly due to the increased processing power, while maintaining the size of the hardware circuit. The number of transistors on a chip continues to increase, but current SoC designs may not be able to exploit the potential performance, especially with energy consumption and chip area becoming two major concerns. Traditional SoC designs usually separate software and hardware. Thus, the process of improving the system performance is a complicated task for both software and hardware designers. The aim of this research is to develop hardware acceleration workflow for software applications. Thus, system performance can be improved with constraints of energy consumption and on-chip resource costs. The characteristics of software applications can be identified by using profiling tools. Hardware acceleration can have significant performance improvement for highly mathematical calculations or repeated functions. The performance of SoC systems can then be improved, if the hardware acceleration method is used to accelerate the element that incurs performance overheads. The concepts mentioned in this study can be easily applied to a variety of sophisticated software applications. The contributions of SoC-based hardware acceleration in the hardware-software co-design platform include the following: (1) Software profiling methods are applied to H.264 Coder-Decoder (CODEC) core. The hotspot function of aimed application is identified by using critical attributes such as cycles per loop, loop rounds, etc. (2) Hardware acceleration method based on Field-Programmable Gate Array (FPGA) is used to resolve system bottlenecks and improve system performance. The identified hotspot function is then converted to a hardware accelerator and mapped onto the hardware platform. Two types of hardware acceleration methods – central bus design and co-processor design, are implemented for comparison in the proposed architecture. (3) System specifications, such as performance, energy consumption, and resource costs, are measured and analyzed. The trade-off of these three factors is compared and balanced. Different hardware accelerators are implemented and evaluated based on system requirements. 4) The system verification platform is designed based on Integrated Circuit (IC) workflow. Hardware optimization techniques are used for higher performance and less resource costs. Experimental results show that the proposed hardware acceleration workflow for software applications is an efficient technique. The system can reach 2.8X performance improvements and save 31.84% energy consumption by applying the Bus-IP design. The Co-processor design can have 7.9X performance and save 75.85% energy consumption.

Use of Fiber Reinforced Polymer Composite Cable for Post-tensioning Application

Corrosion of steel tendons is a major problem for post-tensioned concrete, especially because corrosion of the steel strands is often hard to detect inside grouted ducts. Non-metallic tendons can serve as an alternative material to steel for post-tensioning applications. Carbon fiber reinforced polymer (CFRP), given its higher strength and elastic modulus, as well as excellent durability and fatigue strength, is the most practical option for post-tensioning applications. The primary objective of this research project was to assess the feasibility of the use of innovative carbon fiber reinforced polymer (CFRP) tendons and to develop guidelines for CFRP in post-tensioned bridge applications, including segmental bridges and pier caps. An experimental investigation and a numerical simulation were conducted to compare the performance of a scaled segmental bridge model, post-tensioned with two types of carbon fiber strands and steel strands. The model was tested at different prestress levels and at different loading configurations. While the study confirms feasibility of both types of carbon fiber strands for segmental bridge applications, and their similar serviceability behavior, strands with higher elastic modulus could improve structural performance and minimize displacements beyond service loads. As the second component of the project, a side-by-side comparison of two types of carbon fiber strands against steel strands was conducted in a scaled pier cap model. Two different strand arrangements were used for post-tensioning, with eight and six strands, respectively representing an over-design and a slight under-design relative to the factored demand. The model was tested under service and factored loads. The investigation confirmed the feasibility of using carbon fiber strands in unbonded post-tensioning of pier caps. Considering both serviceability and overload conditions, the general performance of the pier cap model was deemed acceptable using either type of carbon fiber strands and quite comparable to that of steel strands. In another component of this research, creep stress tests were conducted with carbon fiber composite cable (CFCC). The anchorages for all the specimens were prepared using a commercially available expansive grout. Specimens withstood 95% of the guaranteed capacity provided by the manufacturer for a period of five months, without any sign of rupture.