System-on-a-Chip (SoC) based hardware acceleration in Register Transfer Level (RTL) design

Today, modern System-on-a-Chip (SoC) systems have grown rapidly due to the increased processing power, while maintaining the size of the hardware circuit. The number of transistors on a chip continues to increase, but current SoC designs may not be able to exploit the potential performance, especially with energy consumption and chip area becoming two major concerns. Traditional SoC designs usually separate software and hardware. Thus, the process of improving the system performance is a complicated task for both software and hardware designers. The aim of this research is to develop hardware acceleration workflow for software applications. Thus, system performance can be improved with constraints of energy consumption and on-chip resource costs. The characteristics of software applications can be identified by using profiling tools. Hardware acceleration can have significant performance improvement for highly mathematical calculations or repeated functions. The performance of SoC systems can then be improved, if the hardware acceleration method is used to accelerate the element that incurs performance overheads. The concepts mentioned in this study can be easily applied to a variety of sophisticated software applications. The contributions of SoC-based hardware acceleration in the hardware-software co-design platform include the following: (1) Software profiling methods are applied to H.264 Coder-Decoder (CODEC) core. The hotspot function of aimed application is identified by using critical attributes such as cycles per loop, loop rounds, etc. (2) Hardware acceleration method based on Field-Programmable Gate Array (FPGA) is used to resolve system bottlenecks and improve system performance. The identified hotspot function is then converted to a hardware accelerator and mapped onto the hardware platform. Two types of hardware acceleration methods – central bus design and co-processor design, are implemented for comparison in the proposed architecture. (3) System specifications, such as performance, energy consumption, and resource costs, are measured and analyzed. The trade-off of these three factors is compared and balanced. Different hardware accelerators are implemented and evaluated based on system requirements. 4) The system verification platform is designed based on Integrated Circuit (IC) workflow. Hardware optimization techniques are used for higher performance and less resource costs. Experimental results show that the proposed hardware acceleration workflow for software applications is an efficient technique. The system can reach 2.8X performance improvements and save 31.84% energy consumption by applying the Bus-IP design. The Co-processor design can have 7.9X performance and save 75.85% energy consumption.

System-on-a-Chip (SoC) based Hardware Acceleration in Register Transfer Level (RTL) Design

Today, modern System-on-a-Chip (SoC) systems have grown rapidly due to the increased processing power, while maintaining the size of the hardware circuit. The number of transistors on a chip continues to increase, but current SoC designs may not be able to exploit the potential performance, especially with energy consumption and chip area becoming two major concerns. Traditional SoC designs usually separate software and hardware. Thus, the process of improving the system performance is a complicated task for both software and hardware designers. The aim of this research is to develop hardware acceleration workflow for software applications. Thus, system performance can be improved with constraints of energy consumption and on-chip resource costs. The characteristics of software applications can be identified by using profiling tools. Hardware acceleration can have significant performance improvement for highly mathematical calculations or repeated functions. The performance of SoC systems can then be improved, if the hardware acceleration method is used to accelerate the element that incurs performance overheads. The concepts mentioned in this study can be easily applied to a variety of sophisticated software applications. The contributions of SoC-based hardware acceleration in the hardware-software co-design platform include the following: (1) Software profiling methods are applied to H.264 Coder-Decoder (CODEC) core. The hotspot function of aimed application is identified by using critical attributes such as cycles per loop, loop rounds, etc. (2) Hardware acceleration method based on Field-Programmable Gate Array (FPGA) is used to resolve system bottlenecks and improve system performance. The identified hotspot function is then converted to a hardware accelerator and mapped onto the hardware platform. Two types of hardware acceleration methods – central bus design and co-processor design, are implemented for comparison in the proposed architecture. (3) System specifications, such as performance, energy consumption, and resource costs, are measured and analyzed. The trade-off of these three factors is compared and balanced. Different hardware accelerators are implemented and evaluated based on system requirements. 4) The system verification platform is designed based on Integrated Circuit (IC) workflow. Hardware optimization techniques are used for higher performance and less resource costs. Experimental results show that the proposed hardware acceleration workflow for software applications is an efficient technique. The system can reach 2.8X performance improvements and save 31.84% energy consumption by applying the Bus-IP design. The Co-processor design can have 7.9X performance and save 75.85% energy consumption.

In-Vivo Corrosion and Fretting of Modular TI-6AL-4V/CO-CR-MO Hip Prostheses: The Influence of Microstructure and Design Parameters

The purpose of this study was to evaluate the incidence of corrosion and fretting in 48 retrieved titanium-6aluminum-4vanadium and/or cobalt-chromium-molybdenum modular total hip prosthesis with respect to alloy material microstructure and design parameters. The results revealed vastly different performance results for the wide array of microstructures examined. Severe corrosion/fretting was seen in 100% of as-cast, 24% of low carbon wrought, 9% of high carbon wrought and 5% of solution heat treated cobalt-chrome. Severe corrosion/fretting was observed in 60% of Ti-6Al-4V components. Design features which allow for fluid entry and stagnation, amplification of contact pressure and/or increased micromotion were also shown to play a role. 75% of prosthesis with high femoral head-trunnion offset exhibited poor performance compared to 15% with a low offset. Large femoral heads (>32mm) did not exhibit poor corrosion or fretting. Implantation time was not sufficient to cause poor performance; 54% of prosthesis with greater than 10 years in-vivo demonstrated none or mild corrosion/fretting.

Design and analysis of micro-channel heat-exchanger embedded in Low Temperature Co-fire Ceramic (LTCC)

Increased device density, switching speeds of integrated circuits and decrease in package size is placing new demands for high power thermal-management. The convectional method of forced air cooling with passive heat sink can handle heat fluxes up-to 3-5W/cm2; however current microprocessors are operating at levels of 100W/cm2, This demands the usage of novel thermal-management systems. In this work, water-cooling systems with active heat sink are embedded in the substrate. The research involved fabricating LTCC substrates of various configurations - an open-duct substrate, the second with thermal vias and the third with thermal vias and free-standing metal columns and metal foil. Thermal testing was performed experimentally and these results are compared with CFD results. An overall thermal resistance for the base substrate is demonstrated to be 3.4oC/W-cm2. Addition of thermal vias reduces the effective resistance of the system by 7times and further addition of free standing columns reduced it by 20times.

What Google Maps can do for Biomedical Data Dissemination: Examples and a Design Study

Background: Biologists often need to assess whether unfamiliar datasets warrant the time investment required for more detailed exploration. Basing such assessments on brief descriptions provided by data publishers is unwieldy for large datasets that contain insights dependent on specific scientific questions. Alternatively, using complex software systems for a preliminary analysis may be deemed as too time consuming in itself, especially for unfamiliar data types and formats. This may lead to wasted analysis time and discarding of potentially useful data. Results: We present an exploration of design opportunities that the Google Maps interface offers to biomedical data visualization. In particular, we focus on synergies between visualization techniques and Google Maps that facilitate the development of biological visualizations which have both low-overhead and sufficient expressivity to support the exploration of data at multiple scales. The methods we explore rely on displaying pre-rendered visualizations of biological data in browsers, with sparse yet powerful interactions, by using the Google Maps API. We structure our discussion around five visualizations: a gene co-regulation visualization, a heatmap viewer, a genome browser, a protein interaction network, and a planar visualization of white matter in the brain. Feedback from collaborative work with domain experts suggests that our Google Maps visualizations offer multiple, scale-dependent perspectives and can be particularly helpful for unfamiliar datasets due to their accessibility. We also find that users, particularly those less experienced with computer use, are attracted by the familiarity of the Google Maps API. Our five implementations introduce design elements that can benefit visualization developers. Conclusions: We describe a low-overhead approach that lets biologists access readily analyzed views of unfamiliar scientific datasets. We rely on pre-computed visualizations prepared by data experts, accompanied by sparse and intuitive interactions, and distributed via the familiar Google Maps framework. Our contributions are an evaluation demonstrating the validity and opportunities of this approach, a set of design guidelines benefiting those wanting to create such visualizations, and five concrete example visualizations.

Can Compensation Committees Effectively Mitigate the CEO Horizon Problem? The Role of Co-opted Directors

Extant research finds inconclusive evidence about the CEO horizon problem. One possibility is that compensation committees design CEO compensation in a way that discourages retiring CEOs from opportunistic earnings management and R&D reduction. However, compensation committees dominated by co-opted directors may not be as effective as those with fewer co-opted directors in mitigating the CEO horizon problem, because directors co-opted by the CEO tend to bias their decisions in favor of the CEO. I find that compensation committees dominated by co-opted directors are associated with higher CEO compensation packages. I document R&D reduction and accruals management in firms with retiring CEOs and compensation committees dominated by co-opted directors, and find that R&D reduction and income-increasing accruals are less discouraged by compensation committees dominated by co-opted directors when deciding CEO compensation. I also examine the effect of boards of directors and compensation committee characteristics on CEO compensation and on mitigating the CEO horizon problem. I find that CEO compensation positively associates with CEO power, director independence, and the percentage of busy directors, and negatively associates with board of directors and committee size and director ownership. Moreover, I find that retiring CEOs are more likely to reduce R&D expenditures when CEOs have more power, and director tenure is longer; retiring CEOs in firms with large boards of directors and compensation committees are less likely to manage accruals.

An Institutional, Socio-economic, and Legal Analysis of Fisheries Co-management and Regulation in the Gulf of Nicoya, Costa Rica

Marine Areas for Responsible Artisanal Fishing (AMPR) have emerged as a new model for co-managing small-scale fisheries in Costa Rica, one that involves collaboration between fishers, government agencies and NGOs. This thesis aims to examine the context for collective action and co-management by small-scale fishers; evaluate the design, implementation, and enforcement of AMPRs; and conduct a linguistic analysis of fisheries legislation. The present work relies on the analysis of several types of qualitative data, including interviews with 23 key informants, rapid rural assessments, and legal documents. Findings demonstrate the strong influence of economic factors for sustaining collective action, as well as the importance of certain types of external organizations for community development and co-management. Additionally, significant enforcement gaps and institutional deficiencies were identified in the work of regulating agencies. Legal analysis suggests that mechanisms for government accountability are unavailable and that legal discourse reflects some of the most salient problems in management.