Genetic individualization of Cannabis sativa by a short tandem repeat multiplex system

Cannabis sativa is the most frequently used of all illicit drugs in the United States. Cannabis has been used throughout history for its stems in the production of hemp fiber, for its seed for oil and food, and for its buds and leaves as a psychoactive drug. Short tandem repeats (STRs), were chosen as molecular markers because of their distinct advantages over other genetic methods. STRs are co-dominant, can be standardized such that reproducibility between laboratories can be easily achieved, have a high discrimination power and can be multiplexed. ^ In this study, six STR markers previously described for Cannabis were multiplexed into one reaction. The multiplex reaction was able to individualize 98 Cannabis samples (14 hemp and 84 marijuana, authenticated as originating from 33 of the 50 United States) and detect 29 alleles averaging 4.8 alleles per loci. The data did not relate the samples from the same state to each other. This is the first study to report a single reaction six-plex and apply it to the analysis of almost 100 Cannabis samples of known geographic collection site. ^

New fuel cells system for portable application with low temperature cofired ceramic (LTCC) technology

Miniature direct methanol fuel cells (DMFCs) are promising micro power sources for portable appliction. Low temperature cofired ceramic (LTCC), a competitive technology for current MEMS based fabrication, provides cost-effective mass manufacturing route for miniature DMFCs. Porous silver tape is adapted as electrodes to replace the traditional porous carbon electrodes due to its compatibility to LTCC processing and other electrochemical advantages. Electrochemical evaluation of silver under DMFCs operating conditions demonstrated that silver is a good electrode for DMFCs because of its reasonable corrosion resistance, low passivating current, and enhanced catalytic effect. Two catalyst loading methods (cofiring and postfiring) of the platinum and ruthenium catalysts are evaluated for LTCC based processing. The electrochemical analysis exhibits that the cofired path out-performs the postfiring path both at the anode and cathode. The reason is the formation of high surface area precipitated whiskers. Self-constraint sintering is utilized to overcome the difficulties of the large difference of coefficient of thermal expansion (CTE) between silver and LTCC (Dupont 951) tape during cofiring. The graphite sheet employed as a cavity fugitive insert guarantees cavity dimension conservation. Finally, performance of the membrane electrode assembly (MEA) with the porous silver electrode in the regular graphite electrode based cell and the integrated cofired cell is measured under passive fuel feeding condition. The MEA of the regular cell performs better as the electrode porosity and temperature increased. The power density of 10 mWcm-2 was obtained at ambient conditions with 1M methanol and it increased to 16 mWcm -2 at 50°C from an open circuit voltage of 0.58V. For the integrated prototype cell, the best performance, which depends on the balance methanol crossover and mass transfer at different temperatures and methanol concentrations, reaches 1.13 mWcm-2 at 2M methanol solution at ambient pressure. The porous media pore structure increases the methanol crossover resistance. As temperature increased to 60°C, the device increases to 2.14 mWcm-2.

System-on-a-Chip (SoC) based hardware acceleration in Register Transfer Level (RTL) design

Today, modern System-on-a-Chip (SoC) systems have grown rapidly due to the increased processing power, while maintaining the size of the hardware circuit. The number of transistors on a chip continues to increase, but current SoC designs may not be able to exploit the potential performance, especially with energy consumption and chip area becoming two major concerns. Traditional SoC designs usually separate software and hardware. Thus, the process of improving the system performance is a complicated task for both software and hardware designers. The aim of this research is to develop hardware acceleration workflow for software applications. Thus, system performance can be improved with constraints of energy consumption and on-chip resource costs. The characteristics of software applications can be identified by using profiling tools. Hardware acceleration can have significant performance improvement for highly mathematical calculations or repeated functions. The performance of SoC systems can then be improved, if the hardware acceleration method is used to accelerate the element that incurs performance overheads. The concepts mentioned in this study can be easily applied to a variety of sophisticated software applications. The contributions of SoC-based hardware acceleration in the hardware-software co-design platform include the following: (1) Software profiling methods are applied to H.264 Coder-Decoder (CODEC) core. The hotspot function of aimed application is identified by using critical attributes such as cycles per loop, loop rounds, etc. (2) Hardware acceleration method based on Field-Programmable Gate Array (FPGA) is used to resolve system bottlenecks and improve system performance. The identified hotspot function is then converted to a hardware accelerator and mapped onto the hardware platform. Two types of hardware acceleration methods – central bus design and co-processor design, are implemented for comparison in the proposed architecture. (3) System specifications, such as performance, energy consumption, and resource costs, are measured and analyzed. The trade-off of these three factors is compared and balanced. Different hardware accelerators are implemented and evaluated based on system requirements. 4) The system verification platform is designed based on Integrated Circuit (IC) workflow. Hardware optimization techniques are used for higher performance and less resource costs. Experimental results show that the proposed hardware acceleration workflow for software applications is an efficient technique. The system can reach 2.8X performance improvements and save 31.84% energy consumption by applying the Bus-IP design. The Co-processor design can have 7.9X performance and save 75.85% energy consumption.

Specific Increase in MDR1 Mediated Drug-Efflux in Human Brain Endothelial Cells following Co-Exposure to HIV-1 and Saquinavir

Persistence of HIV-1 reservoirs within the Central Nervous System (CNS) remains a significant challenge to the efficacy of potent anti-HIV-1 drugs. The primary human Brain Microvascular Endothelial Cells (HBMVEC) constitutes the Blood Brain Barrier (BBB) which interferes with anti-HIV drug delivery into the CNS. The ATP binding cassette (ABC) transporters expressed on HBMVEC can efflux HIV-1 protease inhibitors (HPI), enabling the persistence of HIV-1 in CNS. Constitutive low level expression of several ABC-transporters, such as MDR1 (a.k.a. P-gp) and MRPs are documented in HBMVEC. Although it is recognized that inflammatory cytokines and exposure to xenobiotic drug substrates (e.g HPI) can augment the expression of these transporters, it is not known whether concomitant exposure to virus and anti-retroviral drugs can increase drug-efflux functions in HBMVEC. Our in vitro studies showed that exposure of HBMVEC to HIV-1 significantly up-regulates both MDR1 gene expression and protein levels; however, no significant increases in either MRP-1 or MRP-2 were observed. Furthermore, calcein-AM dye-efflux assays using HBMVEC showed that, compared to virus exposure alone, the MDR1 mediated drug-efflux function was significantly induced following concomitant exposure to both HIV-1 and saquinavir (SQV). This increase in MDR1 mediated drug-efflux was further substantiated via increased intracellular retention of radiolabeled [3H-] SQV. The crucial role of MDR1 in 3H-SQV efflux from HBMVEC was further confirmed by using both a MDR1 specific blocker (PSC-833) and MDR1 specific siRNAs. Therefore, MDR1 specific drug-efflux function increases in HBMVEC following co-exposure to HIV-1 and SQV which can reduce the penetration of HPIs into the infected brain reservoirs of HIV-1. A targeted suppression of MDR1 in the BBB may thus provide a novel strategy to suppress residual viral replication in the CNS, by augmenting the therapeutic efficacy of HAART drugs.

Design and analysis of micro-channel heat-exchanger embedded in Low Temperature Co-fire Ceramic (LTCC)

Increased device density, switching speeds of integrated circuits and decrease in package size is placing new demands for high power thermal-management. The convectional method of forced air cooling with passive heat sink can handle heat fluxes up-to 3-5W/cm2; however current microprocessors are operating at levels of 100W/cm2, This demands the usage of novel thermal-management systems. In this work, water-cooling systems with active heat sink are embedded in the substrate. The research involved fabricating LTCC substrates of various configurations - an open-duct substrate, the second with thermal vias and the third with thermal vias and free-standing metal columns and metal foil. Thermal testing was performed experimentally and these results are compared with CFD results. An overall thermal resistance for the base substrate is demonstrated to be 3.4oC/W-cm2. Addition of thermal vias reduces the effective resistance of the system by 7times and further addition of free standing columns reduced it by 20times.

System-on-a-Chip (SoC) based Hardware Acceleration in Register Transfer Level (RTL) Design

Today, modern System-on-a-Chip (SoC) systems have grown rapidly due to the increased processing power, while maintaining the size of the hardware circuit. The number of transistors on a chip continues to increase, but current SoC designs may not be able to exploit the potential performance, especially with energy consumption and chip area becoming two major concerns. Traditional SoC designs usually separate software and hardware. Thus, the process of improving the system performance is a complicated task for both software and hardware designers. The aim of this research is to develop hardware acceleration workflow for software applications. Thus, system performance can be improved with constraints of energy consumption and on-chip resource costs. The characteristics of software applications can be identified by using profiling tools. Hardware acceleration can have significant performance improvement for highly mathematical calculations or repeated functions. The performance of SoC systems can then be improved, if the hardware acceleration method is used to accelerate the element that incurs performance overheads. The concepts mentioned in this study can be easily applied to a variety of sophisticated software applications. The contributions of SoC-based hardware acceleration in the hardware-software co-design platform include the following: (1) Software profiling methods are applied to H.264 Coder-Decoder (CODEC) core. The hotspot function of aimed application is identified by using critical attributes such as cycles per loop, loop rounds, etc. (2) Hardware acceleration method based on Field-Programmable Gate Array (FPGA) is used to resolve system bottlenecks and improve system performance. The identified hotspot function is then converted to a hardware accelerator and mapped onto the hardware platform. Two types of hardware acceleration methods – central bus design and co-processor design, are implemented for comparison in the proposed architecture. (3) System specifications, such as performance, energy consumption, and resource costs, are measured and analyzed. The trade-off of these three factors is compared and balanced. Different hardware accelerators are implemented and evaluated based on system requirements. 4) The system verification platform is designed based on Integrated Circuit (IC) workflow. Hardware optimization techniques are used for higher performance and less resource costs. Experimental results show that the proposed hardware acceleration workflow for software applications is an efficient technique. The system can reach 2.8X performance improvements and save 31.84% energy consumption by applying the Bus-IP design. The Co-processor design can have 7.9X performance and save 75.85% energy consumption.

Electrochemical Immunosensing of Cortisol in an Automated Microfluidic System Towards Point-of-Care Applications

This dissertation describes the development of a label-free, electrochemical immunosensing platform integrated into a low-cost microfluidic system for the sensitive, selective and accurate detection of cortisol, a steroid hormone co-related with many physiological disorders. Abnormal levels of cortisol is indicative of conditions such as Cushing’s syndrome, Addison’s disease, adrenal insufficiencies and more recently post-traumatic stress disorder (PTSD). Electrochemical detection of immuno-complex formation is utilized for the sensitive detection of Cortisol using Anti-Cortisol antibodies immobilized on sensing electrodes. Electrochemical detection techniques such as cyclic voltammetry (CV) and electrochemical impedance spectroscopy (EIS) have been utilized for the characterization and sensing of the label-free detection of Cortisol. The utilization of nanomaterial’s as the immobilizing matrix for Anti-cortisol antibodies that leads to improved sensor response has been explored. A hybrid nano-composite of Polyanaline-Ag/AgO film has been fabricated onto Au substrate using electrophoretic deposition for the preparation of electrochemical immunosening of cortisol. Using a conventional 3-electrode electrochemical cell, a linear sensing range of 1pM to 1µM at a sensitivity of 66µA/M and detection limit of 0.64pg/mL has been demonstrated for detection of cortisol. Alternately, a self-assembled monolayer (SAM) of dithiobis(succinimidylpropionte) (DTSP) has been fabricated for the modification of sensing electrode to immobilize with Anti-Cortisol antibodies. To increase the sensitivity at lower detection limit and to develop a point-of-care sensing platform, the DTSP-SAM has been fabricated on micromachined interdigitated microelectrodes (µIDE). Detection of cortisol is demonstrated at a sensitivity of 20.7µA/M and detection limit of 10pg/mL for a linear sensing range of 10pM to 200nM using the µIDE’s. A simple, low-cost microfluidic system is designed using low-temperature co-fired ceramics (LTCC) technology for the integration of the electrochemical cortisol immunosensor and automation of the immunoassay. For the first time, the non-specific adsorption of analyte on LTCC has been characterized for microfluidic applications. The design, fabrication technique and fluidic characterization of the immunoassay are presented. The DTSP-SAM based electrochemical immunosensor on µIDE is integrated into the LTCC microfluidic system and cortisol detection is achieved in the microfluidic system in a fully automated assay. The fully automated microfluidic immunosensor hold great promise for accurate, sensitive detection of cortisol in point-of-care applications.