Analysis of the lateral diffuse metal-oxide semiconductor (LDMOS) power amplifier for cellular base stations

The primary purpose of this thesis was to present a theoretical large-signal analysis to study the power gain and efficiency of a microwave power amplifier for LS-band communications using software simulation. Power gain, efficiency, reliability, and stability are important characteristics in the power amplifier design process. These characteristics affect advance wireless systems, which require low-cost device amplification without sacrificing system performance. Large-signal modeling and input and output matching components are used for this thesis. Motorola's Electro Thermal LDMOS model is a new transistor model that includes self-heating affects and is capable of small-large signal simulations. It allows for most of the design considerations to be on stability, power gain, bandwidth, and DC requirements. The matching technique allows for the gain to be maximized at a specific target frequency. Calculations and simulations for the microwave power amplifier design were performed using Matlab and Microwave Office respectively. Microwave Office is the simulation software used in this thesis. The study demonstrated that Motorola's Electro Thermal LDMOS transistor in microwave power amplifier design process is a viable solution for common-source amplifier applications in high power base stations. The MET-LDMOS met the stability requirements for the specified frequency range without a stability-improvement model. The power gain of the amplifier circuit was improved through proper microwave matching design using input/output-matching techniques. The gain and efficiency of the amplifier improve approximately 4dB and 7.27% respectively. The gain value is roughly .89 dB higher than the maximum gain specified by the MRF21010 data sheet specifications. This work can lead to efficient modeling and development of high power LDMOS transistor implementations in commercial and industry applications.

Improved Electronics for the Hall A Detectors at JLab: Summing Modules and VDC Amplifier/Discriminator Cards

Testing of summing electronics and VDC A/D Cards was performed to assure proper functioning and operation within defined parameters. In both the summing modules and the VDC A/D cards, testing for minimum threshold voltage for each channel and crosstalk between neighboring channels was performed. Additionally, the modules were installed in Hall A with input signals from shower detectors arranged to establish a trigger by summing signals together with the use of tested modules. Testing involved utilizing a pulser to mimic PMT signals, a discriminator, an attenuator, a scaler, a level translator, an oscilloscope, a high voltage power supply, and a special apparatus used to power and send signal to the A/D cards. After testing, modules were obtained that meet necessary criteria for use in the APEX experiment, and the A/D cards obtained were determined to have adequate specifications for their utilization, with specific results included in the appendix.