Weight vs magnetization enumerator for Gallager codes

We propose a method to determine the critical noise level for decoding Gallager type low density parity check error correcting codes. The method is based on the magnetization enumerator (¸M), rather than on the weight enumerator (¸W) presented recently in the information theory literature. The interpretation of our method is appealingly simple, and the relation between the different decoding schemes such as typical pairs decoding, MAP, and finite temperature decoding (MPM) becomes clear. Our results are more optimistic than those derived via the methods of information theory and are in excellent agreement with recent results from another statistical physics approach.

Magnetization enumerator for real-valued symmetric channels in Gallager error-correcting codes

Using the magnetization enumerator method, we evaluate the practical and theoretical limitations of symmetric channels with real outputs. Results are presented for several regular Gallager code constructions.

Magnetization enumerator for LDPC codes - a statistical physics approach

We propose a method based on the magnetization enumerator to determine the critical noise level for Gallager type low density parity check error correcting codes (LDPC). Our method provides an appealingly simple interpretation to the relation between different decoding schemes, and provides more optimistic critical noise levels than those reported in the information theory literature.

Asymmetrical switch costs in children

Switching between tasks produces decreases in performance as compared to repeating the same task. Asymmetrical switch costs occur when switching between two tasks of unequal difficulty. This asymmetry occurs because the cost is greater when switching to the less difficult task than when switching to the more difficult task. Various theories about the origins of these asymmetrical switch costs have emerged from numerous and detailed experiments with adults. There is no documented evidence of asymmetrical switch costs in children. We conducted a series of studies that examined age-related changes in asymmetrical switch costs, within the same paradigm. Similarities in the patterns of asymmetrical switch costs between children and adults suggested that theoretical explanations of the cognitive mechanisms driving asymmetrical switch costs in adults could be applied to children. Age-related differences indicate that these theoretical explanations need to incorporate the relative contributions and interactions of developmental processes and task mastery. © 2006 Elsevier Inc. All rights reserved.

Novel asymmetrical filtered 40 Gb/s NRZ-DPSK receiver design in a 50GHz grid

We present a novel differential phase shift keying receiver design under strong optical filtering. The receiver design is based on the different offset filtering performances of the output ports of the NRZ-DPSK Mach Zehnder Interferometer. The asymmetrical filtered receiver design can significantly increase performance by 2 dB in calculated Q for an OSNR of 15 dB.

Performance improvement of asymmetrical filtered 40GB/s RZ-DPSK receiver design-strong filtering considerations

We present a novel differential phase shift keying receiver design under strong optical filtering. The receiver design is based on asymmetrical filtering at the destructive port of the Mach Zehnder Interferometer. The asymmetrical filtered receiver design can significantly increase performance by 2 to 4.7dB in calculated "Q".

Performance improvement of asymmetrical filtered 40GB/s RZ-DPSK receiver design-strong filtering considerations

We present a novel differential phase shift keying receiver design under strong optical filtering. The receiver design is based on asymmetrical filtering at the destructive port of the Mach Zehnder Interferometer. The asymmetrical filtered receiver design can significantly increase performance by 2 to 4.7dB in calculated "Q".

Performance enhancement of partial-42.7 Gb/s DPSK via an asymmetrical receiver design

We present numerically and experimentally the combined impact of an asymmetric receiver design and a partial 42.7 Gb/s DPSK system. By implementing an optimized bit period delay at the MZI and Asymmetric filtering at the destructive port, system performance can be significantly improved by 1.8 dB for an OSNR of 20 dB. © 2013 IEEE.